mirror of https://gitee.com/openkylin/linux.git
Merge branch 'stmmac-100GB-Enterprise-MAC-support'
Jose Abreu says: ==================== net: stmmac: 100GB Enterprise MAC support Adds the support for Enterprise MAC IP version which allows operating speeds up to 100GB. Patch 1/4, adds the support in XPCS for XLGMII interface that is used in this kind of Enterprise MAC IPs. Patch 2/4, adds the XLGMII interface support in stmmac. Patch 3/4, adds the HW specific support for Enterprise MAC. We end in patch 4/4, by updating stmmac documentation to mention the support for this new IP version. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
commit
0419c450e1
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@ -32,7 +32,8 @@ is also supported.
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DesignWare(R) Cores Ethernet MAC 10/100/1000 Universal version 3.70a
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(and older) and DesignWare(R) Cores Ethernet Quality-of-Service version 4.0
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(and upper) have been used for developing this driver as well as
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DesignWare(R) Cores XGMAC - 10G Ethernet MAC.
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DesignWare(R) Cores XGMAC - 10G Ethernet MAC and DesignWare(R) Cores
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Enterprise MAC - 100G Ethernet MAC.
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This driver supports both the platform bus and PCI.
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@ -48,6 +49,8 @@ Cores Ethernet Controllers and corresponding minimum and maximum versions:
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+-------------------------------+--------------+--------------+--------------+
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| XGMAC - 10G Ethernet MAC | 2.10a | N/A | XGMAC2+ |
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+-------------------------------+--------------+--------------+--------------+
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| XLGMAC - 100G Ethernet MAC | 2.00a | N/A | XLGMAC2+ |
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+-------------------------------+--------------+--------------+--------------+
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For questions related to hardware requirements, refer to the documentation
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supplied with your Ethernet adapter. All hardware requirements listed apply
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@ -57,7 +60,7 @@ Feature List
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============
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The following features are available in this driver:
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- GMII/MII/RGMII/SGMII/RMII/XGMII Interface
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- GMII/MII/RGMII/SGMII/RMII/XGMII/XLGMII Interface
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- Half-Duplex / Full-Duplex Operation
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- Energy Efficient Ethernet (EEE)
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- IEEE 802.3x PAUSE Packets (Flow Control)
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@ -34,6 +34,11 @@
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#define DWMAC_CORE_5_00 0x50
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#define DWMAC_CORE_5_10 0x51
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#define DWXGMAC_CORE_2_10 0x21
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#define DWXLGMAC_CORE_2_00 0x20
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/* Device ID */
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#define DWXGMAC_ID 0x76
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#define DWXLGMAC_ID 0x27
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#define STMMAC_CHAN0 0 /* Always supported and default for all chips */
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@ -426,6 +431,12 @@ struct mac_link {
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u32 speed5000;
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u32 speed10000;
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} xgmii;
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struct {
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u32 speed25000;
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u32 speed40000;
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u32 speed50000;
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u32 speed100000;
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} xlgmii;
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};
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struct mii_regs {
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@ -459,6 +470,7 @@ struct mac_device_info {
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unsigned int pcs;
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unsigned int pmt;
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unsigned int ps;
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unsigned int xlgmac;
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};
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struct stmmac_rx_routing {
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@ -470,6 +482,7 @@ int dwmac100_setup(struct stmmac_priv *priv);
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int dwmac1000_setup(struct stmmac_priv *priv);
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int dwmac4_setup(struct stmmac_priv *priv);
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int dwxgmac2_setup(struct stmmac_priv *priv);
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int dwxlgmac2_setup(struct stmmac_priv *priv);
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void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
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unsigned int high, unsigned int low);
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@ -9,6 +9,7 @@
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#include <linux/iopoll.h>
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#include "stmmac.h"
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#include "stmmac_ptp.h"
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#include "dwxlgmac2.h"
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#include "dwxgmac2.h"
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static void dwxgmac2_core_init(struct mac_device_info *hw,
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@ -1485,6 +1486,67 @@ const struct stmmac_ops dwxgmac210_ops = {
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.fpe_configure = dwxgmac3_fpe_configure,
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};
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static void dwxlgmac2_rx_queue_enable(struct mac_device_info *hw, u8 mode,
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u32 queue)
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{
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void __iomem *ioaddr = hw->pcsr;
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u32 value;
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value = readl(ioaddr + XLGMAC_RXQ_ENABLE_CTRL0) & ~XGMAC_RXQEN(queue);
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if (mode == MTL_QUEUE_AVB)
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value |= 0x1 << XGMAC_RXQEN_SHIFT(queue);
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else if (mode == MTL_QUEUE_DCB)
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value |= 0x2 << XGMAC_RXQEN_SHIFT(queue);
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writel(value, ioaddr + XLGMAC_RXQ_ENABLE_CTRL0);
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}
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const struct stmmac_ops dwxlgmac2_ops = {
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.core_init = dwxgmac2_core_init,
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.set_mac = dwxgmac2_set_mac,
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.rx_ipc = dwxgmac2_rx_ipc,
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.rx_queue_enable = dwxlgmac2_rx_queue_enable,
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.rx_queue_prio = dwxgmac2_rx_queue_prio,
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.tx_queue_prio = dwxgmac2_tx_queue_prio,
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.rx_queue_routing = NULL,
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.prog_mtl_rx_algorithms = dwxgmac2_prog_mtl_rx_algorithms,
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.prog_mtl_tx_algorithms = dwxgmac2_prog_mtl_tx_algorithms,
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.set_mtl_tx_queue_weight = dwxgmac2_set_mtl_tx_queue_weight,
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.map_mtl_to_dma = dwxgmac2_map_mtl_to_dma,
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.config_cbs = dwxgmac2_config_cbs,
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.dump_regs = dwxgmac2_dump_regs,
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.host_irq_status = dwxgmac2_host_irq_status,
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.host_mtl_irq_status = dwxgmac2_host_mtl_irq_status,
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.flow_ctrl = dwxgmac2_flow_ctrl,
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.pmt = dwxgmac2_pmt,
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.set_umac_addr = dwxgmac2_set_umac_addr,
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.get_umac_addr = dwxgmac2_get_umac_addr,
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.set_eee_mode = dwxgmac2_set_eee_mode,
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.reset_eee_mode = dwxgmac2_reset_eee_mode,
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.set_eee_timer = dwxgmac2_set_eee_timer,
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.set_eee_pls = dwxgmac2_set_eee_pls,
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.pcs_ctrl_ane = NULL,
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.pcs_rane = NULL,
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.pcs_get_adv_lp = NULL,
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.debug = NULL,
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.set_filter = dwxgmac2_set_filter,
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.safety_feat_config = dwxgmac3_safety_feat_config,
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.safety_feat_irq_status = dwxgmac3_safety_feat_irq_status,
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.safety_feat_dump = dwxgmac3_safety_feat_dump,
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.set_mac_loopback = dwxgmac2_set_mac_loopback,
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.rss_configure = dwxgmac2_rss_configure,
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.update_vlan_hash = dwxgmac2_update_vlan_hash,
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.rxp_config = dwxgmac3_rxp_config,
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.get_mac_tx_timestamp = dwxgmac2_get_mac_tx_timestamp,
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.flex_pps_config = dwxgmac2_flex_pps_config,
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.sarc_configure = dwxgmac2_sarc_configure,
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.enable_vlan = dwxgmac2_enable_vlan,
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.config_l3_filter = dwxgmac2_config_l3_filter,
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.config_l4_filter = dwxgmac2_config_l4_filter,
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.set_arp_offload = dwxgmac2_set_arp_offload,
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.est_configure = dwxgmac3_est_configure,
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.fpe_configure = dwxgmac3_fpe_configure,
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};
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int dwxgmac2_setup(struct stmmac_priv *priv)
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{
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struct mac_device_info *mac = priv->hw;
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@ -1521,3 +1583,40 @@ int dwxgmac2_setup(struct stmmac_priv *priv)
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return 0;
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}
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int dwxlgmac2_setup(struct stmmac_priv *priv)
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{
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struct mac_device_info *mac = priv->hw;
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dev_info(priv->device, "\tXLGMAC\n");
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priv->dev->priv_flags |= IFF_UNICAST_FLT;
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mac->pcsr = priv->ioaddr;
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mac->multicast_filter_bins = priv->plat->multicast_filter_bins;
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mac->unicast_filter_entries = priv->plat->unicast_filter_entries;
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mac->mcast_bits_log2 = 0;
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if (mac->multicast_filter_bins)
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mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
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mac->link.duplex = 0;
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mac->link.speed1000 = XLGMAC_CONFIG_SS_1000;
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mac->link.speed2500 = XLGMAC_CONFIG_SS_2500;
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mac->link.xgmii.speed10000 = XLGMAC_CONFIG_SS_10G;
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mac->link.xlgmii.speed25000 = XLGMAC_CONFIG_SS_25G;
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mac->link.xlgmii.speed40000 = XLGMAC_CONFIG_SS_40G;
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mac->link.xlgmii.speed50000 = XLGMAC_CONFIG_SS_50G;
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mac->link.xlgmii.speed100000 = XLGMAC_CONFIG_SS_100G;
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mac->link.speed_mask = XLGMAC_CONFIG_SS;
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mac->mii.addr = XGMAC_MDIO_ADDR;
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mac->mii.data = XGMAC_MDIO_DATA;
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mac->mii.addr_shift = 16;
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mac->mii.addr_mask = GENMASK(20, 16);
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mac->mii.reg_shift = 0;
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mac->mii.reg_mask = GENMASK(15, 0);
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mac->mii.clk_csr_shift = 19;
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mac->mii.clk_csr_mask = GENMASK(21, 19);
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return 0;
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}
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@ -0,0 +1,22 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2020 Synopsys, Inc. and/or its affiliates.
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* Synopsys DesignWare XLGMAC definitions.
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*/
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#ifndef __STMMAC_DWXLGMAC2_H__
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#define __STMMAC_DWXLGMAC2_H__
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/* MAC Registers */
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#define XLGMAC_CONFIG_SS GENMASK(30, 28)
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#define XLGMAC_CONFIG_SS_SHIFT 28
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#define XLGMAC_CONFIG_SS_40G (0x0 << XLGMAC_CONFIG_SS_SHIFT)
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#define XLGMAC_CONFIG_SS_25G (0x1 << XLGMAC_CONFIG_SS_SHIFT)
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#define XLGMAC_CONFIG_SS_50G (0x2 << XLGMAC_CONFIG_SS_SHIFT)
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#define XLGMAC_CONFIG_SS_100G (0x3 << XLGMAC_CONFIG_SS_SHIFT)
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#define XLGMAC_CONFIG_SS_10G (0x4 << XLGMAC_CONFIG_SS_SHIFT)
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#define XLGMAC_CONFIG_SS_2500 (0x6 << XLGMAC_CONFIG_SS_SHIFT)
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#define XLGMAC_CONFIG_SS_1000 (0x7 << XLGMAC_CONFIG_SS_SHIFT)
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#define XLGMAC_RXQ_ENABLE_CTRL0 0x00000140
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#endif /* __STMMAC_DWXLGMAC2_H__ */
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@ -23,6 +23,18 @@ static u32 stmmac_get_id(struct stmmac_priv *priv, u32 id_reg)
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return reg & GENMASK(7, 0);
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}
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static u32 stmmac_get_dev_id(struct stmmac_priv *priv, u32 id_reg)
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{
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u32 reg = readl(priv->ioaddr + id_reg);
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if (!reg) {
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dev_info(priv->device, "Version ID not available\n");
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return 0x0;
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}
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return (reg & GENMASK(15, 8)) >> 8;
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}
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static void stmmac_dwmac_mode_quirk(struct stmmac_priv *priv)
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{
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struct mac_device_info *mac = priv->hw;
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@ -69,11 +81,18 @@ static int stmmac_dwmac4_quirks(struct stmmac_priv *priv)
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return 0;
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}
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static int stmmac_dwxlgmac_quirks(struct stmmac_priv *priv)
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{
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priv->hw->xlgmac = true;
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return 0;
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}
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static const struct stmmac_hwif_entry {
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bool gmac;
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bool gmac4;
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bool xgmac;
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u32 min_id;
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u32 dev_id;
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const struct stmmac_regs_off regs;
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const void *desc;
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const void *dma;
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@ -199,6 +218,7 @@ static const struct stmmac_hwif_entry {
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.gmac4 = false,
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.xgmac = true,
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.min_id = DWXGMAC_CORE_2_10,
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.dev_id = DWXGMAC_ID,
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.regs = {
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.ptp_off = PTP_XGMAC_OFFSET,
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.mmc_off = MMC_XGMAC_OFFSET,
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@ -212,6 +232,25 @@ static const struct stmmac_hwif_entry {
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.mmc = &dwxgmac_mmc_ops,
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.setup = dwxgmac2_setup,
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.quirks = NULL,
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}, {
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.gmac = false,
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.gmac4 = false,
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.xgmac = true,
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.min_id = DWXLGMAC_CORE_2_00,
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.dev_id = DWXLGMAC_ID,
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.regs = {
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.ptp_off = PTP_XGMAC_OFFSET,
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.mmc_off = MMC_XGMAC_OFFSET,
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},
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.desc = &dwxgmac210_desc_ops,
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.dma = &dwxgmac210_dma_ops,
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.mac = &dwxlgmac2_ops,
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.hwtimestamp = &stmmac_ptp,
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.mode = NULL,
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.tc = &dwmac510_tc_ops,
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.mmc = &dwxgmac_mmc_ops,
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.setup = dwxlgmac2_setup,
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.quirks = stmmac_dwxlgmac_quirks,
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},
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};
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|
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@ -223,13 +262,15 @@ int stmmac_hwif_init(struct stmmac_priv *priv)
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const struct stmmac_hwif_entry *entry;
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struct mac_device_info *mac;
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bool needs_setup = true;
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u32 id, dev_id = 0;
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int i, ret;
|
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u32 id;
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|
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if (needs_gmac) {
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id = stmmac_get_id(priv, GMAC_VERSION);
|
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} else if (needs_gmac4 || needs_xgmac) {
|
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id = stmmac_get_id(priv, GMAC4_VERSION);
|
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if (needs_xgmac)
|
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dev_id = stmmac_get_dev_id(priv, GMAC4_VERSION);
|
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} else {
|
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id = 0;
|
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}
|
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|
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@ -267,6 +308,8 @@ int stmmac_hwif_init(struct stmmac_priv *priv)
|
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/* Use synopsys_id var because some setups can override this */
|
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if (priv->synopsys_id < entry->min_id)
|
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continue;
|
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if (needs_xgmac && (dev_id ^ entry->dev_id))
|
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continue;
|
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|
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/* Only use generic HW helpers if needed */
|
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mac->desc = mac->desc ? : entry->desc;
|
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|
|
|
|||
|
|
@ -605,6 +605,7 @@ extern const struct stmmac_dma_ops dwmac410_dma_ops;
|
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extern const struct stmmac_ops dwmac510_ops;
|
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extern const struct stmmac_tc_ops dwmac510_tc_ops;
|
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extern const struct stmmac_ops dwxgmac210_ops;
|
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extern const struct stmmac_ops dwxlgmac2_ops;
|
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extern const struct stmmac_dma_ops dwxgmac210_dma_ops;
|
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extern const struct stmmac_desc_ops dwxgmac210_desc_ops;
|
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extern const struct stmmac_mmc_ops dwmac_mmc_ops;
|
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|
|
|
|||
|
|
@ -849,6 +849,38 @@ static void stmmac_validate(struct phylink_config *config,
|
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phylink_set(mac_supported, 10000baseKX4_Full);
|
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phylink_set(mac_supported, 10000baseKR_Full);
|
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}
|
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if (!max_speed || (max_speed >= 25000)) {
|
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phylink_set(mac_supported, 25000baseCR_Full);
|
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phylink_set(mac_supported, 25000baseKR_Full);
|
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phylink_set(mac_supported, 25000baseSR_Full);
|
||||
}
|
||||
if (!max_speed || (max_speed >= 40000)) {
|
||||
phylink_set(mac_supported, 40000baseKR4_Full);
|
||||
phylink_set(mac_supported, 40000baseCR4_Full);
|
||||
phylink_set(mac_supported, 40000baseSR4_Full);
|
||||
phylink_set(mac_supported, 40000baseLR4_Full);
|
||||
}
|
||||
if (!max_speed || (max_speed >= 50000)) {
|
||||
phylink_set(mac_supported, 50000baseCR2_Full);
|
||||
phylink_set(mac_supported, 50000baseKR2_Full);
|
||||
phylink_set(mac_supported, 50000baseSR2_Full);
|
||||
phylink_set(mac_supported, 50000baseKR_Full);
|
||||
phylink_set(mac_supported, 50000baseSR_Full);
|
||||
phylink_set(mac_supported, 50000baseCR_Full);
|
||||
phylink_set(mac_supported, 50000baseLR_ER_FR_Full);
|
||||
phylink_set(mac_supported, 50000baseDR_Full);
|
||||
}
|
||||
if (!max_speed || (max_speed >= 100000)) {
|
||||
phylink_set(mac_supported, 100000baseKR4_Full);
|
||||
phylink_set(mac_supported, 100000baseSR4_Full);
|
||||
phylink_set(mac_supported, 100000baseCR4_Full);
|
||||
phylink_set(mac_supported, 100000baseLR4_ER4_Full);
|
||||
phylink_set(mac_supported, 100000baseKR2_Full);
|
||||
phylink_set(mac_supported, 100000baseSR2_Full);
|
||||
phylink_set(mac_supported, 100000baseCR2_Full);
|
||||
phylink_set(mac_supported, 100000baseLR2_ER2_FR2_Full);
|
||||
phylink_set(mac_supported, 100000baseDR2_Full);
|
||||
}
|
||||
}
|
||||
|
||||
/* Half-Duplex can only work with single queue */
|
||||
|
|
@ -929,6 +961,32 @@ static void stmmac_mac_link_up(struct phylink_config *config,
|
|||
default:
|
||||
return;
|
||||
}
|
||||
} else if (interface == PHY_INTERFACE_MODE_XLGMII) {
|
||||
switch (speed) {
|
||||
case SPEED_100000:
|
||||
ctrl |= priv->hw->link.xlgmii.speed100000;
|
||||
break;
|
||||
case SPEED_50000:
|
||||
ctrl |= priv->hw->link.xlgmii.speed50000;
|
||||
break;
|
||||
case SPEED_40000:
|
||||
ctrl |= priv->hw->link.xlgmii.speed40000;
|
||||
break;
|
||||
case SPEED_25000:
|
||||
ctrl |= priv->hw->link.xlgmii.speed25000;
|
||||
break;
|
||||
case SPEED_10000:
|
||||
ctrl |= priv->hw->link.xgmii.speed10000;
|
||||
break;
|
||||
case SPEED_2500:
|
||||
ctrl |= priv->hw->link.speed2500;
|
||||
break;
|
||||
case SPEED_1000:
|
||||
ctrl |= priv->hw->link.speed1000;
|
||||
break;
|
||||
default:
|
||||
return;
|
||||
}
|
||||
} else {
|
||||
switch (speed) {
|
||||
case SPEED_2500:
|
||||
|
|
|
|||
|
|
@ -14,6 +14,7 @@
|
|||
|
||||
#define SYNOPSYS_XPCS_USXGMII_ID 0x7996ced0
|
||||
#define SYNOPSYS_XPCS_10GKR_ID 0x7996ced0
|
||||
#define SYNOPSYS_XPCS_XLGMII_ID 0x7996ced0
|
||||
#define SYNOPSYS_XPCS_MASK 0xffffffff
|
||||
|
||||
/* Vendor regs access */
|
||||
|
|
@ -74,6 +75,36 @@ static const int xpcs_10gkr_features[] = {
|
|||
__ETHTOOL_LINK_MODE_MASK_NBITS,
|
||||
};
|
||||
|
||||
static const int xpcs_xlgmii_features[] = {
|
||||
ETHTOOL_LINK_MODE_Pause_BIT,
|
||||
ETHTOOL_LINK_MODE_Asym_Pause_BIT,
|
||||
ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
|
||||
ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
|
||||
ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
|
||||
ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
|
||||
ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
|
||||
ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
|
||||
ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
|
||||
ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
|
||||
ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
|
||||
ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
|
||||
ETHTOOL_LINK_MODE_50000baseKR_Full_BIT,
|
||||
ETHTOOL_LINK_MODE_50000baseSR_Full_BIT,
|
||||
ETHTOOL_LINK_MODE_50000baseCR_Full_BIT,
|
||||
ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT,
|
||||
ETHTOOL_LINK_MODE_50000baseDR_Full_BIT,
|
||||
ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
|
||||
ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
|
||||
ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
|
||||
ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
|
||||
ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT,
|
||||
ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT,
|
||||
ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT,
|
||||
ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT,
|
||||
ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT,
|
||||
__ETHTOOL_LINK_MODE_MASK_NBITS,
|
||||
};
|
||||
|
||||
static const phy_interface_t xpcs_usxgmii_interfaces[] = {
|
||||
PHY_INTERFACE_MODE_USXGMII,
|
||||
PHY_INTERFACE_MODE_MAX,
|
||||
|
|
@ -84,6 +115,11 @@ static const phy_interface_t xpcs_10gkr_interfaces[] = {
|
|||
PHY_INTERFACE_MODE_MAX,
|
||||
};
|
||||
|
||||
static const phy_interface_t xpcs_xlgmii_interfaces[] = {
|
||||
PHY_INTERFACE_MODE_XLGMII,
|
||||
PHY_INTERFACE_MODE_MAX,
|
||||
};
|
||||
|
||||
static struct xpcs_id {
|
||||
u32 id;
|
||||
u32 mask;
|
||||
|
|
@ -100,6 +136,11 @@ static struct xpcs_id {
|
|||
.mask = SYNOPSYS_XPCS_MASK,
|
||||
.supported = xpcs_10gkr_features,
|
||||
.interface = xpcs_10gkr_interfaces,
|
||||
}, {
|
||||
.id = SYNOPSYS_XPCS_XLGMII_ID,
|
||||
.mask = SYNOPSYS_XPCS_MASK,
|
||||
.supported = xpcs_xlgmii_features,
|
||||
.interface = xpcs_xlgmii_interfaces,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -458,6 +499,60 @@ static void xpcs_resolve_lpa(struct mdio_xpcs_args *xpcs,
|
|||
state->duplex = DUPLEX_FULL;
|
||||
}
|
||||
|
||||
static int xpcs_get_max_xlgmii_speed(struct mdio_xpcs_args *xpcs,
|
||||
struct phylink_link_state *state)
|
||||
{
|
||||
unsigned long *adv = state->advertising;
|
||||
int speed = SPEED_UNKNOWN;
|
||||
int bit;
|
||||
|
||||
for_each_set_bit(bit, adv, __ETHTOOL_LINK_MODE_MASK_NBITS) {
|
||||
int new_speed = SPEED_UNKNOWN;
|
||||
|
||||
switch (bit) {
|
||||
case ETHTOOL_LINK_MODE_25000baseCR_Full_BIT:
|
||||
case ETHTOOL_LINK_MODE_25000baseKR_Full_BIT:
|
||||
case ETHTOOL_LINK_MODE_25000baseSR_Full_BIT:
|
||||
new_speed = SPEED_25000;
|
||||
break;
|
||||
case ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT:
|
||||
case ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT:
|
||||
case ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT:
|
||||
case ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT:
|
||||
new_speed = SPEED_40000;
|
||||
break;
|
||||
case ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT:
|
||||
case ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT:
|
||||
case ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT:
|
||||
case ETHTOOL_LINK_MODE_50000baseKR_Full_BIT:
|
||||
case ETHTOOL_LINK_MODE_50000baseSR_Full_BIT:
|
||||
case ETHTOOL_LINK_MODE_50000baseCR_Full_BIT:
|
||||
case ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT:
|
||||
case ETHTOOL_LINK_MODE_50000baseDR_Full_BIT:
|
||||
new_speed = SPEED_50000;
|
||||
break;
|
||||
case ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT:
|
||||
case ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT:
|
||||
case ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT:
|
||||
case ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT:
|
||||
case ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT:
|
||||
case ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT:
|
||||
case ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT:
|
||||
case ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT:
|
||||
case ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT:
|
||||
new_speed = SPEED_100000;
|
||||
break;
|
||||
default:
|
||||
continue;
|
||||
}
|
||||
|
||||
if (new_speed > speed)
|
||||
speed = new_speed;
|
||||
}
|
||||
|
||||
return speed;
|
||||
}
|
||||
|
||||
static void xpcs_resolve_pma(struct mdio_xpcs_args *xpcs,
|
||||
struct phylink_link_state *state)
|
||||
{
|
||||
|
|
@ -468,6 +563,9 @@ static void xpcs_resolve_pma(struct mdio_xpcs_args *xpcs,
|
|||
case PHY_INTERFACE_MODE_10GKR:
|
||||
state->speed = SPEED_10000;
|
||||
break;
|
||||
case PHY_INTERFACE_MODE_XLGMII:
|
||||
state->speed = xpcs_get_max_xlgmii_speed(xpcs, state);
|
||||
break;
|
||||
default:
|
||||
state->speed = SPEED_UNKNOWN;
|
||||
break;
|
||||
|
|
|
|||
Loading…
Reference in New Issue