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x86/platform/intel-mid: Drop unused __intel_mid_cpu_chip and Co. 

Since there is no more user of this global variable and associated custom API,
we may safely drop this legacy reinvented a wheel from the kernel sources.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
This commit is contained in:
Andy Shevchenko 2021-02-11 15:40:06 +02:00 committed by Rafael J. Wysocki
parent 6517da7aac
commit 043698c580
2 changed files with 0 additions and 40 deletions
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23
arch/x86/include/asm/intel-mid.h
View File

@ -21,36 +21,13 @@ extern void intel_mid_pwr_power_off(void);
extern int intel_mid_pwr_get_lss_id(struct pci_dev *pdev); extern int intel_mid_pwr_get_lss_id(struct pci_dev *pdev);
/*
* Medfield is the follow-up of Moorestown, it combines two chip solution into
* one. Other than that it also added always-on and constant tsc and lapic
* timers. Medfield is the platform name, and the chip name is called Penwell
* we treat Medfield/Penwell as a variant of Moorestown. Penwell can be
* identified via MSRs.
*/
enum intel_mid_cpu_type {
/* 1 was Moorestown */
INTEL_MID_CPU_CHIP_PENWELL = 2,
INTEL_MID_CPU_CHIP_CLOVERVIEW,
INTEL_MID_CPU_CHIP_TANGIER,
};
extern enum intel_mid_cpu_type __intel_mid_cpu_chip;
#ifdef CONFIG_X86_INTEL_MID #ifdef CONFIG_X86_INTEL_MID
static inline enum intel_mid_cpu_type intel_mid_identify_cpu(void)
{
return __intel_mid_cpu_chip;
}
extern void intel_scu_devices_create(void); extern void intel_scu_devices_create(void);
extern void intel_scu_devices_destroy(void); extern void intel_scu_devices_destroy(void);
#else /* !CONFIG_X86_INTEL_MID */ #else /* !CONFIG_X86_INTEL_MID */
#define intel_mid_identify_cpu() 0
static inline void intel_scu_devices_create(void) { } static inline void intel_scu_devices_create(void) { }
static inline void intel_scu_devices_destroy(void) { } static inline void intel_scu_devices_destroy(void) { }

17
arch/x86/platform/intel-mid/intel-mid.c
View File

@ -32,9 +32,6 @@
#define IPCMSG_COLD_OFF 0x80 /* Only for Tangier */ #define IPCMSG_COLD_OFF 0x80 /* Only for Tangier */
#define IPCMSG_COLD_RESET 0xF1 #define IPCMSG_COLD_RESET 0xF1
enum intel_mid_cpu_type __intel_mid_cpu_chip;
EXPORT_SYMBOL_GPL(__intel_mid_cpu_chip);
static void intel_mid_power_off(void) static void intel_mid_power_off(void)
{ {
/* Shut down South Complex via PWRMU */ /* Shut down South Complex via PWRMU */
@ -58,29 +55,15 @@ static void __init intel_mid_time_init(void)
static void intel_mid_arch_setup(void) static void intel_mid_arch_setup(void)
{ {
if (boot_cpu_data.x86 != 6) {
pr_err("Unknown Intel MID CPU (%d:%d), default to Penwell\n",
boot_cpu_data.x86, boot_cpu_data.x86_model);
__intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_PENWELL;
goto out;
}
switch (boot_cpu_data.x86_model) { switch (boot_cpu_data.x86_model) {
case 0x35:
__intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_CLOVERVIEW;
break;
case 0x3C: case 0x3C:
case 0x4A: case 0x4A:
__intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_TANGIER;
x86_platform.legacy.rtc = 1; x86_platform.legacy.rtc = 1;
break; break;
case 0x27:
default: default:
__intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_PENWELL;
break; break;
} }
out:
/* /*
* Intel MID platforms are using explicitly defined regulators. * Intel MID platforms are using explicitly defined regulators.
* *