openkylin
/
linux
mirror of https://gitee.com/openkylin/linux.git
9
0
Fork 0
Code Issues Projects Releases Wiki Activity

clk: qcom: ipq8074: Add correct index for PCIe clocks 

The PCIe clocks GCC_PCIE0_AXI_S_BRIDGE_CLK, GCC_PCIE0_RCHNG_CLK_SRC,
GCC_PCIE0_RCHNG_CLK are wrongly added to the gcc reset group.

Move them to the gcc clock group.

Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
Link: https://lore.kernel.org/r/1594877570-9280-1-git-send-email-sivaprak@codeaurora.org
Fixes: e7fb524cfc ("dt-bindings: clock: qcom: ipq8074: Add missing bindings for PCIe")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Sivaprakash Murugesan 2020-07-16 11:02:50 +05:30 committed by Stephen Boyd
parent b429784499
commit 044f507dc0
1 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
include/dt-bindings/clock/qcom,gcc-ipq8074.h
View File

@ -230,6 +230,9 @@
#define GCC_GP1_CLK 221
#define GCC_GP2_CLK 222
#define GCC_GP3_CLK 223
#define GCC_PCIE0_AXI_S_BRIDGE_CLK 224
#define GCC_PCIE0_RCHNG_CLK_SRC 225
#define GCC_PCIE0_RCHNG_CLK 226
#define GCC_BLSP1_BCR 0
#define GCC_BLSP1_QUP1_BCR 1
@ -363,8 +366,5 @@
#define GCC_PCIE1_AHB_ARES 129
#define GCC_PCIE1_AXI_MASTER_STICKY_ARES 130
#define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 131
#define GCC_PCIE0_AXI_S_BRIDGE_CLK 132
#define GCC_PCIE0_RCHNG_CLK_SRC 133
#define GCC_PCIE0_RCHNG_CLK 134
#endif