mirror of https://gitee.com/openkylin/linux.git
drm: EDID endianness fixes.
Mostly replacing bitfields with explicit masks and shifts. Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Michel Dänzer
Dave Airlie
parent
00fa28ae29
commit
0454beab0f
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@ -252,16 +252,18 @@ struct drm_display_mode *drm_mode_std(struct drm_device *dev,
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{
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struct drm_display_mode *mode;
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int hsize = t->hsize * 8 + 248, vsize;
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unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
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>> EDID_TIMING_ASPECT_SHIFT;
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mode = drm_mode_create(dev);
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if (!mode)
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return NULL;
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if (t->aspect_ratio == 0)
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if (aspect_ratio == 0)
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vsize = (hsize * 10) / 16;
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else if (t->aspect_ratio == 1)
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else if (aspect_ratio == 1)
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vsize = (hsize * 3) / 4;
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else if (t->aspect_ratio == 2)
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else if (aspect_ratio == 2)
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vsize = (hsize * 4) / 5;
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else
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vsize = (hsize * 9) / 16;
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@ -288,17 +290,24 @@ static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
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{
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struct drm_display_mode *mode;
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struct detailed_pixel_timing *pt = &timing->data.pixel_data;
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unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
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unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
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unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
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unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
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unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 8 | pt->hsync_offset_lo;
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unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 6 | pt->hsync_pulse_width_lo;
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unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) | (pt->vsync_offset_pulse_width_lo & 0xf);
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unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) >> 2 | pt->vsync_offset_pulse_width_lo >> 4;
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/* ignore tiny modes */
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if (((pt->hactive_hi << 8) | pt->hactive_lo) < 64 ||
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((pt->vactive_hi << 8) | pt->hactive_lo) < 64)
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if (hactive < 64 || vactive < 64)
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return NULL;
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if (pt->stereo) {
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if (pt->misc & DRM_EDID_PT_STEREO) {
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printk(KERN_WARNING "stereo mode not supported\n");
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return NULL;
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}
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if (!pt->separate_sync) {
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if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
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printk(KERN_WARNING "integrated sync not supported\n");
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return NULL;
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}
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@ -310,41 +319,36 @@ static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
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mode->type = DRM_MODE_TYPE_DRIVER;
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if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
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timing->pixel_clock = 1088;
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timing->pixel_clock = cpu_to_le16(1088);
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mode->clock = timing->pixel_clock * 10;
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mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
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mode->hdisplay = (pt->hactive_hi << 8) | pt->hactive_lo;
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mode->hsync_start = mode->hdisplay + ((pt->hsync_offset_hi << 8) |
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pt->hsync_offset_lo);
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mode->hsync_end = mode->hsync_start +
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((pt->hsync_pulse_width_hi << 8) |
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pt->hsync_pulse_width_lo);
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mode->htotal = mode->hdisplay + ((pt->hblank_hi << 8) | pt->hblank_lo);
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mode->hdisplay = hactive;
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mode->hsync_start = mode->hdisplay + hsync_offset;
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mode->hsync_end = mode->hsync_start + hsync_pulse_width;
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mode->htotal = mode->hdisplay + hblank;
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mode->vdisplay = (pt->vactive_hi << 8) | pt->vactive_lo;
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mode->vsync_start = mode->vdisplay + ((pt->vsync_offset_hi << 4) |
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pt->vsync_offset_lo);
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mode->vsync_end = mode->vsync_start +
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((pt->vsync_pulse_width_hi << 4) |
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pt->vsync_pulse_width_lo);
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mode->vtotal = mode->vdisplay + ((pt->vblank_hi << 8) | pt->vblank_lo);
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mode->vdisplay = vactive;
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mode->vsync_start = mode->vdisplay + vsync_offset;
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mode->vsync_end = mode->vsync_start + vsync_pulse_width;
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mode->vtotal = mode->vdisplay + vblank;
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drm_mode_set_name(mode);
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if (pt->interlaced)
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if (pt->misc & DRM_EDID_PT_INTERLACED)
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mode->flags |= DRM_MODE_FLAG_INTERLACE;
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if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
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pt->hsync_positive = 1;
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pt->vsync_positive = 1;
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pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
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}
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mode->flags |= pt->hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
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mode->flags |= pt->vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
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mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
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DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
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mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
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DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
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mode->width_mm = pt->width_mm_lo | (pt->width_mm_hi << 8);
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mode->height_mm = pt->height_mm_lo | (pt->height_mm_hi << 8);
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mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
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mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
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if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
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mode->width_mm *= 10;
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@ -465,7 +469,7 @@ static int add_standard_modes(struct drm_connector *connector, struct edid *edid
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struct drm_display_mode *newmode;
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/* If std timings bytes are 1, 1 it's empty */
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if (t->hsize == 1 && (t->aspect_ratio | t->vfreq) == 1)
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if (t->hsize == 1 && t->vfreq_aspect == 1)
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continue;
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newmode = drm_mode_std(dev, &edid->standard_timings[i]);
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@ -509,7 +513,7 @@ static int add_detailed_info(struct drm_connector *connector,
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continue;
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/* First detailed mode is preferred */
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if (i == 0 && edid->preferred_timing)
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if (i == 0 && (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING))
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newmode->type |= DRM_MODE_TYPE_PREFERRED;
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drm_mode_probed_add(connector, newmode);
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@ -767,22 +771,22 @@ int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
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if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
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edid_fixup_preferred(connector, quirks);
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connector->display_info.serration_vsync = edid->serration_vsync;
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connector->display_info.sync_on_green = edid->sync_on_green;
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connector->display_info.composite_sync = edid->composite_sync;
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connector->display_info.separate_syncs = edid->separate_syncs;
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connector->display_info.blank_to_black = edid->blank_to_black;
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connector->display_info.video_level = edid->video_level;
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connector->display_info.digital = edid->digital;
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connector->display_info.serration_vsync = (edid->input & DRM_EDID_INPUT_SERRATION_VSYNC) ? 1 : 0;
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connector->display_info.sync_on_green = (edid->input & DRM_EDID_INPUT_SYNC_ON_GREEN) ? 1 : 0;
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connector->display_info.composite_sync = (edid->input & DRM_EDID_INPUT_COMPOSITE_SYNC) ? 1 : 0;
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connector->display_info.separate_syncs = (edid->input & DRM_EDID_INPUT_SEPARATE_SYNCS) ? 1 : 0;
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connector->display_info.blank_to_black = (edid->input & DRM_EDID_INPUT_BLANK_TO_BLACK) ? 1 : 0;
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connector->display_info.video_level = (edid->input & DRM_EDID_INPUT_VIDEO_LEVEL) >> 5;
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connector->display_info.digital = (edid->input & DRM_EDID_INPUT_DIGITAL) ? 1 : 0;
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connector->display_info.width_mm = edid->width_cm * 10;
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connector->display_info.height_mm = edid->height_cm * 10;
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connector->display_info.gamma = edid->gamma;
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connector->display_info.gtf_supported = edid->default_gtf;
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connector->display_info.standard_color = edid->standard_color;
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connector->display_info.display_type = edid->display_type;
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connector->display_info.active_off_supported = edid->pm_active_off;
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connector->display_info.suspend_supported = edid->pm_suspend;
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connector->display_info.standby_supported = edid->pm_standby;
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connector->display_info.gtf_supported = (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) ? 1 : 0;
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connector->display_info.standard_color = (edid->features & DRM_EDID_FEATURE_STANDARD_COLOR) ? 1 : 0;
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connector->display_info.display_type = (edid->features & DRM_EDID_FEATURE_DISPLAY_TYPE) >> 3;
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connector->display_info.active_off_supported = (edid->features & DRM_EDID_FEATURE_PM_ACTIVE_OFF) ? 1 : 0;
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connector->display_info.suspend_supported = (edid->features & DRM_EDID_FEATURE_PM_SUSPEND) ? 1 : 0;
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connector->display_info.standby_supported = (edid->features & DRM_EDID_FEATURE_PM_STANDBY) ? 1 : 0;
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connector->display_info.gamma = edid->gamma;
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return num_modes;
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@ -351,7 +351,7 @@ int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
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radeon_i2c_do_lock(radeon_connector, 0);
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if (edid) {
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/* update digital bits here */
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if (edid->digital)
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if (edid->input & DRM_EDID_INPUT_DIGITAL)
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radeon_connector->use_digital = 1;
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else
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radeon_connector->use_digital = 0;
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@ -28,53 +28,49 @@
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#define EDID_LENGTH 128
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#define DDC_ADDR 0x50
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#ifdef BIG_ENDIAN
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#error "EDID structure is little endian, need big endian versions"
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#else
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struct est_timings {
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u8 t1;
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u8 t2;
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u8 mfg_rsvd;
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} __attribute__((packed));
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/* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */
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#define EDID_TIMING_ASPECT_SHIFT 0
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#define EDID_TIMING_ASPECT_MASK (0x3 << EDID_TIMING_ASPECT_SHIFT)
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/* need to add 60 */
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#define EDID_TIMING_VFREQ_SHIFT 2
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#define EDID_TIMING_VFREQ_MASK (0x3f << EDID_TIMING_VFREQ_SHIFT)
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struct std_timing {
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u8 hsize; /* need to multiply by 8 then add 248 */
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u8 vfreq:6; /* need to add 60 */
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u8 aspect_ratio:2; /* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */
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u8 vfreq_aspect;
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} __attribute__((packed));
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#define DRM_EDID_PT_HSYNC_POSITIVE (1 << 6)
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#define DRM_EDID_PT_VSYNC_POSITIVE (1 << 5)
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#define DRM_EDID_PT_SEPARATE_SYNC (3 << 3)
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#define DRM_EDID_PT_STEREO (1 << 2)
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#define DRM_EDID_PT_INTERLACED (1 << 1)
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/* If detailed data is pixel timing */
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struct detailed_pixel_timing {
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u8 hactive_lo;
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u8 hblank_lo;
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u8 hblank_hi:4;
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u8 hactive_hi:4;
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u8 hactive_hblank_hi;
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u8 vactive_lo;
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u8 vblank_lo;
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u8 vblank_hi:4;
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u8 vactive_hi:4;
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u8 vactive_vblank_hi;
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u8 hsync_offset_lo;
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u8 hsync_pulse_width_lo;
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u8 vsync_pulse_width_lo:4;
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u8 vsync_offset_lo:4;
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u8 vsync_pulse_width_hi:2;
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u8 vsync_offset_hi:2;
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u8 hsync_pulse_width_hi:2;
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u8 hsync_offset_hi:2;
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u8 vsync_offset_pulse_width_lo;
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u8 hsync_vsync_offset_pulse_width_hi;
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u8 width_mm_lo;
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u8 height_mm_lo;
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u8 height_mm_hi:4;
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u8 width_mm_hi:4;
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u8 width_height_mm_hi;
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u8 hborder;
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u8 vborder;
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u8 unknown0:1;
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u8 hsync_positive:1;
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u8 vsync_positive:1;
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u8 separate_sync:2;
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u8 stereo:1;
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u8 unknown6:1;
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u8 interlaced:1;
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u8 misc;
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} __attribute__((packed));
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/* If it's not pixel timing, it'll be one of the below */
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@ -88,18 +84,16 @@ struct detailed_data_monitor_range {
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u8 min_hfreq_khz;
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u8 max_hfreq_khz;
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u8 pixel_clock_mhz; /* need to multiply by 10 */
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u16 sec_gtf_toggle; /* A000=use above, 20=use below */ /* FIXME: byte order */
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__le16 sec_gtf_toggle; /* A000=use above, 20=use below */
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u8 hfreq_start_khz; /* need to multiply by 2 */
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u8 c; /* need to divide by 2 */
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u16 m; /* FIXME: byte order */
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__le16 m;
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u8 k;
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u8 j; /* need to divide by 2 */
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} __attribute__((packed));
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struct detailed_data_wpindex {
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u8 white_y_lo:2;
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u8 white_x_lo:2;
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u8 pad:4;
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u8 white_xy_lo; /* Upper 2 bits each */
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u8 white_x_hi;
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u8 white_y_hi;
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u8 gamma; /* need to divide by 100 then add 1 */
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@ -134,13 +128,29 @@ struct detailed_non_pixel {
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#define EDID_DETAIL_MONITOR_SERIAL 0xff
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struct detailed_timing {
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u16 pixel_clock; /* need to multiply by 10 KHz */ /* FIXME: byte order */
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__le16 pixel_clock; /* need to multiply by 10 KHz */
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union {
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struct detailed_pixel_timing pixel_data;
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struct detailed_non_pixel other_data;
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} data;
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} __attribute__((packed));
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#define DRM_EDID_INPUT_SERRATION_VSYNC (1 << 7)
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#define DRM_EDID_INPUT_SYNC_ON_GREEN (1 << 5)
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#define DRM_EDID_INPUT_COMPOSITE_SYNC (1 << 4)
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#define DRM_EDID_INPUT_SEPARATE_SYNCS (1 << 3)
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#define DRM_EDID_INPUT_BLANK_TO_BLACK (1 << 2)
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#define DRM_EDID_INPUT_VIDEO_LEVEL (3 << 1)
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#define DRM_EDID_INPUT_DIGITAL (1 << 0) /* bits above must be zero if set */
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#define DRM_EDID_FEATURE_DEFAULT_GTF (1 << 7)
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#define DRM_EDID_FEATURE_PREFERRED_TIMING (1 << 6)
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#define DRM_EDID_FEATURE_STANDARD_COLOR (1 << 5)
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#define DRM_EDID_FEATURE_DISPLAY_TYPE (3 << 3) /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */
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#define DRM_EDID_FEATURE_PM_ACTIVE_OFF (1 << 2)
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#define DRM_EDID_FEATURE_PM_SUSPEND (1 << 1)
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#define DRM_EDID_FEATURE_PM_STANDBY (1 << 0)
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struct edid {
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u8 header[8];
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/* Vendor & product info */
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@ -153,25 +163,11 @@ struct edid {
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u8 version;
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u8 revision;
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/* Display info: */
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/* input definition */
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u8 serration_vsync:1;
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u8 sync_on_green:1;
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u8 composite_sync:1;
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u8 separate_syncs:1;
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u8 blank_to_black:1;
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u8 video_level:2;
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u8 digital:1; /* bits below must be zero if set */
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u8 input;
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u8 width_cm;
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u8 height_cm;
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u8 gamma;
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/* feature support */
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u8 default_gtf:1;
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u8 preferred_timing:1;
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u8 standard_color:1;
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u8 display_type:2; /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */
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u8 pm_active_off:1;
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u8 pm_suspend:1;
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u8 pm_standby:1;
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u8 features;
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/* Color characteristics */
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u8 red_green_lo;
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u8 black_white_lo;
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@ -195,8 +191,6 @@ struct edid {
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u8 checksum;
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} __attribute__((packed));
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#endif /* little endian structs */
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#define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8))
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#endif /* __DRM_EDID_H__ */
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