mirror of https://gitee.com/openkylin/linux.git
crypto: amcc - Add crypt4xx driver
This patch adds support for AMCC ppc4xx security device driver. This is the initial release that includes the driver framework with AES and SHA1 algorithms support. The remaining algorithms will be released in the near future. Signed-off-by: James Hsiao <jhsiao@amcc.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
James Hsiao
Herbert Xu
parent
5b07bd5701
commit
049359d655
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@ -127,6 +127,13 @@ SDRAM0: sdram {
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dcr-reg = <0x010 0x002>;
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};
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CRYPTO: crypto@180000 {
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compatible = "amcc,ppc460ex-crypto", "amcc,ppc4xx-crypto";
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reg = <4 0x00180000 0x80400>;
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interrupt-parent = <&UIC0>;
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interrupts = <0x1d 0x4>;
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};
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MAL0: mcmal {
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compatible = "ibm,mcmal-460ex", "ibm,mcmal2";
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dcr-reg = <0x180 0x062>;
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@ -97,6 +97,13 @@ SDRAM0: memory-controller {
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0x6 0x4>; /* ECC SEC Error */
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};
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CRYPTO: crypto@ef700000 {
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compatible = "amcc,ppc405ex-crypto", "amcc,ppc4xx-crypto";
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reg = <0xef700000 0x80400>;
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interrupt-parent = <&UIC0>;
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interrupts = <0x17 0x2>;
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};
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MAL0: mcmal {
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compatible = "ibm,mcmal-405ex", "ibm,mcmal2";
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dcr-reg = <0x180 0x062>;
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@ -200,4 +200,13 @@ config CRYPTO_DEV_IXP4XX
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help
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Driver for the IXP4xx NPE crypto engine.
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config CRYPTO_DEV_PPC4XX
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tristate "Driver AMCC PPC4xx crypto accelerator"
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depends on PPC && 4xx
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select CRYPTO_HASH
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select CRYPTO_ALGAPI
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select CRYPTO_BLKCIPHER
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help
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This option allows you to have support for AMCC crypto acceleration.
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endif # CRYPTO_HW
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@ -4,3 +4,4 @@ obj-$(CONFIG_CRYPTO_DEV_GEODE) += geode-aes.o
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obj-$(CONFIG_CRYPTO_DEV_HIFN_795X) += hifn_795x.o
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obj-$(CONFIG_CRYPTO_DEV_TALITOS) += talitos.o
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obj-$(CONFIG_CRYPTO_DEV_IXP4XX) += ixp4xx_crypto.o
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obj-$(CONFIG_CRYPTO_DEV_PPC4XX) += amcc/
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@ -0,0 +1,2 @@
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obj-$(CONFIG_CRYPTO_DEV_PPC4XX) += crypto4xx.o
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crypto4xx-objs := crypto4xx_core.o crypto4xx_alg.o crypto4xx_sa.o
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@ -0,0 +1,293 @@
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/**
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* AMCC SoC PPC4xx Crypto Driver
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*
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* Copyright (c) 2008 Applied Micro Circuits Corporation.
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* All rights reserved. James Hsiao <jhsiao@amcc.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* This file implements the Linux crypto algorithms.
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*/
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/spinlock_types.h>
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#include <linux/scatterlist.h>
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#include <linux/crypto.h>
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#include <linux/hash.h>
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#include <crypto/internal/hash.h>
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#include <linux/dma-mapping.h>
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#include <crypto/algapi.h>
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#include <crypto/aes.h>
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#include <crypto/sha.h>
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#include "crypto4xx_reg_def.h"
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#include "crypto4xx_sa.h"
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#include "crypto4xx_core.h"
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void set_dynamic_sa_command_0(struct dynamic_sa_ctl *sa, u32 save_h,
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u32 save_iv, u32 ld_h, u32 ld_iv, u32 hdr_proc,
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u32 h, u32 c, u32 pad_type, u32 op_grp, u32 op,
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u32 dir)
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{
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sa->sa_command_0.w = 0;
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sa->sa_command_0.bf.save_hash_state = save_h;
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sa->sa_command_0.bf.save_iv = save_iv;
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sa->sa_command_0.bf.load_hash_state = ld_h;
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sa->sa_command_0.bf.load_iv = ld_iv;
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sa->sa_command_0.bf.hdr_proc = hdr_proc;
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sa->sa_command_0.bf.hash_alg = h;
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sa->sa_command_0.bf.cipher_alg = c;
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sa->sa_command_0.bf.pad_type = pad_type & 3;
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sa->sa_command_0.bf.extend_pad = pad_type >> 2;
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sa->sa_command_0.bf.op_group = op_grp;
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sa->sa_command_0.bf.opcode = op;
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sa->sa_command_0.bf.dir = dir;
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}
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void set_dynamic_sa_command_1(struct dynamic_sa_ctl *sa, u32 cm, u32 hmac_mc,
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u32 cfb, u32 esn, u32 sn_mask, u32 mute,
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u32 cp_pad, u32 cp_pay, u32 cp_hdr)
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{
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sa->sa_command_1.w = 0;
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sa->sa_command_1.bf.crypto_mode31 = (cm & 4) >> 2;
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sa->sa_command_1.bf.crypto_mode9_8 = cm & 3;
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sa->sa_command_1.bf.feedback_mode = cfb,
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sa->sa_command_1.bf.sa_rev = 1;
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sa->sa_command_1.bf.extended_seq_num = esn;
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sa->sa_command_1.bf.seq_num_mask = sn_mask;
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sa->sa_command_1.bf.mutable_bit_proc = mute;
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sa->sa_command_1.bf.copy_pad = cp_pad;
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sa->sa_command_1.bf.copy_payload = cp_pay;
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sa->sa_command_1.bf.copy_hdr = cp_hdr;
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}
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int crypto4xx_encrypt(struct ablkcipher_request *req)
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{
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struct crypto4xx_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
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ctx->direction = DIR_OUTBOUND;
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ctx->hash_final = 0;
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ctx->is_hash = 0;
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ctx->pd_ctl = 0x1;
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return crypto4xx_build_pd(&req->base, ctx, req->src, req->dst,
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req->nbytes, req->info,
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get_dynamic_sa_iv_size(ctx));
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}
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int crypto4xx_decrypt(struct ablkcipher_request *req)
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{
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struct crypto4xx_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
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ctx->direction = DIR_INBOUND;
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ctx->hash_final = 0;
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ctx->is_hash = 0;
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ctx->pd_ctl = 1;
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return crypto4xx_build_pd(&req->base, ctx, req->src, req->dst,
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req->nbytes, req->info,
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get_dynamic_sa_iv_size(ctx));
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}
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/**
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* AES Functions
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*/
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static int crypto4xx_setkey_aes(struct crypto_ablkcipher *cipher,
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const u8 *key,
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unsigned int keylen,
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unsigned char cm,
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u8 fb)
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{
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struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher);
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struct crypto4xx_ctx *ctx = crypto_tfm_ctx(tfm);
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struct dynamic_sa_ctl *sa;
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int rc;
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if (keylen != AES_KEYSIZE_256 &&
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keylen != AES_KEYSIZE_192 && keylen != AES_KEYSIZE_128) {
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crypto_ablkcipher_set_flags(cipher,
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CRYPTO_TFM_RES_BAD_KEY_LEN);
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return -EINVAL;
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}
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/* Create SA */
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if (ctx->sa_in_dma_addr || ctx->sa_out_dma_addr)
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crypto4xx_free_sa(ctx);
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rc = crypto4xx_alloc_sa(ctx, SA_AES128_LEN + (keylen-16) / 4);
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if (rc)
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return rc;
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if (ctx->state_record_dma_addr == 0) {
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rc = crypto4xx_alloc_state_record(ctx);
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if (rc) {
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crypto4xx_free_sa(ctx);
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return rc;
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}
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}
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/* Setup SA */
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sa = (struct dynamic_sa_ctl *) ctx->sa_in;
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ctx->hash_final = 0;
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set_dynamic_sa_command_0(sa, SA_NOT_SAVE_HASH, SA_NOT_SAVE_IV,
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SA_LOAD_HASH_FROM_SA, SA_LOAD_IV_FROM_STATE,
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SA_NO_HEADER_PROC, SA_HASH_ALG_NULL,
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SA_CIPHER_ALG_AES, SA_PAD_TYPE_ZERO,
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SA_OP_GROUP_BASIC, SA_OPCODE_DECRYPT,
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DIR_INBOUND);
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set_dynamic_sa_command_1(sa, cm, SA_HASH_MODE_HASH,
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fb, SA_EXTENDED_SN_OFF,
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SA_SEQ_MASK_OFF, SA_MC_ENABLE,
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SA_NOT_COPY_PAD, SA_NOT_COPY_PAYLOAD,
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SA_NOT_COPY_HDR);
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crypto4xx_memcpy_le(ctx->sa_in + get_dynamic_sa_offset_key_field(ctx),
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key, keylen);
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sa->sa_contents = SA_AES_CONTENTS | (keylen << 2);
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sa->sa_command_1.bf.key_len = keylen >> 3;
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ctx->is_hash = 0;
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ctx->direction = DIR_INBOUND;
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memcpy(ctx->sa_in + get_dynamic_sa_offset_state_ptr_field(ctx),
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(void *)&ctx->state_record_dma_addr, 4);
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ctx->offset_to_sr_ptr = get_dynamic_sa_offset_state_ptr_field(ctx);
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memcpy(ctx->sa_out, ctx->sa_in, ctx->sa_len * 4);
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sa = (struct dynamic_sa_ctl *) ctx->sa_out;
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sa->sa_command_0.bf.dir = DIR_OUTBOUND;
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return 0;
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}
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int crypto4xx_setkey_aes_cbc(struct crypto_ablkcipher *cipher,
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const u8 *key, unsigned int keylen)
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{
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return crypto4xx_setkey_aes(cipher, key, keylen, CRYPTO_MODE_CBC,
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CRYPTO_FEEDBACK_MODE_NO_FB);
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}
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/**
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* HASH SHA1 Functions
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*/
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static int crypto4xx_hash_alg_init(struct crypto_tfm *tfm,
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unsigned int sa_len,
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unsigned char ha,
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unsigned char hm)
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{
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struct crypto_alg *alg = tfm->__crt_alg;
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struct crypto4xx_alg *my_alg = crypto_alg_to_crypto4xx_alg(alg);
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struct crypto4xx_ctx *ctx = crypto_tfm_ctx(tfm);
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struct dynamic_sa_ctl *sa;
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struct dynamic_sa_hash160 *sa_in;
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int rc;
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ctx->dev = my_alg->dev;
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ctx->is_hash = 1;
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ctx->hash_final = 0;
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/* Create SA */
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if (ctx->sa_in_dma_addr || ctx->sa_out_dma_addr)
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crypto4xx_free_sa(ctx);
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rc = crypto4xx_alloc_sa(ctx, sa_len);
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if (rc)
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return rc;
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if (ctx->state_record_dma_addr == 0) {
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crypto4xx_alloc_state_record(ctx);
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if (!ctx->state_record_dma_addr) {
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crypto4xx_free_sa(ctx);
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return -ENOMEM;
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}
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}
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tfm->crt_ahash.reqsize = sizeof(struct crypto4xx_ctx);
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sa = (struct dynamic_sa_ctl *) ctx->sa_in;
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set_dynamic_sa_command_0(sa, SA_SAVE_HASH, SA_NOT_SAVE_IV,
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SA_NOT_LOAD_HASH, SA_LOAD_IV_FROM_SA,
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SA_NO_HEADER_PROC, ha, SA_CIPHER_ALG_NULL,
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SA_PAD_TYPE_ZERO, SA_OP_GROUP_BASIC,
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SA_OPCODE_HASH, DIR_INBOUND);
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set_dynamic_sa_command_1(sa, 0, SA_HASH_MODE_HASH,
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CRYPTO_FEEDBACK_MODE_NO_FB, SA_EXTENDED_SN_OFF,
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SA_SEQ_MASK_OFF, SA_MC_ENABLE,
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SA_NOT_COPY_PAD, SA_NOT_COPY_PAYLOAD,
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SA_NOT_COPY_HDR);
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ctx->direction = DIR_INBOUND;
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sa->sa_contents = SA_HASH160_CONTENTS;
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sa_in = (struct dynamic_sa_hash160 *) ctx->sa_in;
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/* Need to zero hash digest in SA */
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memset(sa_in->inner_digest, 0, sizeof(sa_in->inner_digest));
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memset(sa_in->outer_digest, 0, sizeof(sa_in->outer_digest));
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sa_in->state_ptr = ctx->state_record_dma_addr;
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ctx->offset_to_sr_ptr = get_dynamic_sa_offset_state_ptr_field(ctx);
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return 0;
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}
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int crypto4xx_hash_init(struct ahash_request *req)
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{
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struct crypto4xx_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
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int ds;
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struct dynamic_sa_ctl *sa;
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sa = (struct dynamic_sa_ctl *) ctx->sa_in;
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ds = crypto_ahash_digestsize(
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__crypto_ahash_cast(req->base.tfm));
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sa->sa_command_0.bf.digest_len = ds >> 2;
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sa->sa_command_0.bf.load_hash_state = SA_LOAD_HASH_FROM_SA;
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ctx->is_hash = 1;
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ctx->direction = DIR_INBOUND;
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return 0;
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}
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int crypto4xx_hash_update(struct ahash_request *req)
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{
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struct crypto4xx_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
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ctx->is_hash = 1;
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ctx->hash_final = 0;
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ctx->pd_ctl = 0x11;
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ctx->direction = DIR_INBOUND;
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return crypto4xx_build_pd(&req->base, ctx, req->src,
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(struct scatterlist *) req->result,
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req->nbytes, NULL, 0);
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}
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int crypto4xx_hash_final(struct ahash_request *req)
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{
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return 0;
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}
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int crypto4xx_hash_digest(struct ahash_request *req)
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{
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struct crypto4xx_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
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ctx->hash_final = 1;
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ctx->pd_ctl = 0x11;
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ctx->direction = DIR_INBOUND;
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return crypto4xx_build_pd(&req->base, ctx, req->src,
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(struct scatterlist *) req->result,
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req->nbytes, NULL, 0);
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}
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/**
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* SHA1 Algorithm
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*/
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int crypto4xx_sha1_alg_init(struct crypto_tfm *tfm)
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{
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return crypto4xx_hash_alg_init(tfm, SA_HASH160_LEN, SA_HASH_ALG_SHA1,
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SA_HASH_MODE_HASH);
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}
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,177 @@
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/**
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* AMCC SoC PPC4xx Crypto Driver
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*
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* Copyright (c) 2008 Applied Micro Circuits Corporation.
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* All rights reserved. James Hsiao <jhsiao@amcc.com>
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*
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* This program is free software; you can redistribute it and/or modify
|
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* it under the terms of the GNU General Public License as published by
|
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* the Free Software Foundation; either version 2 of the License, or
|
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
|
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* This is the header file for AMCC Crypto offload Linux device driver for
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* use with Linux CryptoAPI.
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*/
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#ifndef __CRYPTO4XX_CORE_H__
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#define __CRYPTO4XX_CORE_H__
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#define PPC460SX_SDR0_SRST 0x201
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#define PPC405EX_SDR0_SRST 0x200
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#define PPC460EX_SDR0_SRST 0x201
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#define PPC460EX_CE_RESET 0x08000000
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#define PPC460SX_CE_RESET 0x20000000
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#define PPC405EX_CE_RESET 0x00000008
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#define CRYPTO4XX_CRYPTO_PRIORITY 300
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#define PPC4XX_LAST_PD 63
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#define PPC4XX_NUM_PD 64
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#define PPC4XX_LAST_GD 1023
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#define PPC4XX_NUM_GD 1024
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#define PPC4XX_LAST_SD 63
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#define PPC4XX_NUM_SD 64
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#define PPC4XX_SD_BUFFER_SIZE 2048
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#define PD_ENTRY_INUSE 1
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#define PD_ENTRY_FREE 0
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#define ERING_WAS_FULL 0xffffffff
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struct crypto4xx_device;
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struct pd_uinfo {
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struct crypto4xx_device *dev;
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u32 state;
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u32 using_sd;
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u32 first_gd; /* first gather discriptor
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used by this packet */
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u32 num_gd; /* number of gather discriptor
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used by this packet */
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u32 first_sd; /* first scatter discriptor
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used by this packet */
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u32 num_sd; /* number of scatter discriptors
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used by this packet */
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void *sa_va; /* shadow sa, when using cp from ctx->sa */
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u32 sa_pa;
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void *sr_va; /* state record for shadow sa */
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u32 sr_pa;
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struct scatterlist *dest_va;
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struct crypto_async_request *async_req; /* base crypto request
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for this packet */
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};
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struct crypto4xx_device {
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struct crypto4xx_core_device *core_dev;
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char *name;
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u64 ce_phy_address;
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void __iomem *ce_base;
|
||||
|
||||
void *pdr; /* base address of packet
|
||||
descriptor ring */
|
||||
dma_addr_t pdr_pa; /* physical address used to
|
||||
program ce pdr_base_register */
|
||||
void *gdr; /* gather descriptor ring */
|
||||
dma_addr_t gdr_pa; /* physical address used to
|
||||
program ce gdr_base_register */
|
||||
void *sdr; /* scatter descriptor ring */
|
||||
dma_addr_t sdr_pa; /* physical address used to
|
||||
program ce sdr_base_register */
|
||||
void *scatter_buffer_va;
|
||||
dma_addr_t scatter_buffer_pa;
|
||||
u32 scatter_buffer_size;
|
||||
|
||||
void *shadow_sa_pool; /* pool of memory for sa in pd_uinfo */
|
||||
dma_addr_t shadow_sa_pool_pa;
|
||||
void *shadow_sr_pool; /* pool of memory for sr in pd_uinfo */
|
||||
dma_addr_t shadow_sr_pool_pa;
|
||||
u32 pdr_tail;
|
||||
u32 pdr_head;
|
||||
u32 gdr_tail;
|
||||
u32 gdr_head;
|
||||
u32 sdr_tail;
|
||||
u32 sdr_head;
|
||||
void *pdr_uinfo;
|
||||
struct list_head alg_list; /* List of algorithm supported
|
||||
by this device */
|
||||
};
|
||||
|
||||
struct crypto4xx_core_device {
|
||||
struct device *device;
|
||||
struct of_device *ofdev;
|
||||
struct crypto4xx_device *dev;
|
||||
u32 int_status;
|
||||
u32 irq;
|
||||
struct tasklet_struct tasklet;
|
||||
spinlock_t lock;
|
||||
};
|
||||
|
||||
struct crypto4xx_ctx {
|
||||
struct crypto4xx_device *dev;
|
||||
void *sa_in;
|
||||
dma_addr_t sa_in_dma_addr;
|
||||
void *sa_out;
|
||||
dma_addr_t sa_out_dma_addr;
|
||||
void *state_record;
|
||||
dma_addr_t state_record_dma_addr;
|
||||
u32 sa_len;
|
||||
u32 offset_to_sr_ptr; /* offset to state ptr, in dynamic sa */
|
||||
u32 direction;
|
||||
u32 next_hdr;
|
||||
u32 save_iv;
|
||||
u32 pd_ctl_len;
|
||||
u32 pd_ctl;
|
||||
u32 bypass;
|
||||
u32 is_hash;
|
||||
u32 hash_final;
|
||||
};
|
||||
|
||||
struct crypto4xx_req_ctx {
|
||||
struct crypto4xx_device *dev; /* Device in which
|
||||
operation to send to */
|
||||
void *sa;
|
||||
u32 sa_dma_addr;
|
||||
u16 sa_len;
|
||||
};
|
||||
|
||||
struct crypto4xx_alg {
|
||||
struct list_head entry;
|
||||
struct crypto_alg alg;
|
||||
struct crypto4xx_device *dev;
|
||||
};
|
||||
|
||||
#define crypto_alg_to_crypto4xx_alg(x) \
|
||||
container_of(x, struct crypto4xx_alg, alg)
|
||||
|
||||
extern int crypto4xx_alloc_sa(struct crypto4xx_ctx *ctx, u32 size);
|
||||
extern void crypto4xx_free_sa(struct crypto4xx_ctx *ctx);
|
||||
extern u32 crypto4xx_alloc_sa_rctx(struct crypto4xx_ctx *ctx,
|
||||
struct crypto4xx_ctx *rctx);
|
||||
extern void crypto4xx_free_sa_rctx(struct crypto4xx_ctx *rctx);
|
||||
extern void crypto4xx_free_ctx(struct crypto4xx_ctx *ctx);
|
||||
extern u32 crypto4xx_alloc_state_record(struct crypto4xx_ctx *ctx);
|
||||
extern u32 get_dynamic_sa_offset_state_ptr_field(struct crypto4xx_ctx *ctx);
|
||||
extern u32 get_dynamic_sa_offset_key_field(struct crypto4xx_ctx *ctx);
|
||||
extern u32 get_dynamic_sa_iv_size(struct crypto4xx_ctx *ctx);
|
||||
extern void crypto4xx_memcpy_le(unsigned int *dst,
|
||||
const unsigned char *buf, int len);
|
||||
extern u32 crypto4xx_build_pd(struct crypto_async_request *req,
|
||||
struct crypto4xx_ctx *ctx,
|
||||
struct scatterlist *src,
|
||||
struct scatterlist *dst,
|
||||
unsigned int datalen,
|
||||
void *iv, u32 iv_len);
|
||||
extern int crypto4xx_setkey_aes_cbc(struct crypto_ablkcipher *cipher,
|
||||
const u8 *key, unsigned int keylen);
|
||||
extern int crypto4xx_encrypt(struct ablkcipher_request *req);
|
||||
extern int crypto4xx_decrypt(struct ablkcipher_request *req);
|
||||
extern int crypto4xx_sha1_alg_init(struct crypto_tfm *tfm);
|
||||
extern int crypto4xx_hash_digest(struct ahash_request *req);
|
||||
extern int crypto4xx_hash_final(struct ahash_request *req);
|
||||
extern int crypto4xx_hash_update(struct ahash_request *req);
|
||||
extern int crypto4xx_hash_init(struct ahash_request *req);
|
||||
#endif
|
||||
|
|
@ -0,0 +1,284 @@
|
|||
/**
|
||||
* AMCC SoC PPC4xx Crypto Driver
|
||||
*
|
||||
* Copyright (c) 2008 Applied Micro Circuits Corporation.
|
||||
* All rights reserved. James Hsiao <jhsiao@amcc.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* This filr defines the register set for Security Subsystem
|
||||
*/
|
||||
|
||||
#ifndef __CRYPTO4XX_REG_DEF_H__
|
||||
#define __CRYPTO4XX_REG_DEF_H__
|
||||
|
||||
/* CRYPTO4XX Register offset */
|
||||
#define CRYPTO4XX_DESCRIPTOR 0x00000000
|
||||
#define CRYPTO4XX_CTRL_STAT 0x00000000
|
||||
#define CRYPTO4XX_SOURCE 0x00000004
|
||||
#define CRYPTO4XX_DEST 0x00000008
|
||||
#define CRYPTO4XX_SA 0x0000000C
|
||||
#define CRYPTO4XX_SA_LENGTH 0x00000010
|
||||
#define CRYPTO4XX_LENGTH 0x00000014
|
||||
|
||||
#define CRYPTO4XX_PE_DMA_CFG 0x00000040
|
||||
#define CRYPTO4XX_PE_DMA_STAT 0x00000044
|
||||
#define CRYPTO4XX_PDR_BASE 0x00000048
|
||||
#define CRYPTO4XX_RDR_BASE 0x0000004c
|
||||
#define CRYPTO4XX_RING_SIZE 0x00000050
|
||||
#define CRYPTO4XX_RING_CTRL 0x00000054
|
||||
#define CRYPTO4XX_INT_RING_STAT 0x00000058
|
||||
#define CRYPTO4XX_EXT_RING_STAT 0x0000005c
|
||||
#define CRYPTO4XX_IO_THRESHOLD 0x00000060
|
||||
#define CRYPTO4XX_GATH_RING_BASE 0x00000064
|
||||
#define CRYPTO4XX_SCAT_RING_BASE 0x00000068
|
||||
#define CRYPTO4XX_PART_RING_SIZE 0x0000006c
|
||||
#define CRYPTO4XX_PART_RING_CFG 0x00000070
|
||||
|
||||
#define CRYPTO4XX_PDR_BASE_UADDR 0x00000080
|
||||
#define CRYPTO4XX_RDR_BASE_UADDR 0x00000084
|
||||
#define CRYPTO4XX_PKT_SRC_UADDR 0x00000088
|
||||
#define CRYPTO4XX_PKT_DEST_UADDR 0x0000008c
|
||||
#define CRYPTO4XX_SA_UADDR 0x00000090
|
||||
#define CRYPTO4XX_GATH_RING_BASE_UADDR 0x000000A0
|
||||
#define CRYPTO4XX_SCAT_RING_BASE_UADDR 0x000000A4
|
||||
|
||||
#define CRYPTO4XX_SEQ_RD 0x00000408
|
||||
#define CRYPTO4XX_SEQ_MASK_RD 0x0000040C
|
||||
|
||||
#define CRYPTO4XX_SA_CMD_0 0x00010600
|
||||
#define CRYPTO4XX_SA_CMD_1 0x00010604
|
||||
|
||||
#define CRYPTO4XX_STATE_PTR 0x000106dc
|
||||
#define CRYPTO4XX_STATE_IV 0x00010700
|
||||
#define CRYPTO4XX_STATE_HASH_BYTE_CNT_0 0x00010710
|
||||
#define CRYPTO4XX_STATE_HASH_BYTE_CNT_1 0x00010714
|
||||
|
||||
#define CRYPTO4XX_STATE_IDIGEST_0 0x00010718
|
||||
#define CRYPTO4XX_STATE_IDIGEST_1 0x0001071c
|
||||
|
||||
#define CRYPTO4XX_DATA_IN 0x00018000
|
||||
#define CRYPTO4XX_DATA_OUT 0x0001c000
|
||||
|
||||
#define CRYPTO4XX_INT_UNMASK_STAT 0x000500a0
|
||||
#define CRYPTO4XX_INT_MASK_STAT 0x000500a4
|
||||
#define CRYPTO4XX_INT_CLR 0x000500a4
|
||||
#define CRYPTO4XX_INT_EN 0x000500a8
|
||||
|
||||
#define CRYPTO4XX_INT_PKA 0x00000002
|
||||
#define CRYPTO4XX_INT_PDR_DONE 0x00008000
|
||||
#define CRYPTO4XX_INT_MA_WR_ERR 0x00020000
|
||||
#define CRYPTO4XX_INT_MA_RD_ERR 0x00010000
|
||||
#define CRYPTO4XX_INT_PE_ERR 0x00000200
|
||||
#define CRYPTO4XX_INT_USER_DMA_ERR 0x00000040
|
||||
#define CRYPTO4XX_INT_SLAVE_ERR 0x00000010
|
||||
#define CRYPTO4XX_INT_MASTER_ERR 0x00000008
|
||||
#define CRYPTO4XX_INT_ERROR 0x00030258
|
||||
|
||||
#define CRYPTO4XX_INT_CFG 0x000500ac
|
||||
#define CRYPTO4XX_INT_DESCR_RD 0x000500b0
|
||||
#define CRYPTO4XX_INT_DESCR_CNT 0x000500b4
|
||||
#define CRYPTO4XX_INT_TIMEOUT_CNT 0x000500b8
|
||||
|
||||
#define CRYPTO4XX_DEVICE_CTRL 0x00060080
|
||||
#define CRYPTO4XX_DEVICE_ID 0x00060084
|
||||
#define CRYPTO4XX_DEVICE_INFO 0x00060088
|
||||
#define CRYPTO4XX_DMA_USER_SRC 0x00060094
|
||||
#define CRYPTO4XX_DMA_USER_DEST 0x00060098
|
||||
#define CRYPTO4XX_DMA_USER_CMD 0x0006009C
|
||||
|
||||
#define CRYPTO4XX_DMA_CFG 0x000600d4
|
||||
#define CRYPTO4XX_BYTE_ORDER_CFG 0x000600d8
|
||||
#define CRYPTO4XX_ENDIAN_CFG 0x000600d8
|
||||
|
||||
#define CRYPTO4XX_PRNG_STAT 0x00070000
|
||||
#define CRYPTO4XX_PRNG_CTRL 0x00070004
|
||||
#define CRYPTO4XX_PRNG_SEED_L 0x00070008
|
||||
#define CRYPTO4XX_PRNG_SEED_H 0x0007000c
|
||||
|
||||
#define CRYPTO4XX_PRNG_RES_0 0x00070020
|
||||
#define CRYPTO4XX_PRNG_RES_1 0x00070024
|
||||
#define CRYPTO4XX_PRNG_RES_2 0x00070028
|
||||
#define CRYPTO4XX_PRNG_RES_3 0x0007002C
|
||||
|
||||
#define CRYPTO4XX_PRNG_LFSR_L 0x00070030
|
||||
#define CRYPTO4XX_PRNG_LFSR_H 0x00070034
|
||||
|
||||
/**
|
||||
* Initilize CRYPTO ENGINE registers, and memory bases.
|
||||
*/
|
||||
#define PPC4XX_PDR_POLL 0x3ff
|
||||
#define PPC4XX_OUTPUT_THRESHOLD 2
|
||||
#define PPC4XX_INPUT_THRESHOLD 2
|
||||
#define PPC4XX_PD_SIZE 6
|
||||
#define PPC4XX_CTX_DONE_INT 0x2000
|
||||
#define PPC4XX_PD_DONE_INT 0x8000
|
||||
#define PPC4XX_BYTE_ORDER 0x22222
|
||||
#define PPC4XX_INTERRUPT_CLR 0x3ffff
|
||||
#define PPC4XX_PRNG_CTRL_AUTO_EN 0x3
|
||||
#define PPC4XX_DC_3DES_EN 1
|
||||
#define PPC4XX_INT_DESCR_CNT 4
|
||||
#define PPC4XX_INT_TIMEOUT_CNT 0
|
||||
#define PPC4XX_INT_CFG 1
|
||||
/**
|
||||
* all follow define are ad hoc
|
||||
*/
|
||||
#define PPC4XX_RING_RETRY 100
|
||||
#define PPC4XX_RING_POLL 100
|
||||
#define PPC4XX_SDR_SIZE PPC4XX_NUM_SD
|
||||
#define PPC4XX_GDR_SIZE PPC4XX_NUM_GD
|
||||
|
||||
/**
|
||||
* Generic Security Association (SA) with all possible fields. These will
|
||||
* never likely used except for reference purpose. These structure format
|
||||
* can be not changed as the hardware expects them to be layout as defined.
|
||||
* Field can be removed or reduced but ordering can not be changed.
|
||||
*/
|
||||
#define CRYPTO4XX_DMA_CFG_OFFSET 0x40
|
||||
union ce_pe_dma_cfg {
|
||||
struct {
|
||||
u32 rsv:7;
|
||||
u32 dir_host:1;
|
||||
u32 rsv1:2;
|
||||
u32 bo_td_en:1;
|
||||
u32 dis_pdr_upd:1;
|
||||
u32 bo_sgpd_en:1;
|
||||
u32 bo_data_en:1;
|
||||
u32 bo_sa_en:1;
|
||||
u32 bo_pd_en:1;
|
||||
u32 rsv2:4;
|
||||
u32 dynamic_sa_en:1;
|
||||
u32 pdr_mode:2;
|
||||
u32 pe_mode:1;
|
||||
u32 rsv3:5;
|
||||
u32 reset_sg:1;
|
||||
u32 reset_pdr:1;
|
||||
u32 reset_pe:1;
|
||||
} bf;
|
||||
u32 w;
|
||||
} __attribute__((packed));
|
||||
|
||||
#define CRYPTO4XX_PDR_BASE_OFFSET 0x48
|
||||
#define CRYPTO4XX_RDR_BASE_OFFSET 0x4c
|
||||
#define CRYPTO4XX_RING_SIZE_OFFSET 0x50
|
||||
union ce_ring_size {
|
||||
struct {
|
||||
u32 ring_offset:16;
|
||||
u32 rsv:6;
|
||||
u32 ring_size:10;
|
||||
} bf;
|
||||
u32 w;
|
||||
} __attribute__((packed));
|
||||
|
||||
#define CRYPTO4XX_RING_CONTROL_OFFSET 0x54
|
||||
union ce_ring_contol {
|
||||
struct {
|
||||
u32 continuous:1;
|
||||
u32 rsv:5;
|
||||
u32 ring_retry_divisor:10;
|
||||
u32 rsv1:4;
|
||||
u32 ring_poll_divisor:10;
|
||||
} bf;
|
||||
u32 w;
|
||||
} __attribute__((packed));
|
||||
|
||||
#define CRYPTO4XX_IO_THRESHOLD_OFFSET 0x60
|
||||
union ce_io_threshold {
|
||||
struct {
|
||||
u32 rsv:6;
|
||||
u32 output_threshold:10;
|
||||
u32 rsv1:6;
|
||||
u32 input_threshold:10;
|
||||
} bf;
|
||||
u32 w;
|
||||
} __attribute__((packed));
|
||||
|
||||
#define CRYPTO4XX_GATHER_RING_BASE_OFFSET 0x64
|
||||
#define CRYPTO4XX_SCATTER_RING_BASE_OFFSET 0x68
|
||||
|
||||
union ce_part_ring_size {
|
||||
struct {
|
||||
u32 sdr_size:16;
|
||||
u32 gdr_size:16;
|
||||
} bf;
|
||||
u32 w;
|
||||
} __attribute__((packed));
|
||||
|
||||
#define MAX_BURST_SIZE_32 0
|
||||
#define MAX_BURST_SIZE_64 1
|
||||
#define MAX_BURST_SIZE_128 2
|
||||
#define MAX_BURST_SIZE_256 3
|
||||
|
||||
/* gather descriptor control length */
|
||||
struct gd_ctl_len {
|
||||
u32 len:16;
|
||||
u32 rsv:14;
|
||||
u32 done:1;
|
||||
u32 ready:1;
|
||||
} __attribute__((packed));
|
||||
|
||||
struct ce_gd {
|
||||
u32 ptr;
|
||||
struct gd_ctl_len ctl_len;
|
||||
} __attribute__((packed));
|
||||
|
||||
struct sd_ctl {
|
||||
u32 ctl:30;
|
||||
u32 done:1;
|
||||
u32 rdy:1;
|
||||
} __attribute__((packed));
|
||||
|
||||
struct ce_sd {
|
||||
u32 ptr;
|
||||
struct sd_ctl ctl;
|
||||
} __attribute__((packed));
|
||||
|
||||
#define PD_PAD_CTL_32 0x10
|
||||
#define PD_PAD_CTL_64 0x20
|
||||
#define PD_PAD_CTL_128 0x40
|
||||
#define PD_PAD_CTL_256 0x80
|
||||
union ce_pd_ctl {
|
||||
struct {
|
||||
u32 pd_pad_ctl:8;
|
||||
u32 status:8;
|
||||
u32 next_hdr:8;
|
||||
u32 rsv:2;
|
||||
u32 cached_sa:1;
|
||||
u32 hash_final:1;
|
||||
u32 init_arc4:1;
|
||||
u32 rsv1:1;
|
||||
u32 pe_done:1;
|
||||
u32 host_ready:1;
|
||||
} bf;
|
||||
u32 w;
|
||||
} __attribute__((packed));
|
||||
|
||||
union ce_pd_ctl_len {
|
||||
struct {
|
||||
u32 bypass:8;
|
||||
u32 pe_done:1;
|
||||
u32 host_ready:1;
|
||||
u32 rsv:2;
|
||||
u32 pkt_len:20;
|
||||
} bf;
|
||||
u32 w;
|
||||
} __attribute__((packed));
|
||||
|
||||
struct ce_pd {
|
||||
union ce_pd_ctl pd_ctl;
|
||||
u32 src;
|
||||
u32 dest;
|
||||
u32 sa; /* get from ctx->sa_dma_addr */
|
||||
u32 sa_len; /* only if dynamic sa is used */
|
||||
union ce_pd_ctl_len pd_ctl_len;
|
||||
|
||||
} __attribute__((packed));
|
||||
#endif
|
||||
|
|
@ -0,0 +1,108 @@
|
|||
/**
|
||||
* AMCC SoC PPC4xx Crypto Driver
|
||||
*
|
||||
* Copyright (c) 2008 Applied Micro Circuits Corporation.
|
||||
* All rights reserved. James Hsiao <jhsiao@amcc.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* @file crypto4xx_sa.c
|
||||
*
|
||||
* This file implements the security context
|
||||
* assoicate format.
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/moduleparam.h>
|
||||
#include <linux/mod_devicetable.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/spinlock_types.h>
|
||||
#include <linux/highmem.h>
|
||||
#include <linux/scatterlist.h>
|
||||
#include <linux/crypto.h>
|
||||
#include <crypto/algapi.h>
|
||||
#include <crypto/des.h>
|
||||
#include "crypto4xx_reg_def.h"
|
||||
#include "crypto4xx_sa.h"
|
||||
#include "crypto4xx_core.h"
|
||||
|
||||
u32 get_dynamic_sa_offset_iv_field(struct crypto4xx_ctx *ctx)
|
||||
{
|
||||
u32 offset;
|
||||
union dynamic_sa_contents cts;
|
||||
|
||||
if (ctx->direction == DIR_INBOUND)
|
||||
cts.w = ((struct dynamic_sa_ctl *)(ctx->sa_in))->sa_contents;
|
||||
else
|
||||
cts.w = ((struct dynamic_sa_ctl *)(ctx->sa_out))->sa_contents;
|
||||
offset = cts.bf.key_size
|
||||
+ cts.bf.inner_size
|
||||
+ cts.bf.outer_size
|
||||
+ cts.bf.spi
|
||||
+ cts.bf.seq_num0
|
||||
+ cts.bf.seq_num1
|
||||
+ cts.bf.seq_num_mask0
|
||||
+ cts.bf.seq_num_mask1
|
||||
+ cts.bf.seq_num_mask2
|
||||
+ cts.bf.seq_num_mask3;
|
||||
|
||||
return sizeof(struct dynamic_sa_ctl) + offset * 4;
|
||||
}
|
||||
|
||||
u32 get_dynamic_sa_offset_state_ptr_field(struct crypto4xx_ctx *ctx)
|
||||
{
|
||||
u32 offset;
|
||||
union dynamic_sa_contents cts;
|
||||
|
||||
if (ctx->direction == DIR_INBOUND)
|
||||
cts.w = ((struct dynamic_sa_ctl *) ctx->sa_in)->sa_contents;
|
||||
else
|
||||
cts.w = ((struct dynamic_sa_ctl *) ctx->sa_out)->sa_contents;
|
||||
offset = cts.bf.key_size
|
||||
+ cts.bf.inner_size
|
||||
+ cts.bf.outer_size
|
||||
+ cts.bf.spi
|
||||
+ cts.bf.seq_num0
|
||||
+ cts.bf.seq_num1
|
||||
+ cts.bf.seq_num_mask0
|
||||
+ cts.bf.seq_num_mask1
|
||||
+ cts.bf.seq_num_mask2
|
||||
+ cts.bf.seq_num_mask3
|
||||
+ cts.bf.iv0
|
||||
+ cts.bf.iv1
|
||||
+ cts.bf.iv2
|
||||
+ cts.bf.iv3;
|
||||
|
||||
return sizeof(struct dynamic_sa_ctl) + offset * 4;
|
||||
}
|
||||
|
||||
u32 get_dynamic_sa_iv_size(struct crypto4xx_ctx *ctx)
|
||||
{
|
||||
union dynamic_sa_contents cts;
|
||||
|
||||
if (ctx->direction == DIR_INBOUND)
|
||||
cts.w = ((struct dynamic_sa_ctl *) ctx->sa_in)->sa_contents;
|
||||
else
|
||||
cts.w = ((struct dynamic_sa_ctl *) ctx->sa_out)->sa_contents;
|
||||
return (cts.bf.iv0 + cts.bf.iv1 + cts.bf.iv2 + cts.bf.iv3) * 4;
|
||||
}
|
||||
|
||||
u32 get_dynamic_sa_offset_key_field(struct crypto4xx_ctx *ctx)
|
||||
{
|
||||
union dynamic_sa_contents cts;
|
||||
|
||||
if (ctx->direction == DIR_INBOUND)
|
||||
cts.w = ((struct dynamic_sa_ctl *) ctx->sa_in)->sa_contents;
|
||||
else
|
||||
cts.w = ((struct dynamic_sa_ctl *) ctx->sa_out)->sa_contents;
|
||||
|
||||
return sizeof(struct dynamic_sa_ctl);
|
||||
}
|
||||
|
|
@ -0,0 +1,243 @@
|
|||
/**
|
||||
* AMCC SoC PPC4xx Crypto Driver
|
||||
*
|
||||
* Copyright (c) 2008 Applied Micro Circuits Corporation.
|
||||
* All rights reserved. James Hsiao <jhsiao@amcc.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* This file defines the security context
|
||||
* assoicate format.
|
||||
*/
|
||||
|
||||
#ifndef __CRYPTO4XX_SA_H__
|
||||
#define __CRYPTO4XX_SA_H__
|
||||
|
||||
#define AES_IV_SIZE 16
|
||||
|
||||
/**
|
||||
* Contents of Dynamic Security Association (SA) with all possible fields
|
||||
*/
|
||||
union dynamic_sa_contents {
|
||||
struct {
|
||||
u32 arc4_state_ptr:1;
|
||||
u32 arc4_ij_ptr:1;
|
||||
u32 state_ptr:1;
|
||||
u32 iv3:1;
|
||||
u32 iv2:1;
|
||||
u32 iv1:1;
|
||||
u32 iv0:1;
|
||||
u32 seq_num_mask3:1;
|
||||
u32 seq_num_mask2:1;
|
||||
u32 seq_num_mask1:1;
|
||||
u32 seq_num_mask0:1;
|
||||
u32 seq_num1:1;
|
||||
u32 seq_num0:1;
|
||||
u32 spi:1;
|
||||
u32 outer_size:5;
|
||||
u32 inner_size:5;
|
||||
u32 key_size:4;
|
||||
u32 cmd_size:4;
|
||||
} bf;
|
||||
u32 w;
|
||||
} __attribute__((packed));
|
||||
|
||||
#define DIR_OUTBOUND 0
|
||||
#define DIR_INBOUND 1
|
||||
#define SA_OP_GROUP_BASIC 0
|
||||
#define SA_OPCODE_ENCRYPT 0
|
||||
#define SA_OPCODE_DECRYPT 0
|
||||
#define SA_OPCODE_HASH 3
|
||||
#define SA_CIPHER_ALG_DES 0
|
||||
#define SA_CIPHER_ALG_3DES 1
|
||||
#define SA_CIPHER_ALG_ARC4 2
|
||||
#define SA_CIPHER_ALG_AES 3
|
||||
#define SA_CIPHER_ALG_KASUMI 4
|
||||
#define SA_CIPHER_ALG_NULL 15
|
||||
|
||||
#define SA_HASH_ALG_MD5 0
|
||||
#define SA_HASH_ALG_SHA1 1
|
||||
#define SA_HASH_ALG_NULL 15
|
||||
#define SA_HASH_ALG_SHA1_DIGEST_SIZE 20
|
||||
|
||||
#define SA_LOAD_HASH_FROM_SA 0
|
||||
#define SA_LOAD_HASH_FROM_STATE 2
|
||||
#define SA_NOT_LOAD_HASH 3
|
||||
#define SA_LOAD_IV_FROM_SA 0
|
||||
#define SA_LOAD_IV_FROM_INPUT 1
|
||||
#define SA_LOAD_IV_FROM_STATE 2
|
||||
#define SA_LOAD_IV_GEN_IV 3
|
||||
|
||||
#define SA_PAD_TYPE_CONSTANT 2
|
||||
#define SA_PAD_TYPE_ZERO 3
|
||||
#define SA_PAD_TYPE_TLS 5
|
||||
#define SA_PAD_TYPE_DTLS 5
|
||||
#define SA_NOT_SAVE_HASH 0
|
||||
#define SA_SAVE_HASH 1
|
||||
#define SA_NOT_SAVE_IV 0
|
||||
#define SA_SAVE_IV 1
|
||||
#define SA_HEADER_PROC 1
|
||||
#define SA_NO_HEADER_PROC 0
|
||||
|
||||
union sa_command_0 {
|
||||
struct {
|
||||
u32 scatter:1;
|
||||
u32 gather:1;
|
||||
u32 save_hash_state:1;
|
||||
u32 save_iv:1;
|
||||
u32 load_hash_state:2;
|
||||
u32 load_iv:2;
|
||||
u32 digest_len:4;
|
||||
u32 hdr_proc:1;
|
||||
u32 extend_pad:1;
|
||||
u32 stream_cipher_pad:1;
|
||||
u32 rsv:1;
|
||||
u32 hash_alg:4;
|
||||
u32 cipher_alg:4;
|
||||
u32 pad_type:2;
|
||||
u32 op_group:2;
|
||||
u32 dir:1;
|
||||
u32 opcode:3;
|
||||
} bf;
|
||||
u32 w;
|
||||
} __attribute__((packed));
|
||||
|
||||
#define CRYPTO_MODE_ECB 0
|
||||
#define CRYPTO_MODE_CBC 1
|
||||
|
||||
#define CRYPTO_FEEDBACK_MODE_NO_FB 0
|
||||
#define CRYPTO_FEEDBACK_MODE_64BIT_OFB 0
|
||||
#define CRYPTO_FEEDBACK_MODE_8BIT_CFB 1
|
||||
#define CRYPTO_FEEDBACK_MODE_1BIT_CFB 2
|
||||
#define CRYPTO_FEEDBACK_MODE_128BIT_CFB 3
|
||||
|
||||
#define SA_AES_KEY_LEN_128 2
|
||||
#define SA_AES_KEY_LEN_192 3
|
||||
#define SA_AES_KEY_LEN_256 4
|
||||
|
||||
#define SA_REV2 1
|
||||
/**
|
||||
* The follow defines bits sa_command_1
|
||||
* In Basic hash mode this bit define simple hash or hmac.
|
||||
* In IPsec mode, this bit define muting control.
|
||||
*/
|
||||
#define SA_HASH_MODE_HASH 0
|
||||
#define SA_HASH_MODE_HMAC 1
|
||||
#define SA_MC_ENABLE 0
|
||||
#define SA_MC_DISABLE 1
|
||||
#define SA_NOT_COPY_HDR 0
|
||||
#define SA_COPY_HDR 1
|
||||
#define SA_NOT_COPY_PAD 0
|
||||
#define SA_COPY_PAD 1
|
||||
#define SA_NOT_COPY_PAYLOAD 0
|
||||
#define SA_COPY_PAYLOAD 1
|
||||
#define SA_EXTENDED_SN_OFF 0
|
||||
#define SA_EXTENDED_SN_ON 1
|
||||
#define SA_SEQ_MASK_OFF 0
|
||||
#define SA_SEQ_MASK_ON 1
|
||||
|
||||
union sa_command_1 {
|
||||
struct {
|
||||
u32 crypto_mode31:1;
|
||||
u32 save_arc4_state:1;
|
||||
u32 arc4_stateful:1;
|
||||
u32 key_len:5;
|
||||
u32 hash_crypto_offset:8;
|
||||
u32 sa_rev:2;
|
||||
u32 byte_offset:1;
|
||||
u32 hmac_muting:1;
|
||||
u32 feedback_mode:2;
|
||||
u32 crypto_mode9_8:2;
|
||||
u32 extended_seq_num:1;
|
||||
u32 seq_num_mask:1;
|
||||
u32 mutable_bit_proc:1;
|
||||
u32 ip_version:1;
|
||||
u32 copy_pad:1;
|
||||
u32 copy_payload:1;
|
||||
u32 copy_hdr:1;
|
||||
u32 rsv1:1;
|
||||
} bf;
|
||||
u32 w;
|
||||
} __attribute__((packed));
|
||||
|
||||
struct dynamic_sa_ctl {
|
||||
u32 sa_contents;
|
||||
union sa_command_0 sa_command_0;
|
||||
union sa_command_1 sa_command_1;
|
||||
} __attribute__((packed));
|
||||
|
||||
/**
|
||||
* State Record for Security Association (SA)
|
||||
*/
|
||||
struct sa_state_record {
|
||||
u32 save_iv[4];
|
||||
u32 save_hash_byte_cnt[2];
|
||||
u32 save_digest[16];
|
||||
} __attribute__((packed));
|
||||
|
||||
/**
|
||||
* Security Association (SA) for AES128
|
||||
*
|
||||
*/
|
||||
struct dynamic_sa_aes128 {
|
||||
struct dynamic_sa_ctl ctrl;
|
||||
u32 key[4];
|
||||
u32 iv[4]; /* for CBC, OFC, and CFB mode */
|
||||
u32 state_ptr;
|
||||
u32 reserved;
|
||||
} __attribute__((packed));
|
||||
|
||||
#define SA_AES128_LEN (sizeof(struct dynamic_sa_aes128)/4)
|
||||
#define SA_AES128_CONTENTS 0x3e000042
|
||||
|
||||
/*
|
||||
* Security Association (SA) for AES192
|
||||
*/
|
||||
struct dynamic_sa_aes192 {
|
||||
struct dynamic_sa_ctl ctrl;
|
||||
u32 key[6];
|
||||
u32 iv[4]; /* for CBC, OFC, and CFB mode */
|
||||
u32 state_ptr;
|
||||
u32 reserved;
|
||||
} __attribute__((packed));
|
||||
|
||||
#define SA_AES192_LEN (sizeof(struct dynamic_sa_aes192)/4)
|
||||
#define SA_AES192_CONTENTS 0x3e000062
|
||||
|
||||
/**
|
||||
* Security Association (SA) for AES256
|
||||
*/
|
||||
struct dynamic_sa_aes256 {
|
||||
struct dynamic_sa_ctl ctrl;
|
||||
u32 key[8];
|
||||
u32 iv[4]; /* for CBC, OFC, and CFB mode */
|
||||
u32 state_ptr;
|
||||
u32 reserved;
|
||||
} __attribute__((packed));
|
||||
|
||||
#define SA_AES256_LEN (sizeof(struct dynamic_sa_aes256)/4)
|
||||
#define SA_AES256_CONTENTS 0x3e000082
|
||||
#define SA_AES_CONTENTS 0x3e000002
|
||||
|
||||
/**
|
||||
* Security Association (SA) for HASH160: HMAC-SHA1
|
||||
*/
|
||||
struct dynamic_sa_hash160 {
|
||||
struct dynamic_sa_ctl ctrl;
|
||||
u32 inner_digest[5];
|
||||
u32 outer_digest[5];
|
||||
u32 state_ptr;
|
||||
u32 reserved;
|
||||
} __attribute__((packed));
|
||||
#define SA_HASH160_LEN (sizeof(struct dynamic_sa_hash160)/4)
|
||||
#define SA_HASH160_CONTENTS 0x2000a502
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue