mirror of https://gitee.com/openkylin/linux.git
mtd: nand: vf610_nfc: add hardware BCH-ECC support
This adds hardware ECC support using the BCH encoder in the NFC IP. The ECC encoder supports up to 32-bit correction by using 60 error correction bytes. There is no sub-page ECC step, ECC is calculated always across the whole page (up to 2k pages). Limitations: - HW ECC: Only 2K page with 64+ OOB. - HW ECC: Only 24 and 32-bit error correction implemented. Raw writes have been tested using the generic nand_write_page_raw implementation. However, raw reads are currently not possible because the controller need to know whether we are going to use the ECC mode already at NAND_CMD_READ0 command time. At this point we do not have the information whether it is a raw read or a regular read at driver level... Signed-off-by: Bill Pringlemeir <bpringlemeir@nbsps.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This commit is contained in:
Stefan Agner
Brian Norris
parent
456930d80a
commit
049f425099
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@ -466,8 +466,10 @@ config MTD_NAND_VF610_NFC
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help
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Enables support for NAND Flash Controller on some Freescale
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processors like the VF610, MPC5125, MCF54418 or Kinetis K70.
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The driver supports a maximum 2k page size. The driver
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currently does not support hardware ECC.
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The driver supports a maximum 2k page size. With 2k pages and
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64 bytes or more of OOB, hardware ECC with up to 32-bit error
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correction is supported. Hardware ECC is only enabled through
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device tree.
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config MTD_NAND_MXC
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tristate "MXC NAND support"
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@ -19,8 +19,8 @@
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* - Untested on MPC5125 and M54418.
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* - DMA and pipelining not used.
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* - 2K pages or less.
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* - No chip select, one NAND chip per controller.
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* - No hardware ECC.
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* - HW ECC: Only 2K page with 64+ OOB.
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* - HW ECC: Only 24 and 32-bit error correction implemented.
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*/
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#include <linux/module.h>
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@ -77,6 +77,8 @@
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/* NFC ECC mode define */
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#define ECC_BYPASS 0
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#define ECC_45_BYTE 6
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#define ECC_60_BYTE 7
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/*** Register Mask and bit definitions */
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@ -129,6 +131,18 @@
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#define CMD_DONE_CLEAR_BIT BIT(18)
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#define IDLE_CLEAR_BIT BIT(17)
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/*
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* ECC status - seems to consume 8 bytes (double word). The documented
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* status byte is located in the lowest byte of the second word (which is
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* the 4th or 7th byte depending on endianness).
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* Calculate an offset to store the ECC status at the end of the buffer.
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*/
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#define ECC_SRAM_ADDR (PAGE_2K + OOB_MAX - 8)
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#define ECC_STATUS 0x4
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#define ECC_STATUS_MASK 0x80
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#define ECC_STATUS_ERR_COUNT 0x3F
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enum vf610_nfc_alt_buf {
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ALT_BUF_DATA = 0,
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ALT_BUF_ID = 1,
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@ -152,10 +166,40 @@ struct vf610_nfc {
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enum vf610_nfc_alt_buf alt_buf;
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enum vf610_nfc_variant variant;
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struct clk *clk;
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bool use_hw_ecc;
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u32 ecc_mode;
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};
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#define mtd_to_nfc(_mtd) container_of(_mtd, struct vf610_nfc, mtd)
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static struct nand_ecclayout vf610_nfc_ecc45 = {
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.eccbytes = 45,
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.eccpos = {19, 20, 21, 22, 23,
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24, 25, 26, 27, 28, 29, 30, 31,
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32, 33, 34, 35, 36, 37, 38, 39,
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40, 41, 42, 43, 44, 45, 46, 47,
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48, 49, 50, 51, 52, 53, 54, 55,
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56, 57, 58, 59, 60, 61, 62, 63},
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.oobfree = {
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{.offset = 2,
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.length = 17} }
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};
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static struct nand_ecclayout vf610_nfc_ecc60 = {
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.eccbytes = 60,
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.eccpos = { 4, 5, 6, 7, 8, 9, 10, 11,
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12, 13, 14, 15, 16, 17, 18, 19,
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20, 21, 22, 23, 24, 25, 26, 27,
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28, 29, 30, 31, 32, 33, 34, 35,
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36, 37, 38, 39, 40, 41, 42, 43,
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44, 45, 46, 47, 48, 49, 50, 51,
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52, 53, 54, 55, 56, 57, 58, 59,
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60, 61, 62, 63 },
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.oobfree = {
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{.offset = 2,
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.length = 2} }
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};
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static inline u32 vf610_nfc_read(struct vf610_nfc *nfc, uint reg)
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{
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return readl(nfc->regs + reg);
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@ -297,6 +341,13 @@ static void vf610_nfc_addr_cycle(struct vf610_nfc *nfc, int column, int page)
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ROW_ADDR_SHIFT, page);
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}
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static inline void vf610_nfc_ecc_mode(struct vf610_nfc *nfc, int ecc_mode)
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{
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vf610_nfc_set_field(nfc, NFC_FLASH_CONFIG,
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CONFIG_ECC_MODE_MASK,
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CONFIG_ECC_MODE_SHIFT, ecc_mode);
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}
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static inline void vf610_nfc_transfer_size(struct vf610_nfc *nfc, int size)
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{
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vf610_nfc_write(nfc, NFC_SECTOR_SIZE, size);
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@ -315,6 +366,8 @@ static void vf610_nfc_command(struct mtd_info *mtd, unsigned command,
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case NAND_CMD_SEQIN:
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/* Use valid column/page from preread... */
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vf610_nfc_addr_cycle(nfc, column, page);
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nfc->buf_offset = 0;
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/*
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* SEQIN => data => PAGEPROG sequence is done by the controller
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* hence we do not need to issue the command here...
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@ -325,6 +378,10 @@ static void vf610_nfc_command(struct mtd_info *mtd, unsigned command,
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vf610_nfc_transfer_size(nfc, trfr_sz);
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vf610_nfc_send_commands(nfc, NAND_CMD_SEQIN,
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command, PROGRAM_PAGE_CMD_CODE);
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if (nfc->use_hw_ecc)
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vf610_nfc_ecc_mode(nfc, nfc->ecc_mode);
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else
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vf610_nfc_ecc_mode(nfc, ECC_BYPASS);
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break;
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case NAND_CMD_RESET:
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@ -339,6 +396,7 @@ static void vf610_nfc_command(struct mtd_info *mtd, unsigned command,
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vf610_nfc_send_commands(nfc, NAND_CMD_READ0,
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NAND_CMD_READSTART, READ_PAGE_CMD_CODE);
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vf610_nfc_addr_cycle(nfc, column, page);
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vf610_nfc_ecc_mode(nfc, ECC_BYPASS);
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break;
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case NAND_CMD_READ0:
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@ -347,6 +405,7 @@ static void vf610_nfc_command(struct mtd_info *mtd, unsigned command,
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vf610_nfc_send_commands(nfc, NAND_CMD_READ0,
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NAND_CMD_READSTART, READ_PAGE_CMD_CODE);
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vf610_nfc_addr_cycle(nfc, column, page);
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vf610_nfc_ecc_mode(nfc, nfc->ecc_mode);
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break;
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case NAND_CMD_PARAM:
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@ -355,6 +414,7 @@ static void vf610_nfc_command(struct mtd_info *mtd, unsigned command,
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vf610_nfc_transfer_size(nfc, trfr_sz);
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vf610_nfc_send_command(nfc, command, READ_ONFI_PARAM_CMD_CODE);
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vf610_nfc_addr_cycle(nfc, -1, column);
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vf610_nfc_ecc_mode(nfc, ECC_BYPASS);
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break;
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case NAND_CMD_ERASE1:
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@ -383,6 +443,7 @@ static void vf610_nfc_command(struct mtd_info *mtd, unsigned command,
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vf610_nfc_done(nfc);
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nfc->use_hw_ecc = false;
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nfc->write_sz = 0;
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}
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@ -477,6 +538,94 @@ static void vf610_nfc_select_chip(struct mtd_info *mtd, int chip)
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vf610_nfc_write(nfc, NFC_ROW_ADDR, tmp);
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}
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/* Count the number of 0's in buff up to max_bits */
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static inline int count_written_bits(uint8_t *buff, int size, int max_bits)
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{
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uint32_t *buff32 = (uint32_t *)buff;
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int k, written_bits = 0;
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for (k = 0; k < (size / 4); k++) {
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written_bits += hweight32(~buff32[k]);
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if (unlikely(written_bits > max_bits))
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break;
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}
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return written_bits;
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}
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static inline int vf610_nfc_correct_data(struct mtd_info *mtd, uint8_t *dat,
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uint8_t *oob, int page)
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{
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struct vf610_nfc *nfc = mtd_to_nfc(mtd);
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u32 ecc_status_off = NFC_MAIN_AREA(0) + ECC_SRAM_ADDR + ECC_STATUS;
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u8 ecc_status;
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u8 ecc_count;
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int flips;
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int flips_threshold = nfc->chip.ecc.strength / 2;
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ecc_status = vf610_nfc_read(nfc, ecc_status_off) & 0xff;
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ecc_count = ecc_status & ECC_STATUS_ERR_COUNT;
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if (!(ecc_status & ECC_STATUS_MASK))
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return ecc_count;
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/* Read OOB without ECC unit enabled */
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vf610_nfc_command(mtd, NAND_CMD_READOOB, 0, page);
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vf610_nfc_read_buf(mtd, oob, mtd->oobsize);
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/*
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* On an erased page, bit count (including OOB) should be zero or
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* at least less then half of the ECC strength.
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*/
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flips = count_written_bits(dat, nfc->chip.ecc.size, flips_threshold);
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flips += count_written_bits(oob, mtd->oobsize, flips_threshold);
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if (unlikely(flips > flips_threshold))
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return -EINVAL;
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/* Erased page. */
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memset(dat, 0xff, nfc->chip.ecc.size);
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memset(oob, 0xff, mtd->oobsize);
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return flips;
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}
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static int vf610_nfc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
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uint8_t *buf, int oob_required, int page)
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{
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int eccsize = chip->ecc.size;
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int stat;
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vf610_nfc_read_buf(mtd, buf, eccsize);
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if (oob_required)
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vf610_nfc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
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stat = vf610_nfc_correct_data(mtd, buf, chip->oob_poi, page);
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if (stat < 0) {
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mtd->ecc_stats.failed++;
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return 0;
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} else {
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mtd->ecc_stats.corrected += stat;
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return stat;
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}
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}
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static int vf610_nfc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
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const uint8_t *buf, int oob_required)
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{
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struct vf610_nfc *nfc = mtd_to_nfc(mtd);
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vf610_nfc_write_buf(mtd, buf, mtd->writesize);
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if (oob_required)
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vf610_nfc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
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/* Always write whole page including OOB due to HW ECC */
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nfc->use_hw_ecc = true;
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nfc->write_sz = mtd->writesize + mtd->oobsize;
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return 0;
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}
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static const struct of_device_id vf610_nfc_dt_ids[] = {
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{ .compatible = "fsl,vf610-nfc", .data = (void *)NFC_VFC610 },
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{ /* sentinel */ }
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@ -503,6 +652,17 @@ static void vf610_nfc_init_controller(struct vf610_nfc *nfc)
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vf610_nfc_set(nfc, NFC_FLASH_CONFIG, CONFIG_16BIT);
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else
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vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_16BIT);
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if (nfc->chip.ecc.mode == NAND_ECC_HW) {
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/* Set ECC status offset in SRAM */
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vf610_nfc_set_field(nfc, NFC_FLASH_CONFIG,
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CONFIG_ECC_SRAM_ADDR_MASK,
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CONFIG_ECC_SRAM_ADDR_SHIFT,
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ECC_SRAM_ADDR >> 3);
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/* Enable ECC status in SRAM */
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vf610_nfc_set(nfc, NFC_FLASH_CONFIG, CONFIG_ECC_SRAM_REQ_BIT);
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}
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}
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static int vf610_nfc_probe(struct platform_device *pdev)
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@ -610,6 +770,45 @@ static int vf610_nfc_probe(struct platform_device *pdev)
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goto error;
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}
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if (chip->ecc.mode == NAND_ECC_HW) {
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if (mtd->writesize != PAGE_2K && mtd->oobsize < 64) {
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dev_err(nfc->dev, "Unsupported flash with hwecc\n");
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err = -ENXIO;
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goto error;
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}
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if (chip->ecc.size != mtd->writesize) {
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dev_err(nfc->dev, "Step size needs to be page size\n");
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err = -ENXIO;
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goto error;
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}
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/* Only 64 byte ECC layouts known */
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if (mtd->oobsize > 64)
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mtd->oobsize = 64;
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if (chip->ecc.strength == 32) {
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nfc->ecc_mode = ECC_60_BYTE;
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chip->ecc.bytes = 60;
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chip->ecc.layout = &vf610_nfc_ecc60;
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} else if (chip->ecc.strength == 24) {
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nfc->ecc_mode = ECC_45_BYTE;
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chip->ecc.bytes = 45;
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chip->ecc.layout = &vf610_nfc_ecc45;
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} else {
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dev_err(nfc->dev, "Unsupported ECC strength\n");
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err = -ENXIO;
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goto error;
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}
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/* propagate ecc.layout to mtd_info */
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mtd->ecclayout = chip->ecc.layout;
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chip->ecc.read_page = vf610_nfc_read_page;
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chip->ecc.write_page = vf610_nfc_write_page;
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chip->ecc.size = PAGE_2K;
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}
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/* second phase scan */
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if (nand_scan_tail(mtd)) {
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err = -ENXIO;
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