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drm/i915: Kill intel_dp->{link_bw, rate_select} 

We only need the link_bw/rate_select parameters when starting link
training, and they should be computed based on the currently active
config, so throw them out from intel_dp and just compute on demand.

Toss in an extra debug print to see rate_select in addition to link_bw,
as the latter may be 0 for eDP 1.4.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Ville Syrjälä 2015-07-06 15:10:06 +03:00 committed by Daniel Vetter
parent a79b8165be
commit 04a60f9ffa
3 changed files with 27 additions and 27 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

39
drivers/gpu/drm/i915/intel_dp.c
View File

@ -1376,6 +1376,19 @@ int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
return rate_to_index(rate, intel_dp->sink_rates);
}
static void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
uint8_t *link_bw, uint8_t *rate_select)
{
if (intel_dp->num_sink_rates) {
*link_bw = 0;
*rate_select =
intel_dp_rate_select(intel_dp, port_clock);
} else {
*link_bw = drm_dp_link_rate_to_bw_code(port_clock);
*rate_select = 0;
}
}
bool
intel_dp_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
@ -1397,6 +1410,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
int link_avail, link_clock;
int common_rates[DP_MAX_SUPPORTED_RATES] = {};
int common_len;
uint8_t link_bw, rate_select;
common_len = intel_dp_common_rates(intel_dp, common_rates);
@ -1501,21 +1515,14 @@ intel_dp_compute_config(struct intel_encoder *encoder,
pipe_config->lane_count = lane_count;
if (intel_dp->num_sink_rates) {
intel_dp->link_bw = 0;
intel_dp->rate_select =
intel_dp_rate_select(intel_dp, common_rates[clock]);
} else {
intel_dp->link_bw =
drm_dp_link_rate_to_bw_code(common_rates[clock]);
intel_dp->rate_select = 0;
}
pipe_config->pipe_bpp = bpp;
pipe_config->port_clock = common_rates[clock];
DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
intel_dp->link_bw, pipe_config->lane_count,
intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
&link_bw, &rate_select);
DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
link_bw, rate_select, pipe_config->lane_count,
pipe_config->port_clock, bpp);
DRM_DEBUG_KMS("DP link bw required %i available %i\n",
mode_rate, link_avail);
@ -3624,19 +3631,23 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
int voltage_tries, loop_tries;
uint32_t DP = intel_dp->DP;
uint8_t link_config[2];
uint8_t link_bw, rate_select;
if (HAS_DDI(dev))
intel_ddi_prepare_link_retrain(encoder);
intel_dp_compute_rate(intel_dp, crtc->config->port_clock,
&link_bw, &rate_select);
/* Write the link configuration data */
link_config[0] = intel_dp->link_bw;
link_config[0] = link_bw;
link_config[1] = crtc->config->lane_count;
if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
if (intel_dp->num_sink_rates)
drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
&intel_dp->rate_select, 1);
&rate_select, 1);
link_config[0] = 0;
link_config[1] = DP_SET_ANSI_8B10B;

13
drivers/gpu/drm/i915/intel_dp_mst.c
View File

@ -38,7 +38,7 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
struct intel_dp *intel_dp = &intel_dig_port->dp;
struct drm_atomic_state *state;
int bpp, i;
int lane_count, slots, rate;
int lane_count, slots;
struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
struct drm_connector *drm_connector;
struct intel_connector *connector, *found = NULL;
@ -55,20 +55,11 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
*/
lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
rate = intel_dp_max_link_rate(intel_dp);
if (intel_dp->num_sink_rates) {
intel_dp->link_bw = 0;
intel_dp->rate_select = intel_dp_rate_select(intel_dp, rate);
} else {
intel_dp->link_bw = drm_dp_link_rate_to_bw_code(rate);
intel_dp->rate_select = 0;
}
pipe_config->lane_count = lane_count;
pipe_config->pipe_bpp = 24;
pipe_config->port_clock = rate;
pipe_config->port_clock = intel_dp_max_link_rate(intel_dp);
state = pipe_config->base.state;

2
drivers/gpu/drm/i915/intel_drv.h
View File

@ -712,8 +712,6 @@ struct intel_dp {
enum hdmi_force_audio force_audio;
bool limited_color_range;
bool color_range_auto;
uint8_t link_bw;
uint8_t rate_select;
uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];