mirror of https://gitee.com/openkylin/linux.git
net: Microchip encx24j600 driver
This ethernet driver supports the Micorchip enc424j600/626j600 Ethernet controller over a SPI bus interface. This driver makes use of the regmap API to optimize access to registers by caching registers where possible. Datasheet: http://ww1.microchip.com/downloads/en/DeviceDoc/39935b.pdf Signed-off-by: Jon Ringle <jringle@gridpoint.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Jon Ringle
David S. Miller
parent
7741c373cf
commit
04fbfce7a2
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@ -33,4 +33,13 @@ config ENC28J60_WRITEVERIFY
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Enable the verify after the buffer write useful for debugging purpose.
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If unsure, say N.
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config ENCX24J600
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tristate "ENCX24J600 support"
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depends on SPI
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---help---
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Support for the Microchip ENC424J600 ethernet chip.
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To compile this driver as a module, choose M here. The module will be
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called enc424j600.
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endif # NET_VENDOR_MICROCHIP
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@ -3,3 +3,4 @@
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#
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obj-$(CONFIG_ENC28J60) += enc28j60.o
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obj-$(CONFIG_ENCX24J600) += encx24j600.o encx24j600-regmap.o
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@ -0,0 +1,551 @@
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/**
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* Register map access API - ENCX24J600 support
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*
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* Copyright 2015 Gridpoint
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*
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* Author: Jon Ringle <jringle@gridpoint.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/netdevice.h>
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#include <linux/regmap.h>
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#include <linux/spi/spi.h>
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#include "encx24j600_hw.h"
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static inline bool is_bits_set(int value, int mask)
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{
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return (value & mask) == mask;
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}
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static int encx24j600_switch_bank(struct encx24j600_context *ctx,
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int bank)
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{
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int ret = 0;
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int bank_opcode = BANK_SELECT(bank);
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ret = spi_write(ctx->spi, &bank_opcode, 1);
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if (ret == 0)
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ctx->bank = bank;
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return ret;
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}
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static int encx24j600_cmdn(struct encx24j600_context *ctx, u8 opcode,
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const void *buf, size_t len)
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{
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struct spi_message m;
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struct spi_transfer t[2] = { { .tx_buf = &opcode, .len = 1, },
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{ .tx_buf = buf, .len = len }, };
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spi_message_init(&m);
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spi_message_add_tail(&t[0], &m);
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spi_message_add_tail(&t[1], &m);
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return spi_sync(ctx->spi, &m);
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}
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static void regmap_lock_mutex(void *context)
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{
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struct encx24j600_context *ctx = context;
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mutex_lock(&ctx->mutex);
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}
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static void regmap_unlock_mutex(void *context)
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{
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struct encx24j600_context *ctx = context;
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mutex_unlock(&ctx->mutex);
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}
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static int regmap_encx24j600_sfr_read(void *context, u8 reg, u8 *val,
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size_t len)
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{
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struct encx24j600_context *ctx = context;
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u8 banked_reg = reg & ADDR_MASK;
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u8 bank = ((reg & BANK_MASK) >> BANK_SHIFT);
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u8 cmd = RCRU;
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int ret = 0;
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int i = 0;
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u8 tx_buf[2];
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if (reg < 0x80) {
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cmd = RCRCODE | banked_reg;
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if ((banked_reg < 0x16) && (ctx->bank != bank))
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ret = encx24j600_switch_bank(ctx, bank);
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if (unlikely(ret))
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return ret;
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} else {
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/* Translate registers that are more effecient using
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* 3-byte SPI commands
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*/
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switch (reg) {
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case EGPRDPT:
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cmd = RGPRDPT; break;
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case EGPWRPT:
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cmd = RGPWRPT; break;
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case ERXRDPT:
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cmd = RRXRDPT; break;
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case ERXWRPT:
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cmd = RRXWRPT; break;
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case EUDARDPT:
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cmd = RUDARDPT; break;
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case EUDAWRPT:
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cmd = RUDAWRPT; break;
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case EGPDATA:
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case ERXDATA:
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case EUDADATA:
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default:
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return -EINVAL;
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}
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}
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tx_buf[i++] = cmd;
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if (cmd == RCRU)
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tx_buf[i++] = reg;
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ret = spi_write_then_read(ctx->spi, tx_buf, i, val, len);
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return ret;
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}
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static int regmap_encx24j600_sfr_update(struct encx24j600_context *ctx,
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u8 reg, u8 *val, size_t len,
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u8 unbanked_cmd, u8 banked_code)
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{
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u8 banked_reg = reg & ADDR_MASK;
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u8 bank = ((reg & BANK_MASK) >> BANK_SHIFT);
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u8 cmd = unbanked_cmd;
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struct spi_message m;
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struct spi_transfer t[3] = { { .tx_buf = &cmd, .len = sizeof(cmd), },
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{ .tx_buf = ®, .len = sizeof(reg), },
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{ .tx_buf = val, .len = len }, };
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if (reg < 0x80) {
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int ret = 0;
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cmd = banked_code | banked_reg;
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if ((banked_reg < 0x16) && (ctx->bank != bank))
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ret = encx24j600_switch_bank(ctx, bank);
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if (unlikely(ret))
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return ret;
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} else {
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/* Translate registers that are more effecient using
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* 3-byte SPI commands
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*/
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switch (reg) {
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case EGPRDPT:
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cmd = WGPRDPT; break;
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case EGPWRPT:
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cmd = WGPWRPT; break;
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case ERXRDPT:
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cmd = WRXRDPT; break;
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case ERXWRPT:
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cmd = WRXWRPT; break;
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case EUDARDPT:
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cmd = WUDARDPT; break;
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case EUDAWRPT:
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cmd = WUDAWRPT; break;
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case EGPDATA:
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case ERXDATA:
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case EUDADATA:
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default:
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return -EINVAL;
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}
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}
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spi_message_init(&m);
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spi_message_add_tail(&t[0], &m);
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if (cmd == unbanked_cmd) {
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t[1].tx_buf = ®
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spi_message_add_tail(&t[1], &m);
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}
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spi_message_add_tail(&t[2], &m);
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return spi_sync(ctx->spi, &m);
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}
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static int regmap_encx24j600_sfr_write(void *context, u8 reg, u8 *val,
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size_t len)
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{
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struct encx24j600_context *ctx = context;
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return regmap_encx24j600_sfr_update(ctx, reg, val, len, WCRU, WCRCODE);
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}
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static int regmap_encx24j600_sfr_set_bits(struct encx24j600_context *ctx,
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u8 reg, u8 val)
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{
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return regmap_encx24j600_sfr_update(ctx, reg, &val, 1, BFSU, BFSCODE);
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}
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static int regmap_encx24j600_sfr_clr_bits(struct encx24j600_context *ctx,
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u8 reg, u8 val)
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{
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return regmap_encx24j600_sfr_update(ctx, reg, &val, 1, BFCU, BFCCODE);
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}
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static int regmap_encx24j600_reg_update_bits(void *context, unsigned int reg,
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unsigned int mask,
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unsigned int val, bool *change,
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bool force_write)
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{
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struct encx24j600_context *ctx = context;
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int ret = 0;
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unsigned int set_mask = mask & val;
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unsigned int clr_mask = mask & ~val;
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if (change)
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*change = false;
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if ((reg >= 0x40 && reg < 0x6c) || reg >= 0x80) {
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/* Must do read/modify/write cycles for
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* MAC/MII regs or Unbanked SFR regs
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*/
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u16 tmp, orig;
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ret = regmap_encx24j600_sfr_read(context, reg, (u8 *)&orig,
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sizeof(orig));
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if (ret != 0)
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return ret;
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tmp = orig & ~mask;
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tmp |= val & mask;
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if (force_write || (tmp != orig)) {
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ret = regmap_encx24j600_sfr_write(context, reg,
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(u8 *)&tmp,
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sizeof(tmp));
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if (change)
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*change = true;
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} else if (change) {
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*change = false;
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}
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return ret;
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}
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if (set_mask & 0xff) {
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ret = regmap_encx24j600_sfr_set_bits(ctx, reg, set_mask);
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if (ret == 0 && change)
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*change = true;
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}
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set_mask = (set_mask & 0xff00) >> 8;
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if ((set_mask & 0xff) && (ret == 0)) {
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ret = regmap_encx24j600_sfr_set_bits(ctx, reg + 1, set_mask);
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if (ret == 0 && change)
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*change = true;
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}
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if ((clr_mask & 0xff) && (ret == 0)) {
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ret = regmap_encx24j600_sfr_clr_bits(ctx, reg, clr_mask);
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if (ret == 0 && change)
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*change = true;
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}
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clr_mask = (clr_mask & 0xff00) >> 8;
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if ((clr_mask & 0xff) && (ret == 0)) {
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ret = regmap_encx24j600_sfr_clr_bits(ctx, reg + 1, clr_mask);
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if (ret == 0 && change)
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*change = true;
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}
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return ret;
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}
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int regmap_encx24j600_spi_write(void *context, u8 reg, const u8 *data,
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size_t count)
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{
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struct encx24j600_context *ctx = context;
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if (reg < 0xc0)
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return encx24j600_cmdn(ctx, reg, data, count);
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else
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/* SPI 1-byte command. Ignore data */
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return spi_write(ctx->spi, ®, 1);
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}
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EXPORT_SYMBOL_GPL(regmap_encx24j600_spi_write);
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int regmap_encx24j600_spi_read(void *context, u8 reg, u8 *data, size_t count)
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{
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struct encx24j600_context *ctx = context;
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if (reg == RBSEL && count > 1)
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count = 1;
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return spi_write_then_read(ctx->spi, ®, sizeof(reg), data, count);
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}
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EXPORT_SYMBOL_GPL(regmap_encx24j600_spi_read);
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static int regmap_encx24j600_write(void *context, const void *data,
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size_t len)
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{
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u8 *dout = (u8 *)data;
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u8 reg = dout[0];
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++dout;
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--len;
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if (reg > 0xa0)
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return regmap_encx24j600_spi_write(context, reg, dout, len);
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if (len > 2)
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return -EINVAL;
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return regmap_encx24j600_sfr_write(context, reg, dout, len);
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}
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static int regmap_encx24j600_read(void *context,
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const void *reg_buf, size_t reg_size,
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void *val, size_t val_size)
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{
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u8 reg = *(const u8 *)reg_buf;
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if (reg_size != 1) {
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pr_err("%s: reg=%02x reg_size=%zu\n", __func__, reg, reg_size);
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return -EINVAL;
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}
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if (reg > 0xa0)
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return regmap_encx24j600_spi_read(context, reg, val, val_size);
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if (val_size > 2) {
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pr_err("%s: reg=%02x val_size=%zu\n", __func__, reg, val_size);
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return -EINVAL;
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}
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return regmap_encx24j600_sfr_read(context, reg, val, val_size);
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}
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static bool encx24j600_regmap_readable(struct device *dev, unsigned int reg)
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{
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if ((reg < 0x36) ||
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((reg >= 0x40) && (reg < 0x4c)) ||
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((reg >= 0x52) && (reg < 0x56)) ||
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((reg >= 0x60) && (reg < 0x66)) ||
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((reg >= 0x68) && (reg < 0x80)) ||
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((reg >= 0x86) && (reg < 0x92)) ||
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(reg == 0xc8))
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return true;
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else
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return false;
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}
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static bool encx24j600_regmap_writeable(struct device *dev, unsigned int reg)
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{
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if ((reg < 0x12) ||
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((reg >= 0x14) && (reg < 0x1a)) ||
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((reg >= 0x1c) && (reg < 0x36)) ||
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((reg >= 0x40) && (reg < 0x4c)) ||
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((reg >= 0x52) && (reg < 0x56)) ||
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((reg >= 0x60) && (reg < 0x68)) ||
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((reg >= 0x6c) && (reg < 0x80)) ||
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((reg >= 0x86) && (reg < 0x92)) ||
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((reg >= 0xc0) && (reg < 0xc8)) ||
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((reg >= 0xca) && (reg < 0xf0)))
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return true;
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else
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return false;
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}
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static bool encx24j600_regmap_volatile(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case ERXHEAD:
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case EDMACS:
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case ETXSTAT:
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case ETXWIRE:
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case ECON1: /* Can be modified via single byte cmds */
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case ECON2: /* Can be modified via single byte cmds */
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case ESTAT:
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case EIR: /* Can be modified via single byte cmds */
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case MIRD:
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case MISTAT:
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return true;
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default:
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break;
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}
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return false;
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}
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static bool encx24j600_regmap_precious(struct device *dev, unsigned int reg)
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{
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/* single byte cmds are precious */
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if (((reg >= 0xc0) && (reg < 0xc8)) ||
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((reg >= 0xca) && (reg < 0xf0)))
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return true;
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else
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return false;
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}
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static int regmap_encx24j600_phy_reg_read(void *context, unsigned int reg,
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unsigned int *val)
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{
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struct encx24j600_context *ctx = context;
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int ret;
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unsigned int mistat;
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reg = MIREGADR_VAL | (reg & PHREG_MASK);
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ret = regmap_write(ctx->regmap, MIREGADR, reg);
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if (unlikely(ret))
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goto err_out;
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ret = regmap_write(ctx->regmap, MICMD, MIIRD);
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if (unlikely(ret))
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goto err_out;
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usleep_range(26, 100);
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while ((ret = regmap_read(ctx->regmap, MISTAT, &mistat) != 0) &&
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(mistat & BUSY))
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cpu_relax();
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if (unlikely(ret))
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goto err_out;
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ret = regmap_write(ctx->regmap, MICMD, 0);
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if (unlikely(ret))
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goto err_out;
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ret = regmap_read(ctx->regmap, MIRD, val);
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err_out:
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if (ret)
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pr_err("%s: error %d reading reg %02x\n", __func__, ret,
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reg & PHREG_MASK);
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return ret;
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}
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static int regmap_encx24j600_phy_reg_write(void *context, unsigned int reg,
|
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unsigned int val)
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{
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struct encx24j600_context *ctx = context;
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int ret;
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unsigned int mistat;
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reg = MIREGADR_VAL | (reg & PHREG_MASK);
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ret = regmap_write(ctx->regmap, MIREGADR, reg);
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if (unlikely(ret))
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goto err_out;
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ret = regmap_write(ctx->regmap, MIWR, val);
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if (unlikely(ret))
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goto err_out;
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usleep_range(26, 100);
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while ((ret = regmap_read(ctx->regmap, MISTAT, &mistat) != 0) &&
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(mistat & BUSY))
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cpu_relax();
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err_out:
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if (ret)
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pr_err("%s: error %d writing reg %02x=%04x\n", __func__, ret,
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reg & PHREG_MASK, val);
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return ret;
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}
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static bool encx24j600_phymap_readable(struct device *dev, unsigned int reg)
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{
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switch (reg) {
|
||||
case PHCON1:
|
||||
case PHSTAT1:
|
||||
case PHANA:
|
||||
case PHANLPA:
|
||||
case PHANE:
|
||||
case PHCON2:
|
||||
case PHSTAT2:
|
||||
case PHSTAT3:
|
||||
return true;
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
static bool encx24j600_phymap_writeable(struct device *dev, unsigned int reg)
|
||||
{
|
||||
switch (reg) {
|
||||
case PHCON1:
|
||||
case PHCON2:
|
||||
case PHANA:
|
||||
return true;
|
||||
case PHSTAT1:
|
||||
case PHSTAT2:
|
||||
case PHSTAT3:
|
||||
case PHANLPA:
|
||||
case PHANE:
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
static bool encx24j600_phymap_volatile(struct device *dev, unsigned int reg)
|
||||
{
|
||||
switch (reg) {
|
||||
case PHSTAT1:
|
||||
case PHSTAT2:
|
||||
case PHSTAT3:
|
||||
case PHANLPA:
|
||||
case PHANE:
|
||||
case PHCON2:
|
||||
return true;
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
static struct regmap_config regcfg = {
|
||||
.name = "reg",
|
||||
.reg_bits = 8,
|
||||
.val_bits = 16,
|
||||
.max_register = 0xee,
|
||||
.reg_stride = 2,
|
||||
.cache_type = REGCACHE_RBTREE,
|
||||
.val_format_endian = REGMAP_ENDIAN_LITTLE,
|
||||
.readable_reg = encx24j600_regmap_readable,
|
||||
.writeable_reg = encx24j600_regmap_writeable,
|
||||
.volatile_reg = encx24j600_regmap_volatile,
|
||||
.precious_reg = encx24j600_regmap_precious,
|
||||
.lock = regmap_lock_mutex,
|
||||
.unlock = regmap_unlock_mutex,
|
||||
};
|
||||
|
||||
static struct regmap_bus regmap_encx24j600 = {
|
||||
.write = regmap_encx24j600_write,
|
||||
.read = regmap_encx24j600_read,
|
||||
.reg_update_bits = regmap_encx24j600_reg_update_bits,
|
||||
};
|
||||
|
||||
static struct regmap_config phycfg = {
|
||||
.name = "phy",
|
||||
.reg_bits = 8,
|
||||
.val_bits = 16,
|
||||
.max_register = 0x1f,
|
||||
.cache_type = REGCACHE_RBTREE,
|
||||
.val_format_endian = REGMAP_ENDIAN_LITTLE,
|
||||
.readable_reg = encx24j600_phymap_readable,
|
||||
.writeable_reg = encx24j600_phymap_writeable,
|
||||
.volatile_reg = encx24j600_phymap_volatile,
|
||||
};
|
||||
static struct regmap_bus phymap_encx24j600 = {
|
||||
.reg_write = regmap_encx24j600_phy_reg_write,
|
||||
.reg_read = regmap_encx24j600_phy_reg_read,
|
||||
};
|
||||
|
||||
void devm_regmap_init_encx24j600(struct device *dev,
|
||||
struct encx24j600_context *ctx)
|
||||
{
|
||||
mutex_init(&ctx->mutex);
|
||||
regcfg.lock_arg = ctx;
|
||||
ctx->regmap = devm_regmap_init(dev, ®map_encx24j600, ctx, ®cfg);
|
||||
ctx->phymap = devm_regmap_init(dev, &phymap_encx24j600, ctx, &phycfg);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(devm_regmap_init_encx24j600);
|
||||
|
||||
MODULE_LICENSE("GPL");
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,437 @@
|
|||
/**
|
||||
* encx24j600_hw.h: Register definitions
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _ENCX24J600_HW_H
|
||||
#define _ENCX24J600_HW_H
|
||||
|
||||
struct encx24j600_context {
|
||||
struct spi_device *spi;
|
||||
struct regmap *regmap;
|
||||
struct regmap *phymap;
|
||||
struct mutex mutex; /* mutex to protect access to regmap */
|
||||
int bank;
|
||||
};
|
||||
|
||||
void devm_regmap_init_encx24j600(struct device *dev,
|
||||
struct encx24j600_context *ctx);
|
||||
|
||||
/* Single-byte instructions */
|
||||
#define BANK_SELECT(bank) (0xC0 | ((bank & (BANK_MASK >> BANK_SHIFT)) << 1))
|
||||
#define B0SEL 0xC0 /* Bank 0 Select */
|
||||
#define B1SEL 0xC2 /* Bank 1 Select */
|
||||
#define B2SEL 0xC4 /* Bank 2 Select */
|
||||
#define B3SEL 0xC6 /* Bank 3 Select */
|
||||
#define SETETHRST 0xCA /* System Reset */
|
||||
#define FCDISABLE 0xE0 /* Flow Control Disable */
|
||||
#define FCSINGLE 0xE2 /* Flow Control Single */
|
||||
#define FCMULTIPLE 0xE4 /* Flow Control Multiple */
|
||||
#define FCCLEAR 0xE6 /* Flow Control Clear */
|
||||
#define SETPKTDEC 0xCC /* Decrement Packet Counter */
|
||||
#define DMASTOP 0xD2 /* DMA Stop */
|
||||
#define DMACKSUM 0xD8 /* DMA Start Checksum */
|
||||
#define DMACKSUMS 0xDA /* DMA Start Checksum with Seed */
|
||||
#define DMACOPY 0xDC /* DMA Start Copy */
|
||||
#define DMACOPYS 0xDE /* DMA Start Copy and Checksum with Seed */
|
||||
#define SETTXRTS 0xD4 /* Request Packet Transmission */
|
||||
#define ENABLERX 0xE8 /* Enable RX */
|
||||
#define DISABLERX 0xEA /* Disable RX */
|
||||
#define SETEIE 0xEC /* Enable Interrupts */
|
||||
#define CLREIE 0xEE /* Disable Interrupts */
|
||||
|
||||
/* Two byte instructions */
|
||||
#define RBSEL 0xC8 /* Read Bank Select */
|
||||
|
||||
/* Three byte instructions */
|
||||
#define WGPRDPT 0x60 /* Write EGPRDPT */
|
||||
#define RGPRDPT 0x62 /* Read EGPRDPT */
|
||||
#define WRXRDPT 0x64 /* Write ERXRDPT */
|
||||
#define RRXRDPT 0x66 /* Read ERXRDPT */
|
||||
#define WUDARDPT 0x68 /* Write EUDARDPT */
|
||||
#define RUDARDPT 0x6A /* Read EUDARDPT */
|
||||
#define WGPWRPT 0x6C /* Write EGPWRPT */
|
||||
#define RGPWRPT 0x6E /* Read EGPWRPT */
|
||||
#define WRXWRPT 0x70 /* Write ERXWRPT */
|
||||
#define RRXWRPT 0x72 /* Read ERXWRPT */
|
||||
#define WUDAWRPT 0x74 /* Write EUDAWRPT */
|
||||
#define RUDAWRPT 0x76 /* Read EUDAWRPT */
|
||||
|
||||
/* n byte instructions */
|
||||
#define RCRCODE 0x00
|
||||
#define WCRCODE 0x40
|
||||
#define BFSCODE 0x80
|
||||
#define BFCCODE 0xA0
|
||||
#define RCR(addr) (RCRCODE | (addr & ADDR_MASK)) /* Read Control Register */
|
||||
#define WCR(addr) (WCRCODE | (addr & ADDR_MASK)) /* Write Control Register */
|
||||
#define RCRU 0x20 /* Read Control Register Unbanked */
|
||||
#define WCRU 0x22 /* Write Control Register Unbanked */
|
||||
#define BFS(addr) (BFSCODE | (addr & ADDR_MASK)) /* Bit Field Set */
|
||||
#define BFC(addr) (BFCCODE | (addr & ADDR_MASK)) /* Bit Field Clear */
|
||||
#define BFSU 0x24 /* Bit Field Set Unbanked */
|
||||
#define BFCU 0x26 /* Bit Field Clear Unbanked */
|
||||
#define RGPDATA 0x28 /* Read EGPDATA */
|
||||
#define WGPDATA 0x2A /* Write EGPDATA */
|
||||
#define RRXDATA 0x2C /* Read ERXDATA */
|
||||
#define WRXDATA 0x2E /* Write ERXDATA */
|
||||
#define RUDADATA 0x30 /* Read EUDADATA */
|
||||
#define WUDADATA 0x32 /* Write EUDADATA */
|
||||
|
||||
#define SFR_REG_COUNT 0xA0
|
||||
|
||||
/* ENC424J600 Control Registers
|
||||
* Control register definitions are a combination of address
|
||||
* and bank number
|
||||
* - Register address (bits 0-4)
|
||||
* - Bank number (bits 5-6)
|
||||
*/
|
||||
#define ADDR_MASK 0x1F
|
||||
#define BANK_MASK 0x60
|
||||
#define BANK_SHIFT 5
|
||||
|
||||
/* All-bank registers */
|
||||
#define EUDAST 0x16
|
||||
#define EUDAND 0x18
|
||||
#define ESTAT 0x1A
|
||||
#define EIR 0x1C
|
||||
#define ECON1 0x1E
|
||||
|
||||
/* Bank 0 registers */
|
||||
#define ETXST (0x00 | 0x00)
|
||||
#define ETXLEN (0x02 | 0x00)
|
||||
#define ERXST (0x04 | 0x00)
|
||||
#define ERXTAIL (0x06 | 0x00)
|
||||
#define ERXHEAD (0x08 | 0x00)
|
||||
#define EDMAST (0x0A | 0x00)
|
||||
#define EDMALEN (0x0C | 0x00)
|
||||
#define EDMADST (0x0E | 0x00)
|
||||
#define EDMACS (0x10 | 0x00)
|
||||
#define ETXSTAT (0x12 | 0x00)
|
||||
#define ETXWIRE (0x14 | 0x00)
|
||||
|
||||
/* Bank 1 registers */
|
||||
#define EHT1 (0x00 | 0x20)
|
||||
#define EHT2 (0x02 | 0x20)
|
||||
#define EHT3 (0x04 | 0x20)
|
||||
#define EHT4 (0x06 | 0x20)
|
||||
#define EPMM1 (0x08 | 0x20)
|
||||
#define EPMM2 (0x0A | 0x20)
|
||||
#define EPMM3 (0x0C | 0x20)
|
||||
#define EPMM4 (0x0E | 0x20)
|
||||
#define EPMCS (0x10 | 0x20)
|
||||
#define EPMO (0x12 | 0x20)
|
||||
#define ERXFCON (0x14 | 0x20)
|
||||
|
||||
/* Bank 2 registers */
|
||||
#define MACON1 (0x00 | 0x40)
|
||||
#define MACON2 (0x02 | 0x40)
|
||||
#define MABBIPG (0x04 | 0x40)
|
||||
#define MAIPG (0x06 | 0x40)
|
||||
#define MACLCON (0x08 | 0x40)
|
||||
#define MAMXFL (0x0A | 0x40)
|
||||
#define MICMD (0x12 | 0x40)
|
||||
#define MIREGADR (0x14 | 0x40)
|
||||
|
||||
/* Bank 3 registers */
|
||||
#define MAADR3 (0x00 | 0x60)
|
||||
#define MAADR2 (0x02 | 0x60)
|
||||
#define MAADR1 (0x04 | 0x60)
|
||||
#define MIWR (0x06 | 0x60)
|
||||
#define MIRD (0x08 | 0x60)
|
||||
#define MISTAT (0x0A | 0x60)
|
||||
#define EPAUS (0x0C | 0x60)
|
||||
#define ECON2 (0x0E | 0x60)
|
||||
#define ERXWM (0x10 | 0x60)
|
||||
#define EIE (0x12 | 0x60)
|
||||
#define EIDLED (0x14 | 0x60)
|
||||
|
||||
/* Unbanked registers */
|
||||
#define EGPDATA (0x00 | 0x80)
|
||||
#define ERXDATA (0x02 | 0x80)
|
||||
#define EUDADATA (0x04 | 0x80)
|
||||
#define EGPRDPT (0x06 | 0x80)
|
||||
#define EGPWRPT (0x08 | 0x80)
|
||||
#define ERXRDPT (0x0A | 0x80)
|
||||
#define ERXWRPT (0x0C | 0x80)
|
||||
#define EUDARDPT (0x0E | 0x80)
|
||||
#define EUDAWRPT (0x10 | 0x80)
|
||||
|
||||
|
||||
/* Register bit definitions */
|
||||
/* ESTAT */
|
||||
#define INT (1 << 15)
|
||||
#define FCIDLE (1 << 14)
|
||||
#define RXBUSY (1 << 13)
|
||||
#define CLKRDY (1 << 12)
|
||||
#define PHYDPX (1 << 10)
|
||||
#define PHYLNK (1 << 8)
|
||||
|
||||
/* EIR */
|
||||
#define CRYPTEN (1 << 15)
|
||||
#define MODEXIF (1 << 14)
|
||||
#define HASHIF (1 << 13)
|
||||
#define AESIF (1 << 12)
|
||||
#define LINKIF (1 << 11)
|
||||
#define PKTIF (1 << 6)
|
||||
#define DMAIF (1 << 5)
|
||||
#define TXIF (1 << 3)
|
||||
#define TXABTIF (1 << 2)
|
||||
#define RXABTIF (1 << 1)
|
||||
#define PCFULIF (1 << 0)
|
||||
|
||||
/* ECON1 */
|
||||
#define MODEXST (1 << 15)
|
||||
#define HASHEN (1 << 14)
|
||||
#define HASHOP (1 << 13)
|
||||
#define HASHLST (1 << 12)
|
||||
#define AESST (1 << 11)
|
||||
#define AESOP1 (1 << 10)
|
||||
#define AESOP0 (1 << 9)
|
||||
#define PKTDEC (1 << 8)
|
||||
#define FCOP1 (1 << 7)
|
||||
#define FCOP0 (1 << 6)
|
||||
#define DMAST (1 << 5)
|
||||
#define DMACPY (1 << 4)
|
||||
#define DMACSSD (1 << 3)
|
||||
#define DMANOCS (1 << 2)
|
||||
#define TXRTS (1 << 1)
|
||||
#define RXEN (1 << 0)
|
||||
|
||||
/* ETXSTAT */
|
||||
#define LATECOL (1 << 10)
|
||||
#define MAXCOL (1 << 9)
|
||||
#define EXDEFER (1 << 8)
|
||||
#define ETXSTATL_DEFER (1 << 7)
|
||||
#define CRCBAD (1 << 4)
|
||||
#define COLCNT_MASK 0xF
|
||||
|
||||
/* ERXFCON */
|
||||
#define HTEN (1 << 15)
|
||||
#define MPEN (1 << 14)
|
||||
#define NOTPM (1 << 12)
|
||||
#define PMEN3 (1 << 11)
|
||||
#define PMEN2 (1 << 10)
|
||||
#define PMEN1 (1 << 9)
|
||||
#define PMEN0 (1 << 8)
|
||||
#define CRCEEN (1 << 7)
|
||||
#define CRCEN (1 << 6)
|
||||
#define RUNTEEN (1 << 5)
|
||||
#define RUNTEN (1 << 4)
|
||||
#define UCEN (1 << 3)
|
||||
#define NOTMEEN (1 << 2)
|
||||
#define MCEN (1 << 1)
|
||||
#define BCEN (1 << 0)
|
||||
|
||||
/* MACON1 */
|
||||
#define LOOPBK (1 << 4)
|
||||
#define RXPAUS (1 << 2)
|
||||
#define PASSALL (1 << 1)
|
||||
|
||||
/* MACON2 */
|
||||
#define MACON2_DEFER (1 << 14)
|
||||
#define BPEN (1 << 13)
|
||||
#define NOBKOFF (1 << 12)
|
||||
#define PADCFG2 (1 << 7)
|
||||
#define PADCFG1 (1 << 6)
|
||||
#define PADCFG0 (1 << 5)
|
||||
#define TXCRCEN (1 << 4)
|
||||
#define PHDREN (1 << 3)
|
||||
#define HFRMEN (1 << 2)
|
||||
#define MACON2_RSV1 (1 << 1)
|
||||
#define FULDPX (1 << 0)
|
||||
|
||||
/* MAIPG */
|
||||
/* value of the high byte is given by the reserved bits,
|
||||
* value of the low byte is recomended setting of the
|
||||
* IPG parameter.
|
||||
*/
|
||||
#define MAIPGH_VAL 0x0C
|
||||
#define MAIPGL_VAL 0x12
|
||||
|
||||
/* MIREGADRH */
|
||||
#define MIREGADR_VAL (1 << 8)
|
||||
|
||||
/* MIREGADRL */
|
||||
#define PHREG_MASK 0x1F
|
||||
|
||||
/* MICMD */
|
||||
#define MIISCAN (1 << 1)
|
||||
#define MIIRD (1 << 0)
|
||||
|
||||
/* MISTAT */
|
||||
#define NVALID (1 << 2)
|
||||
#define SCAN (1 << 1)
|
||||
#define BUSY (1 << 0)
|
||||
|
||||
/* ECON2 */
|
||||
#define ETHEN (1 << 15)
|
||||
#define STRCH (1 << 14)
|
||||
#define TXMAC (1 << 13)
|
||||
#define SHA1MD5 (1 << 12)
|
||||
#define COCON3 (1 << 11)
|
||||
#define COCON2 (1 << 10)
|
||||
#define COCON1 (1 << 9)
|
||||
#define COCON0 (1 << 8)
|
||||
#define AUTOFC (1 << 7)
|
||||
#define TXRST (1 << 6)
|
||||
#define RXRST (1 << 5)
|
||||
#define ETHRST (1 << 4)
|
||||
#define MODLEN1 (1 << 3)
|
||||
#define MODLEN0 (1 << 2)
|
||||
#define AESLEN1 (1 << 1)
|
||||
#define AESLEN0 (1 << 0)
|
||||
|
||||
/* EIE */
|
||||
#define INTIE (1 << 15)
|
||||
#define MODEXIE (1 << 14)
|
||||
#define HASHIE (1 << 13)
|
||||
#define AESIE (1 << 12)
|
||||
#define LINKIE (1 << 11)
|
||||
#define PKTIE (1 << 6)
|
||||
#define DMAIE (1 << 5)
|
||||
#define TXIE (1 << 3)
|
||||
#define TXABTIE (1 << 2)
|
||||
#define RXABTIE (1 << 1)
|
||||
#define PCFULIE (1 << 0)
|
||||
|
||||
/* EIDLED */
|
||||
#define LACFG3 (1 << 15)
|
||||
#define LACFG2 (1 << 14)
|
||||
#define LACFG1 (1 << 13)
|
||||
#define LACFG0 (1 << 12)
|
||||
#define LBCFG3 (1 << 11)
|
||||
#define LBCFG2 (1 << 10)
|
||||
#define LBCFG1 (1 << 9)
|
||||
#define LBCFG0 (1 << 8)
|
||||
#define DEVID_SHIFT 5
|
||||
#define DEVID_MASK (0x7 << DEVID_SHIFT)
|
||||
#define REVID_SHIFT 0
|
||||
#define REVID_MASK (0x1F << REVID_SHIFT)
|
||||
|
||||
/* PHY registers */
|
||||
#define PHCON1 0x00
|
||||
#define PHSTAT1 0x01
|
||||
#define PHANA 0x04
|
||||
#define PHANLPA 0x05
|
||||
#define PHANE 0x06
|
||||
#define PHCON2 0x11
|
||||
#define PHSTAT2 0x1B
|
||||
#define PHSTAT3 0x1F
|
||||
|
||||
/* PHCON1 */
|
||||
#define PRST (1 << 15)
|
||||
#define PLOOPBK (1 << 14)
|
||||
#define SPD100 (1 << 13)
|
||||
#define ANEN (1 << 12)
|
||||
#define PSLEEP (1 << 11)
|
||||
#define RENEG (1 << 9)
|
||||
#define PFULDPX (1 << 8)
|
||||
|
||||
/* PHSTAT1 */
|
||||
#define FULL100 (1 << 14)
|
||||
#define HALF100 (1 << 13)
|
||||
#define FULL10 (1 << 12)
|
||||
#define HALF10 (1 << 11)
|
||||
#define ANDONE (1 << 5)
|
||||
#define LRFAULT (1 << 4)
|
||||
#define ANABLE (1 << 3)
|
||||
#define LLSTAT (1 << 2)
|
||||
#define EXTREGS (1 << 0)
|
||||
|
||||
/* PHSTAT2 */
|
||||
#define PLRITY (1 << 4)
|
||||
|
||||
/* PHSTAT3 */
|
||||
#define PHY3SPD100 (1 << 3)
|
||||
#define PHY3DPX (1 << 4)
|
||||
#define SPDDPX_SHIFT 2
|
||||
#define SPDDPX_MASK (0x7 << SPDDPX_SHIFT)
|
||||
|
||||
/* PHANA */
|
||||
/* Default value for PHY initialization*/
|
||||
#define PHANA_DEFAULT 0x05E1
|
||||
|
||||
/* PHANE */
|
||||
#define PDFLT (1 << 4)
|
||||
#define LPARCD (1 << 1)
|
||||
#define LPANABL (1 << 0)
|
||||
|
||||
#define EUDAST_TEST_VAL 0x1234
|
||||
|
||||
#define TSV_SIZE 7
|
||||
|
||||
#define ENCX24J600_DEV_ID 0x1
|
||||
|
||||
/* Configuration */
|
||||
|
||||
/* Led is on when the link is present and driven low
|
||||
* temporarily when packet is TX'd or RX'd
|
||||
*/
|
||||
#define LED_A_SETTINGS 0xC
|
||||
|
||||
/* Led is on if the link is in 100 Mbps mode */
|
||||
#define LED_B_SETTINGS 0x8
|
||||
|
||||
/* maximum ethernet frame length
|
||||
* Currently not used as a limit anywhere
|
||||
* (we're using the "huge frame enable" feature of
|
||||
* enc424j600).
|
||||
*/
|
||||
#define MAX_FRAMELEN 1518
|
||||
|
||||
/* Size in bytes of the receive buffer in enc424j600.
|
||||
* Must be word aligned (even).
|
||||
*/
|
||||
#define RX_BUFFER_SIZE (15 * MAX_FRAMELEN)
|
||||
|
||||
/* Start of the general purpose area in sram */
|
||||
#define SRAM_GP_START 0x0
|
||||
|
||||
/* SRAM size */
|
||||
#define SRAM_SIZE 0x6000
|
||||
|
||||
/* Start of the receive buffer */
|
||||
#define ERXST_VAL (SRAM_SIZE - RX_BUFFER_SIZE)
|
||||
|
||||
#define RSV_RXLONGEVDROPEV 16
|
||||
#define RSV_CARRIEREV 18
|
||||
#define RSV_CRCERROR 20
|
||||
#define RSV_LENCHECKERR 21
|
||||
#define RSV_LENOUTOFRANGE 22
|
||||
#define RSV_RXOK 23
|
||||
#define RSV_RXMULTICAST 24
|
||||
#define RSV_RXBROADCAST 25
|
||||
#define RSV_DRIBBLENIBBLE 26
|
||||
#define RSV_RXCONTROLFRAME 27
|
||||
#define RSV_RXPAUSEFRAME 28
|
||||
#define RSV_RXUNKNOWNOPCODE 29
|
||||
#define RSV_RXTYPEVLAN 30
|
||||
|
||||
#define RSV_RUNTFILTERMATCH 31
|
||||
#define RSV_NOTMEFILTERMATCH 32
|
||||
#define RSV_HASHFILTERMATCH 33
|
||||
#define RSV_MAGICPKTFILTERMATCH 34
|
||||
#define RSV_PTRNMTCHFILTERMATCH 35
|
||||
#define RSV_UNICASTFILTERMATCH 36
|
||||
|
||||
#define RSV_SIZE 8
|
||||
#define RSV_BITMASK(x) (1 << ((x) - 16))
|
||||
#define RSV_GETBIT(x, y) (((x) & RSV_BITMASK(y)) ? 1 : 0)
|
||||
|
||||
struct rsv {
|
||||
u16 next_packet;
|
||||
u16 len;
|
||||
u32 rxstat;
|
||||
};
|
||||
|
||||
/* Put RX buffer at 0 as suggested by the Errata datasheet */
|
||||
|
||||
#define RXSTART_INIT ERXST_VAL
|
||||
#define RXEND_INIT 0x5FFF
|
||||
|
||||
int regmap_encx24j600_spi_write(void *context, u8 reg, const u8 *data,
|
||||
size_t count);
|
||||
int regmap_encx24j600_spi_read(void *context, u8 reg, u8 *data, size_t count);
|
||||
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue