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habanalabs: update firmware files 

Update various firmware header files with new defines.

Signed-off-by: Oded Gabbay <ogabbay@kernel.org>
This commit is contained in:
Oded Gabbay 2020-11-20 21:39:09 +02:00
parent 293744d92c
commit 051504d9f6
3 changed files with 21 additions and 2 deletions
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17
drivers/misc/habanalabs/include/common/hl_boot_if.h
View File

@ -56,6 +56,20 @@
* CPU_BOOT_ERR0_EFUSE_FAIL Reading from eFuse failed. * CPU_BOOT_ERR0_EFUSE_FAIL Reading from eFuse failed.
* The PCI device ID might be wrong. * The PCI device ID might be wrong.
* *
* CPU_BOOT_ERR0_PRI_IMG_VER_FAIL Verification of primary image failed.
* It mean that ppboot checksum
* verification for the preboot primary
* image has failed to match expected
* checksum. Trying to program image again
* might solve this.
*
* CPU_BOOT_ERR0_SEC_IMG_VER_FAIL Verification of secondary image failed.
* It mean that ppboot checksum
* verification for the preboot secondary
* image has failed to match expected
* checksum. Trying to program image again
* might solve this.
*
* CPU_BOOT_ERR0_ENABLED Error registers enabled. * CPU_BOOT_ERR0_ENABLED Error registers enabled.
* This is a main indication that the * This is a main indication that the
* running FW populates the error * running FW populates the error
@ -72,6 +86,8 @@
#define CPU_BOOT_ERR0_SECURITY_NOT_RDY (1 << 7) #define CPU_BOOT_ERR0_SECURITY_NOT_RDY (1 << 7)
#define CPU_BOOT_ERR0_SECURITY_FAIL (1 << 8) #define CPU_BOOT_ERR0_SECURITY_FAIL (1 << 8)
#define CPU_BOOT_ERR0_EFUSE_FAIL (1 << 9) #define CPU_BOOT_ERR0_EFUSE_FAIL (1 << 9)
#define CPU_BOOT_ERR0_PRI_IMG_VER_FAIL (1 << 10)
#define CPU_BOOT_ERR0_SEC_IMG_VER_FAIL (1 << 11)
#define CPU_BOOT_ERR0_ENABLED (1 << 31) #define CPU_BOOT_ERR0_ENABLED (1 << 31)
/* /*
@ -141,6 +157,7 @@
* bits are not garbage, but actual * bits are not garbage, but actual
* statuses. * statuses.
* Initialized in: preboot * Initialized in: preboot
*
*/ */
#define CPU_BOOT_DEV_STS0_SECURITY_EN (1 << 0) #define CPU_BOOT_DEV_STS0_SECURITY_EN (1 << 0)
#define CPU_BOOT_DEV_STS0_DEBUG_EN (1 << 1) #define CPU_BOOT_DEV_STS0_DEBUG_EN (1 << 1)

3
drivers/misc/habanalabs/include/gaudi/gaudi_fw_if.h
View File

@ -30,7 +30,8 @@ enum gaudi_pll_index {
MESH_PLL, MESH_PLL,
MME_PLL, MME_PLL,
TPC_PLL, TPC_PLL,
IF_PLL IF_PLL,
PLL_MAX
}; };
enum gaudi_nic_axi_error { enum gaudi_nic_axi_error {

3
drivers/misc/habanalabs/include/goya/goya_fw_if.h
View File

@ -22,7 +22,8 @@ enum goya_pll_index {
MME_PLL, MME_PLL,
PCI_PLL, PCI_PLL,
EMMC_PLL, EMMC_PLL,
TPC_PLL TPC_PLL,
PLL_MAX
}; };
#define GOYA_PLL_FREQ_LOW 50000000 /* 50 MHz */ #define GOYA_PLL_FREQ_LOW 50000000 /* 50 MHz */