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[IA64] Fix ISA IRQ trigger model and polarity setting 

When handling Interrupt Source Override in MADT table, the default
ISA IRQ trigger model and polarity should be edge-rising.
Current IA64 implmentation doesn't follow the specification and
set default ISA IRQ trigger model as level-low. With that wrong
configuration and when system runs out of interrupt vectors,
it will cause vector sharing among edge triggered ISA IRQ and
level triggered PCI IRQ, then interrupt storm. So change the code
to follow the specification.

Signed-off-by: Liu Jiang <jiang.liu@huawei.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
This commit is contained in:
Liu Jiang 2012-03-13 22:07:09 +08:00 committed by Tony Luck
parent 15839b4774
commit 0577bb661e
1 changed files with 4 additions and 4 deletions
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8
arch/ia64/kernel/acpi.c
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@ -349,11 +349,11 @@ acpi_parse_int_src_ovr(struct acpi_subtable_header * header,
iosapic_override_isa_irq(p->source_irq, p->global_irq,
((p->inti_flags & ACPI_MADT_POLARITY_MASK) ==
ACPI_MADT_POLARITY_ACTIVE_HIGH) ?
IOSAPIC_POL_HIGH : IOSAPIC_POL_LOW,
ACPI_MADT_POLARITY_ACTIVE_LOW) ?
IOSAPIC_POL_LOW : IOSAPIC_POL_HIGH,
((p->inti_flags & ACPI_MADT_TRIGGER_MASK) ==
ACPI_MADT_TRIGGER_EDGE) ?
IOSAPIC_EDGE : IOSAPIC_LEVEL);
ACPI_MADT_TRIGGER_LEVEL) ?
IOSAPIC_LEVEL : IOSAPIC_EDGE);
return 0;
}