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drm/amdgpu/gmc10: add navi14 support 

same as navi10

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Xiaojie Yuan 2018-12-17 18:19:42 +08:00 committed by Alex Deucher
parent c8ff09bf41
commit 05d72b8d36
1 changed files with 4 additions and 1 deletions
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5
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
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@ -524,6 +524,7 @@ static int gmc_v10_0_mc_init(struct amdgpu_device *adev)
if (amdgpu_gart_size == -1) {
switch (adev->asic_type) {
case CHIP_NAVI10:
case CHIP_NAVI14:
default:
adev->gmc.gart_size = 512ULL << 20;
break;
@ -601,9 +602,10 @@ static int gmc_v10_0_sw_init(void *handle)
adev->gmc.vram_type = amdgpu_atomfirmware_get_vram_type(adev);
switch (adev->asic_type) {
case CHIP_NAVI10:
case CHIP_NAVI14:
/*
* To fulfill 4-level page support,
* vm size is 256TB (48bit), maximum size of Navi10,
* vm size is 256TB (48bit), maximum size of Navi10/Navi14,
* block size 512 (9bit)
*/
amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
@ -717,6 +719,7 @@ static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev)
{
switch (adev->asic_type) {
case CHIP_NAVI10:
case CHIP_NAVI14:
break;
default:
break;