mirror of https://gitee.com/openkylin/linux.git
A new clock-type for the 1-2 muxes per soc that are for whatever reason
controlled through the General Register Files, support for the rk3328 clock-controller (including a new pll-type) and the usual clock ids and some fixes. -----BEGIN PGP SIGNATURE----- iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAlh+vFMQHGhlaWtvQHNu dGVjaC5kZQAKCRDzpnnJnNEdgf7TCACncJmYlvYp+aZEgBlEcyCTulHNSyRZHVPd c4zBsgZmgxqmgrxe8YsW6DcfPP96MtL/C/fIupxTphxxfAS5HQx2KCeVpOrfffk7 lJ1CPyCP5GdjaZ98hKVuMpKVkQu1u26DTNWSy62hbSQQndbpP0NbGsIJJUFia1vm JX0POVYt0xSo6GnbVRcKN/5b9k0HJNG9aejL8u/uA3+yr8diiKzYrtnaFzai5kvE 3LgXIDGPUZVfwZ2vrJfDCYqNlij/tF2yLIhEDDoMSl00WolJfmnMKOg1Lt0DzuMz OQY6ZIexTV1CCV+9BjXMVCLth7DH7K3EztQsvyJtr90wrfYs+4Vd =4WOJ -----END PGP SIGNATURE----- Merge tag 'v4.11-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Pull Rockchip clk updates from Heiko Stuebner: A new clock-type for the 1-2 muxes per soc that are for whatever reason controlled through the General Register Files, support for the rk3328 clock-controller (including a new pll-type) and the usual clock ids and some fixes. * tag 'v4.11-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: dt-bindings: clk: add rockchip,grf property for RK3399 clk: rockchip: use clock ids for memory controller parts on rk3066/rk3188 clk: rockchip: use rk3288 isp_in clock ids clk: rockchip: add clock ids for memory controller parts on rk3066/rk3188 clk: rockchip: add rk3288 isp_in clock ids clk: rockchip: Remove useless init of "grf" to -EPROBE_DEFER clk: rockchip: add clock controller for rk3328 dt-bindings: add bindings for rk3328 clock controller clk: rockchip: add dt-binding header for rk3328 clk: rockchip: add new pll-type for rk3328 clk: rockchip: describe aclk_vcodec using the new muxgrf type on rk3288 clk: rockchip: add a clock-type for muxes based in the grf
This commit is contained in:
Stephen Boyd
commit
060982670b
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@ -0,0 +1,57 @@
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* Rockchip RK3328 Clock and Reset Unit
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The RK3328 clock controller generates and supplies clock to various
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controllers within the SoC and also implements a reset controller for SoC
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peripherals.
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Required Properties:
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- compatible: should be "rockchip,rk3328-cru"
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- reg: physical base address of the controller and length of memory mapped
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region.
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- #clock-cells: should be 1.
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- #reset-cells: should be 1.
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Optional Properties:
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- rockchip,grf: phandle to the syscon managing the "general register files"
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If missing pll rates are not changeable, due to the missing pll lock status.
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Each clock is assigned an identifier and client nodes can use this identifier
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to specify the clock which they consume. All available clocks are defined as
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preprocessor macros in the dt-bindings/clock/rk3328-cru.h headers and can be
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used in device tree sources. Similar macros exist for the reset sources in
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these files.
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External clocks:
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There are several clocks that are generated outside the SoC. It is expected
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that they are defined using standard clock bindings with following
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clock-output-names:
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- "xin24m" - crystal input - required,
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- "clkin_i2s" - external I2S clock - optional,
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- "gmac_clkin" - external GMAC clock - optional
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- "phy_50m_out" - output clock of the pll in the mac phy
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Example: Clock controller node:
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cru: clock-controller@ff440000 {
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compatible = "rockchip,rk3328-cru";
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reg = <0x0 0xff440000 0x0 0x1000>;
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rockchip,grf = <&grf>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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Example: UART controller node that consumes the clock generated by the clock
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controller:
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uart0: serial@ff120000 {
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compatible = "snps,dw-apb-uart";
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reg = <0xff120000 0x100>;
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interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&cru SCLK_UART0>;
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};
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@ -13,6 +13,12 @@ Required Properties:
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- #clock-cells: should be 1.
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- #reset-cells: should be 1.
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Optional Properties:
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- rockchip,grf: phandle to the syscon managing the "general register files".
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It is used for GRF muxes, if missing any muxes present in the GRF will not
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be available.
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Each clock is assigned an identifier and client nodes can use this identifier
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to specify the clock which they consume. All available clocks are defined as
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preprocessor macros in the dt-bindings/clock/rk3399-cru.h headers and can be
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@ -8,6 +8,7 @@ obj-y += clk-pll.o
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obj-y += clk-cpu.o
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obj-y += clk-inverter.o
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obj-y += clk-mmc-phase.o
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obj-y += clk-muxgrf.o
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obj-y += clk-ddr.o
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obj-$(CONFIG_RESET_CONTROLLER) += softrst.o
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@ -16,5 +17,6 @@ obj-y += clk-rk3036.o
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obj-y += clk-rk3188.o
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obj-y += clk-rk3228.o
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obj-y += clk-rk3288.o
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obj-y += clk-rk3328.o
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obj-y += clk-rk3368.o
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obj-y += clk-rk3399.o
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@ -0,0 +1,102 @@
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/*
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/slab.h>
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#include <linux/bitops.h>
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#include <linux/regmap.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include "clk.h"
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struct rockchip_muxgrf_clock {
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struct clk_hw hw;
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struct regmap *regmap;
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u32 reg;
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u32 shift;
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u32 width;
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int flags;
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};
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#define to_muxgrf_clock(_hw) container_of(_hw, struct rockchip_muxgrf_clock, hw)
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static u8 rockchip_muxgrf_get_parent(struct clk_hw *hw)
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{
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struct rockchip_muxgrf_clock *mux = to_muxgrf_clock(hw);
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unsigned int mask = GENMASK(mux->width - 1, 0);
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unsigned int val;
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regmap_read(mux->regmap, mux->reg, &val);
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val >>= mux->shift;
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val &= mask;
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return val;
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}
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static int rockchip_muxgrf_set_parent(struct clk_hw *hw, u8 index)
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{
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struct rockchip_muxgrf_clock *mux = to_muxgrf_clock(hw);
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unsigned int mask = GENMASK(mux->width + mux->shift - 1, mux->shift);
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unsigned int val;
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val = index;
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val <<= mux->shift;
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if (mux->flags & CLK_MUX_HIWORD_MASK)
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return regmap_write(mux->regmap, mux->reg, val | (mask << 16));
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else
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return regmap_update_bits(mux->regmap, mux->reg, mask, val);
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}
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static const struct clk_ops rockchip_muxgrf_clk_ops = {
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.get_parent = rockchip_muxgrf_get_parent,
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.set_parent = rockchip_muxgrf_set_parent,
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.determine_rate = __clk_mux_determine_rate,
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};
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struct clk *rockchip_clk_register_muxgrf(const char *name,
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const char *const *parent_names, u8 num_parents,
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int flags, struct regmap *regmap, int reg,
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int shift, int width, int mux_flags)
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{
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struct rockchip_muxgrf_clock *muxgrf_clock;
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struct clk_init_data init;
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struct clk *clk;
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if (IS_ERR(regmap)) {
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pr_err("%s: regmap not available\n", __func__);
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return ERR_PTR(-ENOTSUPP);
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}
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muxgrf_clock = kmalloc(sizeof(*muxgrf_clock), GFP_KERNEL);
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if (!muxgrf_clock)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.flags = flags;
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init.num_parents = num_parents;
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init.parent_names = parent_names;
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init.ops = &rockchip_muxgrf_clk_ops;
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muxgrf_clock->hw.init = &init;
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muxgrf_clock->regmap = regmap;
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muxgrf_clock->reg = reg;
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muxgrf_clock->shift = shift;
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muxgrf_clock->width = width;
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muxgrf_clock->flags = mux_flags;
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clk = clk_register(NULL, &muxgrf_clock->hw);
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if (IS_ERR(clk))
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kfree(muxgrf_clock);
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return clk;
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}
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@ -29,6 +29,7 @@
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#define PLL_MODE_SLOW 0x0
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#define PLL_MODE_NORM 0x1
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#define PLL_MODE_DEEP 0x2
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#define PLL_RK3328_MODE_MASK 0x1
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struct rockchip_clk_pll {
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struct clk_hw hw;
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@ -848,7 +849,8 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
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struct clk *pll_clk, *mux_clk;
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char pll_name[20];
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if (num_parents != 2) {
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if ((pll_type != pll_rk3328 && num_parents != 2) ||
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(pll_type == pll_rk3328 && num_parents != 1)) {
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pr_err("%s: needs two parent clocks\n", __func__);
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return ERR_PTR(-EINVAL);
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}
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@ -865,13 +867,17 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
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pll_mux = &pll->pll_mux;
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pll_mux->reg = ctx->reg_base + mode_offset;
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pll_mux->shift = mode_shift;
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pll_mux->mask = PLL_MODE_MASK;
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if (pll_type == pll_rk3328)
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pll_mux->mask = PLL_RK3328_MODE_MASK;
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else
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pll_mux->mask = PLL_MODE_MASK;
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pll_mux->flags = 0;
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pll_mux->lock = &ctx->lock;
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pll_mux->hw.init = &init;
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if (pll_type == pll_rk3036 ||
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pll_type == pll_rk3066 ||
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pll_type == pll_rk3328 ||
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pll_type == pll_rk3399)
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pll_mux->flags |= CLK_MUX_HIWORD_MASK;
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@ -884,7 +890,10 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
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init.flags = CLK_SET_RATE_PARENT;
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init.ops = pll->pll_mux_ops;
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init.parent_names = pll_parents;
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init.num_parents = ARRAY_SIZE(pll_parents);
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if (pll_type == pll_rk3328)
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init.num_parents = 2;
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else
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init.num_parents = ARRAY_SIZE(pll_parents);
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mux_clk = clk_register(NULL, &pll_mux->hw);
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if (IS_ERR(mux_clk))
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@ -918,6 +927,7 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
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switch (pll_type) {
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case pll_rk3036:
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case pll_rk3328:
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if (!pll->rate_table || IS_ERR(ctx->grf))
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init.ops = &rockchip_rk3036_pll_clk_norate_ops;
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else
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@ -507,8 +507,8 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
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GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS),
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GATE(PCLK_EFUSE, "pclk_efuse", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 2, GFLAGS),
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GATE(PCLK_TZPC, "pclk_tzpc", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 3, GFLAGS),
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GATE(0, "pclk_ddrupctl", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 7, GFLAGS),
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GATE(0, "pclk_ddrpubl", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS),
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GATE(PCLK_DDRUPCTL, "pclk_ddrupctl", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 7, GFLAGS),
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GATE(PCLK_PUBL, "pclk_ddrpubl", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS),
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GATE(0, "pclk_dbg", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 1, GFLAGS),
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GATE(PCLK_GRF, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 4, GFLAGS),
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GATE(PCLK_PMU, "pclk_pmu", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 5, GFLAGS),
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@ -198,6 +198,7 @@ PNAME(mux_hsadcout_p) = { "hsadc_src", "ext_hsadc" };
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PNAME(mux_edp_24m_p) = { "ext_edp_24m", "xin24m" };
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PNAME(mux_tspout_p) = { "cpll", "gpll", "npll", "xin27m" };
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PNAME(mux_aclk_vcodec_pre_p) = { "aclk_vepu", "aclk_vdpu" };
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PNAME(mux_usbphy480m_p) = { "sclk_otgphy1_480m", "sclk_otgphy2_480m",
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"sclk_otgphy0_480m" };
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PNAME(mux_hsicphy480m_p) = { "cpll", "gpll", "usbphy480m_src" };
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@ -398,14 +399,12 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
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COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_usb480m_p, 0,
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RK3288_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS,
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RK3288_CLKGATE_CON(3), 11, GFLAGS),
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/*
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* We use aclk_vdpu by default GRF_SOC_CON0[7] setting in system,
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* so we ignore the mux and make clocks nodes as following,
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*/
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GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vdpu", 0,
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MUXGRF(0, "aclk_vcodec_pre", mux_aclk_vcodec_pre_p, 0,
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RK3288_GRF_SOC_CON(0), 7, 1, MFLAGS),
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GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vcodec_pre", 0,
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RK3288_CLKGATE_CON(9), 0, GFLAGS),
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FACTOR_GATE(0, "hclk_vcodec_pre", "aclk_vdpu", 0, 1, 4,
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FACTOR_GATE(0, "hclk_vcodec_pre", "aclk_vcodec_pre", 0, 1, 4,
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RK3288_CLKGATE_CON(3), 10, GFLAGS),
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GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0,
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|
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@ -801,7 +800,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
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|||
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GATE(0, "pclk_vip_in", "ext_vip", 0, RK3288_CLKGATE_CON(16), 0, GFLAGS),
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INVERTER(0, "pclk_vip", "pclk_vip_in", RK3288_CLKSEL_CON(29), 4, IFLAGS),
|
||||
GATE(0, "pclk_isp_in", "ext_isp", 0, RK3288_CLKGATE_CON(16), 3, GFLAGS),
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GATE(PCLK_ISP_IN, "pclk_isp_in", "ext_isp", 0, RK3288_CLKGATE_CON(16), 3, GFLAGS),
|
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INVERTER(0, "pclk_isp", "pclk_isp_in", RK3288_CLKSEL_CON(29), 3, IFLAGS),
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,895 @@
|
|||
/*
|
||||
* Copyright (c) 2016 Rockchip Electronics Co. Ltd.
|
||||
* Author: Elaine <zhangqing@rock-chips.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/syscore_ops.h>
|
||||
#include <dt-bindings/clock/rk3328-cru.h>
|
||||
#include "clk.h"
|
||||
|
||||
#define RK3328_GRF_SOC_STATUS0 0x480
|
||||
#define RK3328_GRF_MAC_CON1 0x904
|
||||
#define RK3328_GRF_MAC_CON2 0x908
|
||||
|
||||
enum rk3328_plls {
|
||||
apll, dpll, cpll, gpll, npll,
|
||||
};
|
||||
|
||||
static struct rockchip_pll_rate_table rk3328_pll_rates[] = {
|
||||
/* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
|
||||
RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
|
||||
RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
|
||||
RK3036_PLL_RATE(984000000, 1, 82, 2, 1, 1, 0),
|
||||
RK3036_PLL_RATE(960000000, 1, 80, 2, 1, 1, 0),
|
||||
RK3036_PLL_RATE(936000000, 1, 78, 2, 1, 1, 0),
|
||||
RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
|
||||
RK3036_PLL_RATE(900000000, 4, 300, 2, 1, 1, 0),
|
||||
RK3036_PLL_RATE(888000000, 1, 74, 2, 1, 1, 0),
|
||||
RK3036_PLL_RATE(864000000, 1, 72, 2, 1, 1, 0),
|
||||
RK3036_PLL_RATE(840000000, 1, 70, 2, 1, 1, 0),
|
||||
RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
|
||||
RK3036_PLL_RATE(800000000, 6, 400, 2, 1, 1, 0),
|
||||
RK3036_PLL_RATE(700000000, 6, 350, 2, 1, 1, 0),
|
||||
RK3036_PLL_RATE(696000000, 1, 58, 2, 1, 1, 0),
|
||||
RK3036_PLL_RATE(600000000, 1, 75, 3, 1, 1, 0),
|
||||
RK3036_PLL_RATE(594000000, 2, 99, 2, 1, 1, 0),
|
||||
RK3036_PLL_RATE(504000000, 1, 63, 3, 1, 1, 0),
|
||||
RK3036_PLL_RATE(500000000, 6, 250, 2, 1, 1, 0),
|
||||
RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
|
||||
RK3036_PLL_RATE(312000000, 1, 52, 2, 2, 1, 0),
|
||||
RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
|
||||
RK3036_PLL_RATE(96000000, 1, 64, 4, 4, 1, 0),
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static struct rockchip_pll_rate_table rk3328_pll_frac_rates[] = {
|
||||
/* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
|
||||
RK3036_PLL_RATE(1016064000, 3, 127, 1, 1, 0, 134217),
|
||||
/* vco = 1016064000 */
|
||||
RK3036_PLL_RATE(983040000, 24, 983, 1, 1, 0, 671088),
|
||||
/* vco = 983040000 */
|
||||
RK3036_PLL_RATE(491520000, 24, 983, 2, 1, 0, 671088),
|
||||
/* vco = 983040000 */
|
||||
RK3036_PLL_RATE(61440000, 6, 215, 7, 2, 0, 671088),
|
||||
/* vco = 860156000 */
|
||||
RK3036_PLL_RATE(56448000, 12, 451, 4, 4, 0, 9797894),
|
||||
/* vco = 903168000 */
|
||||
RK3036_PLL_RATE(40960000, 12, 409, 4, 5, 0, 10066329),
|
||||
/* vco = 819200000 */
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
#define RK3328_DIV_ACLKM_MASK 0x7
|
||||
#define RK3328_DIV_ACLKM_SHIFT 4
|
||||
#define RK3328_DIV_PCLK_DBG_MASK 0xf
|
||||
#define RK3328_DIV_PCLK_DBG_SHIFT 0
|
||||
|
||||
#define RK3328_CLKSEL1(_aclk_core, _pclk_dbg) \
|
||||
{ \
|
||||
.reg = RK3328_CLKSEL_CON(1), \
|
||||
.val = HIWORD_UPDATE(_aclk_core, RK3328_DIV_ACLKM_MASK, \
|
||||
RK3328_DIV_ACLKM_SHIFT) | \
|
||||
HIWORD_UPDATE(_pclk_dbg, RK3328_DIV_PCLK_DBG_MASK, \
|
||||
RK3328_DIV_PCLK_DBG_SHIFT), \
|
||||
}
|
||||
|
||||
#define RK3328_CPUCLK_RATE(_prate, _aclk_core, _pclk_dbg) \
|
||||
{ \
|
||||
.prate = _prate, \
|
||||
.divs = { \
|
||||
RK3328_CLKSEL1(_aclk_core, _pclk_dbg), \
|
||||
}, \
|
||||
}
|
||||
|
||||
static struct rockchip_cpuclk_rate_table rk3328_cpuclk_rates[] __initdata = {
|
||||
RK3328_CPUCLK_RATE(1800000000, 1, 7),
|
||||
RK3328_CPUCLK_RATE(1704000000, 1, 7),
|
||||
RK3328_CPUCLK_RATE(1608000000, 1, 7),
|
||||
RK3328_CPUCLK_RATE(1512000000, 1, 7),
|
||||
RK3328_CPUCLK_RATE(1488000000, 1, 5),
|
||||
RK3328_CPUCLK_RATE(1416000000, 1, 5),
|
||||
RK3328_CPUCLK_RATE(1392000000, 1, 5),
|
||||
RK3328_CPUCLK_RATE(1296000000, 1, 5),
|
||||
RK3328_CPUCLK_RATE(1200000000, 1, 5),
|
||||
RK3328_CPUCLK_RATE(1104000000, 1, 5),
|
||||
RK3328_CPUCLK_RATE(1008000000, 1, 5),
|
||||
RK3328_CPUCLK_RATE(912000000, 1, 5),
|
||||
RK3328_CPUCLK_RATE(816000000, 1, 3),
|
||||
RK3328_CPUCLK_RATE(696000000, 1, 3),
|
||||
RK3328_CPUCLK_RATE(600000000, 1, 3),
|
||||
RK3328_CPUCLK_RATE(408000000, 1, 1),
|
||||
RK3328_CPUCLK_RATE(312000000, 1, 1),
|
||||
RK3328_CPUCLK_RATE(216000000, 1, 1),
|
||||
RK3328_CPUCLK_RATE(96000000, 1, 1),
|
||||
};
|
||||
|
||||
static const struct rockchip_cpuclk_reg_data rk3328_cpuclk_data = {
|
||||
.core_reg = RK3328_CLKSEL_CON(0),
|
||||
.div_core_shift = 0,
|
||||
.div_core_mask = 0x1f,
|
||||
.mux_core_alt = 1,
|
||||
.mux_core_main = 3,
|
||||
.mux_core_shift = 6,
|
||||
.mux_core_mask = 0x3,
|
||||
};
|
||||
|
||||
PNAME(mux_pll_p) = { "xin24m" };
|
||||
|
||||
PNAME(mux_2plls_p) = { "cpll", "gpll" };
|
||||
PNAME(mux_gpll_cpll_p) = { "gpll", "cpll" };
|
||||
PNAME(mux_cpll_gpll_apll_p) = { "cpll", "gpll", "apll" };
|
||||
PNAME(mux_2plls_xin24m_p) = { "cpll", "gpll", "xin24m" };
|
||||
PNAME(mux_2plls_hdmiphy_p) = { "cpll", "gpll",
|
||||
"dummy_hdmiphy" };
|
||||
PNAME(mux_4plls_p) = { "cpll", "gpll",
|
||||
"dummy_hdmiphy",
|
||||
"usb480m" };
|
||||
PNAME(mux_2plls_u480m_p) = { "cpll", "gpll",
|
||||
"usb480m" };
|
||||
PNAME(mux_2plls_24m_u480m_p) = { "cpll", "gpll",
|
||||
"xin24m", "usb480m" };
|
||||
|
||||
PNAME(mux_ddrphy_p) = { "dpll", "apll", "cpll" };
|
||||
PNAME(mux_armclk_p) = { "apll_core",
|
||||
"gpll_core",
|
||||
"dpll_core",
|
||||
"npll_core"};
|
||||
PNAME(mux_hdmiphy_p) = { "hdmi_phy", "xin24m" };
|
||||
PNAME(mux_usb480m_p) = { "usb480m_phy",
|
||||
"xin24m" };
|
||||
|
||||
PNAME(mux_i2s0_p) = { "clk_i2s0_div",
|
||||
"clk_i2s0_frac",
|
||||
"xin12m",
|
||||
"xin12m" };
|
||||
PNAME(mux_i2s1_p) = { "clk_i2s1_div",
|
||||
"clk_i2s1_frac",
|
||||
"clkin_i2s1",
|
||||
"xin12m" };
|
||||
PNAME(mux_i2s2_p) = { "clk_i2s2_div",
|
||||
"clk_i2s2_frac",
|
||||
"clkin_i2s2",
|
||||
"xin12m" };
|
||||
PNAME(mux_i2s1out_p) = { "clk_i2s1", "xin12m"};
|
||||
PNAME(mux_i2s2out_p) = { "clk_i2s2", "xin12m" };
|
||||
PNAME(mux_spdif_p) = { "clk_spdif_div",
|
||||
"clk_spdif_frac",
|
||||
"xin12m",
|
||||
"xin12m" };
|
||||
PNAME(mux_uart0_p) = { "clk_uart0_div",
|
||||
"clk_uart0_frac",
|
||||
"xin24m" };
|
||||
PNAME(mux_uart1_p) = { "clk_uart1_div",
|
||||
"clk_uart1_frac",
|
||||
"xin24m" };
|
||||
PNAME(mux_uart2_p) = { "clk_uart2_div",
|
||||
"clk_uart2_frac",
|
||||
"xin24m" };
|
||||
|
||||
PNAME(mux_sclk_cif_p) = { "clk_cif_src",
|
||||
"xin24m" };
|
||||
PNAME(mux_dclk_lcdc_p) = { "hdmiphy",
|
||||
"dclk_lcdc_src" };
|
||||
PNAME(mux_aclk_peri_pre_p) = { "cpll_peri",
|
||||
"gpll_peri",
|
||||
"hdmiphy_peri" };
|
||||
PNAME(mux_ref_usb3otg_src_p) = { "xin24m",
|
||||
"clk_usb3otg_ref" };
|
||||
PNAME(mux_xin24m_32k_p) = { "xin24m",
|
||||
"clk_rtc32k" };
|
||||
PNAME(mux_mac2io_src_p) = { "clk_mac2io_src",
|
||||
"gmac_clkin" };
|
||||
PNAME(mux_mac2phy_src_p) = { "clk_mac2phy_src",
|
||||
"phy_50m_out" };
|
||||
|
||||
static struct rockchip_pll_clock rk3328_pll_clks[] __initdata = {
|
||||
[apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
|
||||
0, RK3328_PLL_CON(0),
|
||||
RK3328_MODE_CON, 0, 4, 0, rk3328_pll_frac_rates),
|
||||
[dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,
|
||||
0, RK3328_PLL_CON(8),
|
||||
RK3328_MODE_CON, 4, 3, 0, NULL),
|
||||
[cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
|
||||
0, RK3328_PLL_CON(16),
|
||||
RK3328_MODE_CON, 8, 2, 0, rk3328_pll_rates),
|
||||
[gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p,
|
||||
0, RK3328_PLL_CON(24),
|
||||
RK3328_MODE_CON, 12, 1, 0, rk3328_pll_frac_rates),
|
||||
[npll] = PLL(pll_rk3328, PLL_NPLL, "npll", mux_pll_p,
|
||||
0, RK3328_PLL_CON(40),
|
||||
RK3328_MODE_CON, 1, 0, 0, rk3328_pll_rates),
|
||||
};
|
||||
|
||||
#define MFLAGS CLK_MUX_HIWORD_MASK
|
||||
#define DFLAGS CLK_DIVIDER_HIWORD_MASK
|
||||
#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
|
||||
|
||||
static struct rockchip_clk_branch rk3328_i2s0_fracmux __initdata =
|
||||
MUX(0, "i2s0_pre", mux_i2s0_p, CLK_SET_RATE_PARENT,
|
||||
RK3328_CLKSEL_CON(6), 8, 2, MFLAGS);
|
||||
|
||||
static struct rockchip_clk_branch rk3328_i2s1_fracmux __initdata =
|
||||
MUX(0, "i2s1_pre", mux_i2s1_p, CLK_SET_RATE_PARENT,
|
||||
RK3328_CLKSEL_CON(8), 8, 2, MFLAGS);
|
||||
|
||||
static struct rockchip_clk_branch rk3328_i2s2_fracmux __initdata =
|
||||
MUX(0, "i2s2_pre", mux_i2s2_p, CLK_SET_RATE_PARENT,
|
||||
RK3328_CLKSEL_CON(10), 8, 2, MFLAGS);
|
||||
|
||||
static struct rockchip_clk_branch rk3328_spdif_fracmux __initdata =
|
||||
MUX(SCLK_SPDIF, "sclk_spdif", mux_spdif_p, CLK_SET_RATE_PARENT,
|
||||
RK3328_CLKSEL_CON(12), 8, 2, MFLAGS);
|
||||
|
||||
static struct rockchip_clk_branch rk3328_uart0_fracmux __initdata =
|
||||
MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
|
||||
RK3328_CLKSEL_CON(14), 8, 2, MFLAGS);
|
||||
|
||||
static struct rockchip_clk_branch rk3328_uart1_fracmux __initdata =
|
||||
MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
|
||||
RK3328_CLKSEL_CON(16), 8, 2, MFLAGS);
|
||||
|
||||
static struct rockchip_clk_branch rk3328_uart2_fracmux __initdata =
|
||||
MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
|
||||
RK3328_CLKSEL_CON(18), 8, 2, MFLAGS);
|
||||
|
||||
static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
|
||||
/*
|
||||
* Clock-Architecture Diagram 1
|
||||
*/
|
||||
|
||||
DIV(0, "clk_24m", "xin24m", CLK_IGNORE_UNUSED,
|
||||
RK3328_CLKSEL_CON(2), 8, 5, DFLAGS),
|
||||
COMPOSITE(SCLK_RTC32K, "clk_rtc32k", mux_2plls_xin24m_p, 0,
|
||||
RK3328_CLKSEL_CON(38), 14, 2, MFLAGS, 0, 14, DFLAGS,
|
||||
RK3328_CLKGATE_CON(0), 11, GFLAGS),
|
||||
|
||||
/* PD_MISC */
|
||||
MUX(HDMIPHY, "hdmiphy", mux_hdmiphy_p, CLK_SET_RATE_PARENT,
|
||||
RK3328_MISC_CON, 13, 1, MFLAGS),
|
||||
MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
|
||||
RK3328_MISC_CON, 15, 1, MFLAGS),
|
||||
|
||||
/*
|
||||
* Clock-Architecture Diagram 2
|
||||
*/
|
||||
|
||||
/* PD_CORE */
|
||||
GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
|
||||
RK3328_CLKGATE_CON(0), 0, GFLAGS),
|
||||
GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,
|
||||
RK3328_CLKGATE_CON(0), 2, GFLAGS),
|
||||
GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED,
|
||||
RK3328_CLKGATE_CON(0), 1, GFLAGS),
|
||||
GATE(0, "npll_core", "npll", CLK_IGNORE_UNUSED,
|
||||
RK3328_CLKGATE_CON(0), 12, GFLAGS),
|
||||
COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED,
|
||||
RK3328_CLKSEL_CON(1), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
|
||||
RK3328_CLKGATE_CON(7), 0, GFLAGS),
|
||||
COMPOSITE_NOMUX(0, "aclk_core", "armclk", CLK_IGNORE_UNUSED,
|
||||
RK3328_CLKSEL_CON(1), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
|
||||
RK3328_CLKGATE_CON(7), 1, GFLAGS),
|
||||
GATE(0, "aclk_core_niu", "aclk_core", CLK_IGNORE_UNUSED,
|
||||
RK3328_CLKGATE_CON(13), 0, GFLAGS),
|
||||
GATE(0, "aclk_gic400", "aclk_core", CLK_IGNORE_UNUSED,
|
||||
RK3328_CLKGATE_CON(13), 1, GFLAGS),
|
||||
|
||||
GATE(0, "clk_jtag", "jtag_clkin", CLK_IGNORE_UNUSED,
|
||||
RK3328_CLKGATE_CON(7), 2, GFLAGS),
|
||||
|
||||
/* PD_GPU */
|
||||
COMPOSITE(0, "aclk_gpu_pre", mux_4plls_p, 0,
|
||||
RK3328_CLKSEL_CON(44), 6, 2, MFLAGS, 0, 5, DFLAGS,
|
||||
RK3328_CLKGATE_CON(6), 6, GFLAGS),
|
||||
GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", CLK_SET_RATE_PARENT,
|
||||
RK3328_CLKGATE_CON(14), 0, GFLAGS),
|
||||
GATE(0, "aclk_gpu_niu", "aclk_gpu_pre", CLK_IGNORE_UNUSED,
|
||||
RK3328_CLKGATE_CON(14), 1, GFLAGS),
|
||||
|
||||
/* PD_DDR */
|
||||
COMPOSITE(0, "clk_ddr", mux_ddrphy_p, CLK_IGNORE_UNUSED,
|
||||
RK3328_CLKSEL_CON(3), 8, 2, MFLAGS, 0, 3, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
|
||||
RK3328_CLKGATE_CON(0), 4, GFLAGS),
|
||||
GATE(0, "clk_ddrmsch", "clk_ddr", CLK_IGNORE_UNUSED,
|
||||
RK3328_CLKGATE_CON(18), 6, GFLAGS),
|
||||
GATE(0, "clk_ddrupctl", "clk_ddr", CLK_IGNORE_UNUSED,
|
||||
RK3328_CLKGATE_CON(18), 5, GFLAGS),
|
||||
GATE(0, "aclk_ddrupctl", "clk_ddr", CLK_IGNORE_UNUSED,
|
||||
RK3328_CLKGATE_CON(18), 4, GFLAGS),
|
||||
GATE(0, "clk_ddrmon", "xin24m", CLK_IGNORE_UNUSED,
|
||||
RK3328_CLKGATE_CON(0), 6, GFLAGS),
|
||||
|
||||
COMPOSITE(PCLK_DDR, "pclk_ddr", mux_2plls_hdmiphy_p, 0,
|
||||
RK3328_CLKSEL_CON(4), 13, 2, MFLAGS, 8, 3, DFLAGS,
|
||||
RK3328_CLKGATE_CON(7), 4, GFLAGS),
|
||||
GATE(0, "pclk_ddrupctl", "pclk_ddr", CLK_IGNORE_UNUSED,
|
||||
RK3328_CLKGATE_CON(18), 1, GFLAGS),
|
||||
GATE(0, "pclk_ddr_msch", "pclk_ddr", CLK_IGNORE_UNUSED,
|
||||
RK3328_CLKGATE_CON(18), 2, GFLAGS),
|
||||
GATE(0, "pclk_ddr_mon", "pclk_ddr", CLK_IGNORE_UNUSED,
|
||||
RK3328_CLKGATE_CON(18), 3, GFLAGS),
|
||||
GATE(0, "pclk_ddrstdby", "pclk_ddr", CLK_IGNORE_UNUSED,
|
||||
RK3328_CLKGATE_CON(18), 7, GFLAGS),
|
||||
GATE(0, "pclk_ddr_grf", "pclk_ddr", CLK_IGNORE_UNUSED,
|
||||
RK3328_CLKGATE_CON(18), 9, GFLAGS),
|
||||
|
||||
/*
|
||||
* Clock-Architecture Diagram 3
|
||||
*/
|
||||
|
||||
/* PD_BUS */
|
||||
COMPOSITE(ACLK_BUS_PRE, "aclk_bus_pre", mux_2plls_hdmiphy_p, 0,
|
||||
RK3328_CLKSEL_CON(0), 13, 2, MFLAGS, 8, 5, DFLAGS,
|
||||
RK3328_CLKGATE_CON(8), 0, GFLAGS),
|
||||
COMPOSITE_NOMUX(HCLK_BUS_PRE, "hclk_bus_pre", "aclk_bus_pre", 0,
|
||||
RK3328_CLKSEL_CON(1), 8, 2, DFLAGS,
|
||||
RK3328_CLKGATE_CON(8), 1, GFLAGS),
|
||||
COMPOSITE_NOMUX(PCLK_BUS_PRE, "pclk_bus_pre", "aclk_bus_pre", 0,
|
||||
RK3328_CLKSEL_CON(1), 12, 3, DFLAGS,
|
||||
RK3328_CLKGATE_CON(8), 2, GFLAGS),
|
||||
GATE(0, "pclk_bus", "pclk_bus_pre", 0,
|
||||
RK3328_CLKGATE_CON(8), 3, GFLAGS),
|
||||
GATE(0, "pclk_phy_pre", "pclk_bus_pre", 0,
|
||||
RK3328_CLKGATE_CON(8), 4, GFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_TSP, "clk_tsp", mux_2plls_p, 0,
|
||||
RK3328_CLKSEL_CON(21), 15, 1, MFLAGS, 8, 5, DFLAGS,
|
||||
RK3328_CLKGATE_CON(2), 5, GFLAGS),
|
||||
GATE(0, "clk_hsadc_tsp", "ext_gpio3a2", 0,
|
||||
RK3328_CLKGATE_CON(17), 13, GFLAGS),
|
||||
|
||||
/* PD_I2S */
|
||||
COMPOSITE(0, "clk_i2s0_div", mux_2plls_p, 0,
|
||||
RK3328_CLKSEL_CON(6), 15, 1, MFLAGS, 0, 7, DFLAGS,
|
||||
RK3328_CLKGATE_CON(1), 1, GFLAGS),
|
||||
COMPOSITE_FRACMUX(0, "clk_i2s0_frac", "clk_i2s0_div", CLK_SET_RATE_PARENT,
|
||||
RK3328_CLKSEL_CON(7), 0,
|
||||
RK3328_CLKGATE_CON(1), 2, GFLAGS,
|
||||
&rk3328_i2s0_fracmux),
|
||||
GATE(SCLK_I2S0, "clk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT,
|
||||
RK3328_CLKGATE_CON(1), 3, GFLAGS),
|
||||
|
||||
COMPOSITE(0, "clk_i2s1_div", mux_2plls_p, 0,
|
||||
RK3328_CLKSEL_CON(8), 15, 1, MFLAGS, 0, 7, DFLAGS,
|
||||
RK3328_CLKGATE_CON(1), 4, GFLAGS),
|
||||
COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_div", CLK_SET_RATE_PARENT,
|
||||
RK3328_CLKSEL_CON(9), 0,
|
||||
RK3328_CLKGATE_CON(1), 5, GFLAGS,
|
||||
&rk3328_i2s1_fracmux),
|
||||
GATE(SCLK_I2S1, "clk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT,
|
||||
RK3328_CLKGATE_CON(0), 6, GFLAGS),
|
||||
COMPOSITE_NODIV(SCLK_I2S1_OUT, "i2s1_out", mux_i2s1out_p, 0,
|
||||
RK3328_CLKSEL_CON(8), 12, 1, MFLAGS,
|
||||
RK3328_CLKGATE_CON(1), 7, GFLAGS),
|
||||
|
||||
COMPOSITE(0, "clk_i2s2_div", mux_2plls_p, 0,
|
||||
RK3328_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 7, DFLAGS,
|
||||
RK3328_CLKGATE_CON(1), 8, GFLAGS),
|
||||
COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_div", CLK_SET_RATE_PARENT,
|
||||
RK3328_CLKSEL_CON(11), 0,
|
||||
RK3328_CLKGATE_CON(1), 9, GFLAGS,
|
||||
&rk3328_i2s2_fracmux),
|
||||
GATE(SCLK_I2S2, "clk_i2s2", "i2s2_pre", CLK_SET_RATE_PARENT,
|
||||
RK3328_CLKGATE_CON(1), 10, GFLAGS),
|
||||
COMPOSITE_NODIV(SCLK_I2S2_OUT, "i2s2_out", mux_i2s2out_p, 0,
|
||||
RK3328_CLKSEL_CON(10), 12, 1, MFLAGS,
|
||||
RK3328_CLKGATE_CON(1), 11, GFLAGS),
|
||||
|
||||
COMPOSITE(0, "clk_spdif_div", mux_2plls_p, 0,
|
||||
RK3328_CLKSEL_CON(12), 15, 1, MFLAGS, 0, 7, DFLAGS,
|
||||
RK3328_CLKGATE_CON(1), 12, GFLAGS),
|
||||
COMPOSITE_FRACMUX(0, "clk_spdif_frac", "clk_spdif_div", CLK_SET_RATE_PARENT,
|
||||
RK3328_CLKSEL_CON(13), 0,
|
||||
RK3328_CLKGATE_CON(1), 13, GFLAGS,
|
||||
&rk3328_spdif_fracmux),
|
||||
|
||||
/* PD_UART */
|
||||
COMPOSITE(0, "clk_uart0_div", mux_2plls_u480m_p, 0,
|
||||
RK3328_CLKSEL_CON(14), 12, 2, MFLAGS, 0, 7, DFLAGS,
|
||||
RK3328_CLKGATE_CON(1), 14, GFLAGS),
|
||||
COMPOSITE(0, "clk_uart1_div", mux_2plls_u480m_p, 0,
|
||||
RK3328_CLKSEL_CON(16), 12, 2, MFLAGS, 0, 7, DFLAGS,
|
||||
RK3328_CLKGATE_CON(2), 0, GFLAGS),
|
||||
COMPOSITE(0, "clk_uart2_div", mux_2plls_u480m_p, 0,
|
||||
RK3328_CLKSEL_CON(18), 12, 2, MFLAGS, 0, 7, DFLAGS,
|
||||
RK3328_CLKGATE_CON(2), 2, GFLAGS),
|
||||
COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_div", CLK_SET_RATE_PARENT,
|
||||
RK3328_CLKSEL_CON(15), 0,
|
||||
RK3328_CLKGATE_CON(1), 15, GFLAGS,
|
||||
&rk3328_uart0_fracmux),
|
||||
COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_div", CLK_SET_RATE_PARENT,
|
||||
RK3328_CLKSEL_CON(17), 0,
|
||||
RK3328_CLKGATE_CON(2), 1, GFLAGS,
|
||||
&rk3328_uart1_fracmux),
|
||||
COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_div", CLK_SET_RATE_PARENT,
|
||||
RK3328_CLKSEL_CON(19), 0,
|
||||
RK3328_CLKGATE_CON(2), 3, GFLAGS,
|
||||
&rk3328_uart2_fracmux),
|
||||
|
||||
/*
|
||||
* Clock-Architecture Diagram 4
|
||||
*/
|
||||
|
||||
COMPOSITE(SCLK_I2C0, "clk_i2c0", mux_2plls_p, 0,
|
||||
RK3328_CLKSEL_CON(34), 7, 1, MFLAGS, 0, 7, DFLAGS,
|
||||
RK3328_CLKGATE_CON(2), 9, GFLAGS),
|
||||
COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_2plls_p, 0,
|
||||
RK3328_CLKSEL_CON(34), 15, 1, MFLAGS, 8, 7, DFLAGS,
|
||||
RK3328_CLKGATE_CON(2), 10, GFLAGS),
|
||||
COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_2plls_p, 0,
|
||||
RK3328_CLKSEL_CON(35), 7, 1, MFLAGS, 0, 7, DFLAGS,
|
||||
RK3328_CLKGATE_CON(2), 11, GFLAGS),
|
||||
COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_2plls_p, 0,
|
||||
RK3328_CLKSEL_CON(35), 15, 1, MFLAGS, 8, 7, DFLAGS,
|
||||
RK3328_CLKGATE_CON(2), 12, GFLAGS),
|
||||
COMPOSITE(SCLK_CRYPTO, "clk_crypto", mux_2plls_p, 0,
|
||||
RK3328_CLKSEL_CON(20), 7, 1, MFLAGS, 0, 7, DFLAGS,
|
||||
RK3328_CLKGATE_CON(2), 4, GFLAGS),
|
||||
COMPOSITE_NOMUX(SCLK_TSADC, "clk_tsadc", "clk_24m", 0,
|
||||
RK3328_CLKSEL_CON(22), 0, 10, DFLAGS,
|
||||
RK3328_CLKGATE_CON(2), 6, GFLAGS),
|
||||
COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "clk_24m", 0,
|
||||
RK3328_CLKSEL_CON(23), 0, 10, DFLAGS,
|
||||
RK3328_CLKGATE_CON(2), 14, GFLAGS),
|
||||
COMPOSITE(SCLK_SPI, "clk_spi", mux_2plls_p, 0,
|
||||
RK3328_CLKSEL_CON(24), 7, 1, MFLAGS, 0, 7, DFLAGS,
|
||||
RK3328_CLKGATE_CON(2), 7, GFLAGS),
|
||||
COMPOSITE(SCLK_PWM, "clk_pwm", mux_2plls_p, 0,
|
||||
RK3328_CLKSEL_CON(24), 15, 1, MFLAGS, 8, 7, DFLAGS,
|
||||
RK3328_CLKGATE_CON(2), 8, GFLAGS),
|
||||
COMPOSITE(SCLK_OTP, "clk_otp", mux_2plls_xin24m_p, 0,
|
||||
RK3328_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 6, DFLAGS,
|
||||
RK3328_CLKGATE_CON(3), 8, GFLAGS),
|
||||
COMPOSITE(SCLK_EFUSE, "clk_efuse", mux_2plls_xin24m_p, 0,
|
||||
RK3328_CLKSEL_CON(5), 14, 2, MFLAGS, 8, 5, DFLAGS,
|
||||
RK3328_CLKGATE_CON(2), 13, GFLAGS),
|
||||
COMPOSITE(SCLK_PDM, "clk_pdm", mux_cpll_gpll_apll_p, CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
|
||||
RK3328_CLKSEL_CON(20), 14, 2, MFLAGS, 8, 5, DFLAGS,
|
||||
RK3328_CLKGATE_CON(2), 15, GFLAGS),
|
||||
|
||||
GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
|
||||
RK3328_CLKGATE_CON(8), 5, GFLAGS),
|
||||
GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
|
||||
RK3328_CLKGATE_CON(8), 6, GFLAGS),
|
||||
GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
|
||||
RK3328_CLKGATE_CON(8), 7, GFLAGS),
|
||||
GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0,
|
||||
RK3328_CLKGATE_CON(8), 8, GFLAGS),
|
||||
GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0,
|
||||
RK3328_CLKGATE_CON(8), 9, GFLAGS),
|
||||
GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0,
|
||||
RK3328_CLKGATE_CON(8), 10, GFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_WIFI, "clk_wifi", mux_2plls_u480m_p, 0,
|
||||
RK3328_CLKSEL_CON(52), 6, 2, MFLAGS, 0, 6, DFLAGS,
|
||||
RK3328_CLKGATE_CON(0), 10, GFLAGS),
|
||||
|
||||
/*
|
||||
* Clock-Architecture Diagram 5
|
||||
*/
|
||||
|
||||
/* PD_VIDEO */
|
||||
COMPOSITE(ACLK_RKVDEC_PRE, "aclk_rkvdec_pre", mux_4plls_p, 0,
|
||||
RK3328_CLKSEL_CON(48), 6, 2, MFLAGS, 0, 5, DFLAGS,
|
||||
RK3328_CLKGATE_CON(6), 0, GFLAGS),
|
||||
FACTOR_GATE(HCLK_RKVDEC_PRE, "hclk_rkvdec_pre", "aclk_rkvdec_pre", 0, 1, 4,
|
||||
RK3328_CLKGATE_CON(11), 0, GFLAGS),
|
||||
GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", CLK_SET_RATE_PARENT,
|
||||
RK3328_CLKGATE_CON(24), 0, GFLAGS),
|
||||
GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", CLK_SET_RATE_PARENT,
|
||||
RK3328_CLKGATE_CON(24), 1, GFLAGS),
|
||||
GATE(0, "aclk_rkvdec_niu", "aclk_rkvdec_pre", CLK_IGNORE_UNUSED,
|
||||
RK3328_CLKGATE_CON(24), 2, GFLAGS),
|
||||
GATE(0, "hclk_rkvdec_niu", "hclk_rkvdec_pre", CLK_IGNORE_UNUSED,
|
||||
RK3328_CLKGATE_CON(24), 3, GFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_VDEC_CABAC, "sclk_vdec_cabac", mux_4plls_p, 0,
|
||||
RK3328_CLKSEL_CON(48), 14, 2, MFLAGS, 8, 5, DFLAGS,
|
||||
RK3328_CLKGATE_CON(6), 1, GFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_VDEC_CORE, "sclk_vdec_core", mux_4plls_p, 0,
|
||||
RK3328_CLKSEL_CON(49), 6, 2, MFLAGS, 0, 5, DFLAGS,
|
||||
RK3328_CLKGATE_CON(6), 2, GFLAGS),
|
||||
|
||||
COMPOSITE(ACLK_VPU_PRE, "aclk_vpu_pre", mux_4plls_p, 0,
|
||||
RK3328_CLKSEL_CON(50), 6, 2, MFLAGS, 0, 5, DFLAGS,
|
||||
RK3328_CLKGATE_CON(6), 5, GFLAGS),
|
||||
FACTOR_GATE(HCLK_VPU_PRE, "hclk_vpu_pre", "aclk_vpu_pre", 0, 1, 4,
|
||||
RK3328_CLKGATE_CON(11), 8, GFLAGS),
|
||||
GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", CLK_SET_RATE_PARENT,
|
||||
RK3328_CLKGATE_CON(23), 0, GFLAGS),
|
||||
GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", CLK_SET_RATE_PARENT,
|
||||
RK3328_CLKGATE_CON(23), 1, GFLAGS),
|
||||
GATE(0, "aclk_vpu_niu", "aclk_vpu_pre", CLK_IGNORE_UNUSED,
|
||||
RK3328_CLKGATE_CON(23), 2, GFLAGS),
|
||||
GATE(0, "hclk_vpu_niu", "hclk_vpu_pre", CLK_IGNORE_UNUSED,
|
||||
RK3328_CLKGATE_CON(23), 3, GFLAGS),
|
||||
|
||||
COMPOSITE(ACLK_RKVENC, "aclk_rkvenc", mux_4plls_p, 0,
|
||||
RK3328_CLKSEL_CON(51), 6, 2, MFLAGS, 0, 5, DFLAGS,
|
||||
RK3328_CLKGATE_CON(6), 3, GFLAGS),
|
||||
FACTOR_GATE(HCLK_RKVENC, "hclk_rkvenc", "aclk_rkvenc", 0, 1, 4,
|
||||
RK3328_CLKGATE_CON(11), 4, GFLAGS),
|
||||
GATE(0, "aclk_rkvenc_niu", "aclk_rkvenc", CLK_IGNORE_UNUSED,
|
||||
RK3328_CLKGATE_CON(25), 0, GFLAGS),
|
||||
GATE(0, "hclk_rkvenc_niu", "hclk_rkvenc", CLK_IGNORE_UNUSED,
|
||||
RK3328_CLKGATE_CON(25), 1, GFLAGS),
|
||||
GATE(ACLK_H265, "aclk_h265", "aclk_rkvenc", 0,
|
||||
RK3328_CLKGATE_CON(25), 0, GFLAGS),
|
||||
GATE(PCLK_H265, "pclk_h265", "hclk_rkvenc", 0,
|
||||
RK3328_CLKGATE_CON(25), 1, GFLAGS),
|
||||
GATE(ACLK_H264, "aclk_h264", "aclk_rkvenc", 0,
|
||||
RK3328_CLKGATE_CON(25), 0, GFLAGS),
|
||||
GATE(HCLK_H264, "hclk_h264", "hclk_rkvenc", 0,
|
||||
RK3328_CLKGATE_CON(25), 1, GFLAGS),
|
||||
GATE(ACLK_AXISRAM, "aclk_axisram", "aclk_rkvenc", CLK_IGNORE_UNUSED,
|
||||
RK3328_CLKGATE_CON(25), 0, GFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_VENC_CORE, "sclk_venc_core", mux_4plls_p, 0,
|
||||
RK3328_CLKSEL_CON(51), 14, 2, MFLAGS, 8, 5, DFLAGS,
|
||||
RK3328_CLKGATE_CON(6), 4, GFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_VENC_DSP, "sclk_venc_dsp", mux_4plls_p, 0,
|
||||
RK3328_CLKSEL_CON(52), 14, 2, MFLAGS, 8, 5, DFLAGS,
|
||||
RK3328_CLKGATE_CON(6), 7, GFLAGS),
|
||||
|
||||
/*
|
||||
* Clock-Architecture Diagram 6
|
||||
*/
|
||||
|
||||
/* PD_VIO */
|
||||
COMPOSITE(ACLK_VIO_PRE, "aclk_vio_pre", mux_4plls_p, 0,
|
||||
RK3328_CLKSEL_CON(37), 6, 2, MFLAGS, 0, 5, DFLAGS,
|
||||
RK3328_CLKGATE_CON(5), 2, GFLAGS),
|
||||
DIV(HCLK_VIO_PRE, "hclk_vio_pre", "aclk_vio_pre", 0,
|
||||
RK3328_CLKSEL_CON(37), 8, 5, DFLAGS),
|
||||
|
||||
COMPOSITE(ACLK_RGA_PRE, "aclk_rga_pre", mux_4plls_p, 0,
|
||||
RK3328_CLKSEL_CON(36), 14, 2, MFLAGS, 8, 5, DFLAGS,
|
||||
RK3328_CLKGATE_CON(5), 0, GFLAGS),
|
||||
COMPOSITE(SCLK_RGA, "clk_rga", mux_4plls_p, 0,
|
||||
RK3328_CLKSEL_CON(36), 6, 2, MFLAGS, 0, 5, DFLAGS,
|
||||
RK3328_CLKGATE_CON(5), 1, GFLAGS),
|
||||
COMPOSITE(ACLK_VOP_PRE, "aclk_vop_pre", mux_4plls_p, 0,
|
||||
RK3328_CLKSEL_CON(39), 6, 2, MFLAGS, 0, 5, DFLAGS,
|
||||
RK3328_CLKGATE_CON(5), 5, GFLAGS),
|
||||
GATE(0, "clk_hdmi_sfc", "xin24m", 0,
|
||||
RK3328_CLKGATE_CON(5), 4, GFLAGS),
|
||||
|
||||
COMPOSITE_NODIV(0, "clk_cif_src", mux_2plls_p, 0,
|
||||
RK3328_CLKSEL_CON(42), 7, 1, MFLAGS,
|
||||
RK3328_CLKGATE_CON(5), 3, GFLAGS),
|
||||
COMPOSITE_NOGATE(SCLK_CIF_OUT, "clk_cif_out", mux_sclk_cif_p, CLK_SET_RATE_PARENT,
|
||||
RK3328_CLKSEL_CON(42), 5, 1, MFLAGS, 0, 5, DFLAGS),
|
||||
|
||||
COMPOSITE(DCLK_LCDC_SRC, "dclk_lcdc_src", mux_gpll_cpll_p, 0,
|
||||
RK3328_CLKSEL_CON(40), 0, 1, MFLAGS, 8, 8, DFLAGS,
|
||||
RK3328_CLKGATE_CON(5), 6, GFLAGS),
|
||||
DIV(DCLK_HDMIPHY, "dclk_hdmiphy", "dclk_lcdc_src", 0,
|
||||
RK3328_CLKSEL_CON(40), 3, 3, DFLAGS),
|
||||
MUX(DCLK_LCDC, "dclk_lcdc", mux_dclk_lcdc_p, 0,
|
||||
RK3328_CLKSEL_CON(40), 1, 1, MFLAGS),
|
||||
|
||||
/*
|
||||
* Clock-Architecture Diagram 7
|
||||
*/
|
||||
|
||||
/* PD_PERI */
|
||||
GATE(0, "gpll_peri", "gpll", CLK_IGNORE_UNUSED,
|
||||
RK3328_CLKGATE_CON(4), 0, GFLAGS),
|
||||
GATE(0, "cpll_peri", "cpll", CLK_IGNORE_UNUSED,
|
||||
RK3328_CLKGATE_CON(4), 1, GFLAGS),
|
||||
GATE(0, "hdmiphy_peri", "hdmiphy", CLK_IGNORE_UNUSED,
|
||||
RK3328_CLKGATE_CON(4), 2, GFLAGS),
|
||||
COMPOSITE_NOGATE(ACLK_PERI_PRE, "aclk_peri_pre", mux_aclk_peri_pre_p, 0,
|
||||
RK3328_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 5, DFLAGS),
|
||||
COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_pre", CLK_IGNORE_UNUSED,
|
||||
RK3328_CLKSEL_CON(29), 0, 2, DFLAGS,
|
||||
RK3328_CLKGATE_CON(10), 2, GFLAGS),
|
||||
COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_pre", CLK_IGNORE_UNUSED,
|
||||
RK3328_CLKSEL_CON(29), 4, 3, DFLAGS,
|
||||
RK3328_CLKGATE_CON(10), 1, GFLAGS),
|
||||
GATE(ACLK_PERI, "aclk_peri", "aclk_peri_pre", CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT,
|
||||
RK3328_CLKGATE_CON(10), 0, GFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_SDMMC, "clk_sdmmc", mux_2plls_24m_u480m_p, 0,
|
||||
RK3328_CLKSEL_CON(30), 8, 2, MFLAGS, 0, 8, DFLAGS,
|
||||
RK3328_CLKGATE_CON(4), 3, GFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_SDIO, "clk_sdio", mux_2plls_24m_u480m_p, 0,
|
||||
RK3328_CLKSEL_CON(31), 8, 2, MFLAGS, 0, 8, DFLAGS,
|
||||
RK3328_CLKGATE_CON(4), 4, GFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_EMMC, "clk_emmc", mux_2plls_24m_u480m_p, 0,
|
||||
RK3328_CLKSEL_CON(32), 8, 2, MFLAGS, 0, 8, DFLAGS,
|
||||
RK3328_CLKGATE_CON(4), 5, GFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_SDMMC_EXT, "clk_sdmmc_ext", mux_2plls_24m_u480m_p, 0,
|
||||
RK3328_CLKSEL_CON(43), 8, 2, MFLAGS, 0, 8, DFLAGS,
|
||||
RK3328_CLKGATE_CON(4), 10, GFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_REF_USB3OTG_SRC, "clk_ref_usb3otg_src", mux_2plls_p, 0,
|
||||
RK3328_CLKSEL_CON(45), 7, 1, MFLAGS, 0, 7, DFLAGS,
|
||||
RK3328_CLKGATE_CON(4), 9, GFLAGS),
|
||||
|
||||
MUX(SCLK_REF_USB3OTG, "clk_ref_usb3otg", mux_ref_usb3otg_src_p, CLK_SET_RATE_PARENT,
|
||||
RK3328_CLKSEL_CON(45), 8, 1, MFLAGS),
|
||||
|
||||
GATE(SCLK_USB3OTG_REF, "clk_usb3otg_ref", "xin24m", 0,
|
||||
RK3328_CLKGATE_CON(4), 7, GFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_USB3OTG_SUSPEND, "clk_usb3otg_suspend", mux_xin24m_32k_p, 0,
|
||||
RK3328_CLKSEL_CON(33), 15, 1, MFLAGS, 0, 10, DFLAGS,
|
||||
RK3328_CLKGATE_CON(4), 8, GFLAGS),
|
||||
|
||||
/*
|
||||
* Clock-Architecture Diagram 8
|
||||
*/
|
||||
|
||||
/* PD_GMAC */
|
||||
COMPOSITE(ACLK_GMAC, "aclk_gmac", mux_2plls_hdmiphy_p, 0,
|
||||
RK3328_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS,
|
||||
RK3328_CLKGATE_CON(3), 2, GFLAGS),
|
||||
COMPOSITE_NOMUX(PCLK_GMAC, "pclk_gmac", "aclk_gmac", 0,
|
||||
RK3328_CLKSEL_CON(25), 8, 3, DFLAGS,
|
||||
RK3328_CLKGATE_CON(9), 0, GFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_MAC2IO_SRC, "clk_mac2io_src", mux_2plls_p, 0,
|
||||
RK3328_CLKSEL_CON(27), 7, 1, MFLAGS, 0, 5, DFLAGS,
|
||||
RK3328_CLKGATE_CON(3), 1, GFLAGS),
|
||||
GATE(SCLK_MAC2IO_REF, "clk_mac2io_ref", "clk_mac2io", 0,
|
||||
RK3328_CLKGATE_CON(9), 7, GFLAGS),
|
||||
GATE(SCLK_MAC2IO_RX, "clk_mac2io_rx", "clk_mac2io", 0,
|
||||
RK3328_CLKGATE_CON(9), 4, GFLAGS),
|
||||
GATE(SCLK_MAC2IO_TX, "clk_mac2io_tx", "clk_mac2io", 0,
|
||||
RK3328_CLKGATE_CON(9), 5, GFLAGS),
|
||||
GATE(SCLK_MAC2IO_REFOUT, "clk_mac2io_refout", "clk_mac2io", 0,
|
||||
RK3328_CLKGATE_CON(9), 6, GFLAGS),
|
||||
COMPOSITE(SCLK_MAC2IO_OUT, "clk_mac2io_out", mux_2plls_p, 0,
|
||||
RK3328_CLKSEL_CON(27), 15, 1, MFLAGS, 8, 5, DFLAGS,
|
||||
RK3328_CLKGATE_CON(3), 5, GFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_MAC2PHY_SRC, "clk_mac2phy_src", mux_2plls_p, 0,
|
||||
RK3328_CLKSEL_CON(26), 7, 1, MFLAGS, 0, 5, DFLAGS,
|
||||
RK3328_CLKGATE_CON(3), 0, GFLAGS),
|
||||
GATE(SCLK_MAC2PHY_REF, "clk_mac2phy_ref", "clk_mac2phy", 0,
|
||||
RK3328_CLKGATE_CON(9), 3, GFLAGS),
|
||||
GATE(SCLK_MAC2PHY_RXTX, "clk_mac2phy_rxtx", "clk_mac2phy", 0,
|
||||
RK3328_CLKGATE_CON(9), 1, GFLAGS),
|
||||
COMPOSITE_NOMUX(SCLK_MAC2PHY_OUT, "clk_mac2phy_out", "clk_mac2phy", 0,
|
||||
RK3328_CLKSEL_CON(26), 8, 2, DFLAGS,
|
||||
RK3328_CLKGATE_CON(9), 2, GFLAGS),
|
||||
|
||||
FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
|
||||
|
||||
/*
|
||||
* Clock-Architecture Diagram 9
|
||||
*/
|
||||
|
||||
/* PD_VOP */
|
||||
GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK3328_CLKGATE_CON(21), 10, GFLAGS),
|
||||
GATE(0, "aclk_rga_niu", "aclk_rga_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(22), 3, GFLAGS),
|
||||
GATE(ACLK_VOP, "aclk_vop", "aclk_vop_pre", 0, RK3328_CLKGATE_CON(21), 2, GFLAGS),
|
||||
GATE(0, "aclk_vop_niu", "aclk_vop_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(21), 4, GFLAGS),
|
||||
|
||||
GATE(ACLK_IEP, "aclk_iep", "aclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 6, GFLAGS),
|
||||
GATE(ACLK_CIF, "aclk_cif", "aclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 8, GFLAGS),
|
||||
GATE(ACLK_HDCP, "aclk_hdcp", "aclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 15, GFLAGS),
|
||||
GATE(0, "aclk_vio_niu", "aclk_vio_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(22), 2, GFLAGS),
|
||||
|
||||
GATE(HCLK_VOP, "hclk_vop", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 3, GFLAGS),
|
||||
GATE(0, "hclk_vop_niu", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 5, GFLAGS),
|
||||
GATE(HCLK_IEP, "hclk_iep", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 7, GFLAGS),
|
||||
GATE(HCLK_CIF, "hclk_cif", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 9, GFLAGS),
|
||||
GATE(HCLK_RGA, "hclk_rga", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 11, GFLAGS),
|
||||
GATE(0, "hclk_ahb1tom", "hclk_vio_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(21), 12, GFLAGS),
|
||||
GATE(0, "pclk_vio_h2p", "hclk_vio_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(21), 13, GFLAGS),
|
||||
GATE(0, "hclk_vio_h2p", "hclk_vio_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(21), 14, GFLAGS),
|
||||
GATE(HCLK_HDCP, "hclk_hdcp", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(22), 0, GFLAGS),
|
||||
GATE(HCLK_VIO, "hclk_vio", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(22), 1, GFLAGS),
|
||||
GATE(PCLK_HDMI, "pclk_hdmi", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(22), 4, GFLAGS),
|
||||
GATE(PCLK_HDCP, "pclk_hdcp", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(22), 5, GFLAGS),
|
||||
|
||||
/* PD_PERI */
|
||||
GATE(0, "aclk_peri_noc", "aclk_peri", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(19), 11, GFLAGS),
|
||||
GATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_peri", 0, RK3328_CLKGATE_CON(19), 4, GFLAGS),
|
||||
|
||||
GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 0, GFLAGS),
|
||||
GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 1, GFLAGS),
|
||||
GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 2, GFLAGS),
|
||||
GATE(HCLK_SDMMC_EXT, "hclk_sdmmc_ext", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 15, GFLAGS),
|
||||
GATE(HCLK_HOST0, "hclk_host0", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 6, GFLAGS),
|
||||
GATE(HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_peri", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(19), 7, GFLAGS),
|
||||
GATE(HCLK_OTG, "hclk_otg", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 8, GFLAGS),
|
||||
GATE(HCLK_OTG_PMU, "hclk_otg_pmu", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 9, GFLAGS),
|
||||
GATE(0, "hclk_peri_niu", "hclk_peri", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(19), 12, GFLAGS),
|
||||
GATE(0, "pclk_peri_niu", "hclk_peri", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(19), 13, GFLAGS),
|
||||
|
||||
/* PD_GMAC */
|
||||
GATE(ACLK_MAC2PHY, "aclk_mac2phy", "aclk_gmac", 0, RK3328_CLKGATE_CON(26), 0, GFLAGS),
|
||||
GATE(ACLK_MAC2IO, "aclk_mac2io", "aclk_gmac", 0, RK3328_CLKGATE_CON(26), 2, GFLAGS),
|
||||
GATE(0, "aclk_gmac_niu", "aclk_gmac", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(26), 4, GFLAGS),
|
||||
GATE(PCLK_MAC2PHY, "pclk_mac2phy", "pclk_gmac", 0, RK3328_CLKGATE_CON(26), 1, GFLAGS),
|
||||
GATE(PCLK_MAC2IO, "pclk_mac2io", "pclk_gmac", 0, RK3328_CLKGATE_CON(26), 3, GFLAGS),
|
||||
GATE(0, "pclk_gmac_niu", "pclk_gmac", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(26), 5, GFLAGS),
|
||||
|
||||
/* PD_BUS */
|
||||
GATE(0, "aclk_bus_niu", "aclk_bus_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(15), 12, GFLAGS),
|
||||
GATE(ACLK_DCF, "aclk_dcf", "aclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 11, GFLAGS),
|
||||
GATE(ACLK_TSP, "aclk_tsp", "aclk_bus_pre", 0, RK3328_CLKGATE_CON(17), 12, GFLAGS),
|
||||
GATE(0, "aclk_intmem", "aclk_bus_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(15), 0, GFLAGS),
|
||||
GATE(ACLK_DMAC, "aclk_dmac_bus", "aclk_bus_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(15), 1, GFLAGS),
|
||||
|
||||
GATE(0, "hclk_rom", "hclk_bus_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(15), 2, GFLAGS),
|
||||
GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 3, GFLAGS),
|
||||
GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 4, GFLAGS),
|
||||
GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 5, GFLAGS),
|
||||
GATE(HCLK_SPDIF_8CH, "hclk_spdif_8ch", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 6, GFLAGS),
|
||||
GATE(HCLK_TSP, "hclk_tsp", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(17), 11, GFLAGS),
|
||||
GATE(HCLK_CRYPTO_MST, "hclk_crypto_mst", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 7, GFLAGS),
|
||||
GATE(HCLK_CRYPTO_SLV, "hclk_crypto_slv", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 8, GFLAGS),
|
||||
GATE(0, "hclk_bus_niu", "hclk_bus_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(15), 13, GFLAGS),
|
||||
GATE(HCLK_PDM, "hclk_pdm", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(28), 0, GFLAGS),
|
||||
|
||||
GATE(0, "pclk_bus_niu", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(15), 14, GFLAGS),
|
||||
GATE(0, "pclk_efuse", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(15), 9, GFLAGS),
|
||||
GATE(0, "pclk_otp", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(28), 4, GFLAGS),
|
||||
GATE(PCLK_I2C0, "pclk_i2c0", "pclk_bus", 0, RK3328_CLKGATE_CON(15), 10, GFLAGS),
|
||||
GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 0, GFLAGS),
|
||||
GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 1, GFLAGS),
|
||||
GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 2, GFLAGS),
|
||||
GATE(PCLK_TIMER, "pclk_timer0", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 3, GFLAGS),
|
||||
GATE(0, "pclk_stimer", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 4, GFLAGS),
|
||||
GATE(PCLK_SPI, "pclk_spi", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 5, GFLAGS),
|
||||
GATE(PCLK_PWM, "pclk_rk_pwm", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 6, GFLAGS),
|
||||
GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 7, GFLAGS),
|
||||
GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 8, GFLAGS),
|
||||
GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 9, GFLAGS),
|
||||
GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 10, GFLAGS),
|
||||
GATE(PCLK_UART0, "pclk_uart0", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 11, GFLAGS),
|
||||
GATE(PCLK_UART1, "pclk_uart1", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 12, GFLAGS),
|
||||
GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 13, GFLAGS),
|
||||
GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 14, GFLAGS),
|
||||
GATE(PCLK_DCF, "pclk_dcf", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 15, GFLAGS),
|
||||
GATE(PCLK_GRF, "pclk_grf", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 0, GFLAGS),
|
||||
GATE(0, "pclk_cru", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 4, GFLAGS),
|
||||
GATE(0, "pclk_sgrf", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 6, GFLAGS),
|
||||
GATE(0, "pclk_sim", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 10, GFLAGS),
|
||||
GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus", 0, RK3328_CLKGATE_CON(17), 15, GFLAGS),
|
||||
GATE(0, "pclk_pmu", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(28), 3, GFLAGS),
|
||||
|
||||
GATE(PCLK_USB3PHY_OTG, "pclk_usb3phy_otg", "pclk_phy_pre", 0, RK3328_CLKGATE_CON(28), 1, GFLAGS),
|
||||
GATE(PCLK_USB3PHY_PIPE, "pclk_usb3phy_pipe", "pclk_phy_pre", 0, RK3328_CLKGATE_CON(28), 2, GFLAGS),
|
||||
GATE(PCLK_USB3_GRF, "pclk_usb3_grf", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 2, GFLAGS),
|
||||
GATE(PCLK_USB2_GRF, "pclk_usb2_grf", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 14, GFLAGS),
|
||||
GATE(0, "pclk_ddrphy", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 13, GFLAGS),
|
||||
GATE(0, "pclk_acodecphy", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 5, GFLAGS),
|
||||
GATE(PCLK_HDMIPHY, "pclk_hdmiphy", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 7, GFLAGS),
|
||||
GATE(0, "pclk_vdacphy", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 8, GFLAGS),
|
||||
GATE(0, "pclk_phy_niu", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(15), 15, GFLAGS),
|
||||
|
||||
/* PD_MMC */
|
||||
MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc",
|
||||
RK3328_SDMMC_CON0, 1),
|
||||
MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc",
|
||||
RK3328_SDMMC_CON1, 1),
|
||||
|
||||
MMC(SCLK_SDIO_DRV, "sdio_drv", "sclk_sdio",
|
||||
RK3328_SDIO_CON0, 1),
|
||||
MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "sclk_sdio",
|
||||
RK3328_SDIO_CON1, 1),
|
||||
|
||||
MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc",
|
||||
RK3328_EMMC_CON0, 1),
|
||||
MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc",
|
||||
RK3328_EMMC_CON1, 1),
|
||||
|
||||
MMC(SCLK_SDMMC_EXT_DRV, "sdmmc_ext_drv", "sclk_sdmmc_ext",
|
||||
RK3328_SDMMC_EXT_CON0, 1),
|
||||
MMC(SCLK_SDMMC_EXT_SAMPLE, "sdmmc_ext_sample", "sclk_sdmmc_ext",
|
||||
RK3328_SDMMC_EXT_CON1, 1),
|
||||
};
|
||||
|
||||
static const char *const rk3328_critical_clocks[] __initconst = {
|
||||
"aclk_bus",
|
||||
"pclk_bus",
|
||||
"hclk_bus",
|
||||
"aclk_peri",
|
||||
"hclk_peri",
|
||||
"pclk_peri",
|
||||
"pclk_dbg",
|
||||
"aclk_core_niu",
|
||||
"aclk_gic400",
|
||||
"aclk_intmem",
|
||||
"hclk_rom",
|
||||
"pclk_grf",
|
||||
"pclk_cru",
|
||||
"pclk_sgrf",
|
||||
"pclk_timer0",
|
||||
"clk_timer0",
|
||||
"pclk_ddr_msch",
|
||||
"pclk_ddr_mon",
|
||||
"pclk_ddr_grf",
|
||||
"clk_ddrupctl",
|
||||
"clk_ddrmsch",
|
||||
"hclk_ahb1tom",
|
||||
"clk_jtag",
|
||||
"pclk_ddrphy",
|
||||
"pclk_pmu",
|
||||
"hclk_otg_pmu",
|
||||
"aclk_rga_niu",
|
||||
"pclk_vio_h2p",
|
||||
"hclk_vio_h2p",
|
||||
};
|
||||
|
||||
static void __init rk3328_clk_init(struct device_node *np)
|
||||
{
|
||||
struct rockchip_clk_provider *ctx;
|
||||
void __iomem *reg_base;
|
||||
|
||||
reg_base = of_iomap(np, 0);
|
||||
if (!reg_base) {
|
||||
pr_err("%s: could not map cru region\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
|
||||
if (IS_ERR(ctx)) {
|
||||
pr_err("%s: rockchip clk init failed\n", __func__);
|
||||
iounmap(reg_base);
|
||||
return;
|
||||
}
|
||||
|
||||
rockchip_clk_register_plls(ctx, rk3328_pll_clks,
|
||||
ARRAY_SIZE(rk3328_pll_clks),
|
||||
RK3328_GRF_SOC_STATUS0);
|
||||
rockchip_clk_register_branches(ctx, rk3328_clk_branches,
|
||||
ARRAY_SIZE(rk3328_clk_branches));
|
||||
rockchip_clk_protect_critical(rk3328_critical_clocks,
|
||||
ARRAY_SIZE(rk3328_critical_clocks));
|
||||
|
||||
rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
|
||||
mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
|
||||
&rk3328_cpuclk_data, rk3328_cpuclk_rates,
|
||||
ARRAY_SIZE(rk3328_cpuclk_rates));
|
||||
|
||||
rockchip_register_softrst(np, 11, reg_base + RK3328_SOFTRST_CON(0),
|
||||
ROCKCHIP_SOFTRST_HIWORD_MASK);
|
||||
|
||||
rockchip_register_restart_notifier(ctx, RK3328_GLB_SRST_FST, NULL);
|
||||
|
||||
rockchip_clk_of_add_provider(np, ctx);
|
||||
}
|
||||
CLK_OF_DECLARE(rk3328_cru, "rockchip,rk3328-cru", rk3328_clk_init);
|
||||
|
|
@ -344,7 +344,6 @@ struct rockchip_clk_provider * __init rockchip_clk_init(struct device_node *np,
|
|||
ctx->clk_data.clks = clk_table;
|
||||
ctx->clk_data.clk_num = nr_clks;
|
||||
ctx->cru_node = np;
|
||||
ctx->grf = ERR_PTR(-EPROBE_DEFER);
|
||||
spin_lock_init(&ctx->lock);
|
||||
|
||||
ctx->grf = syscon_regmap_lookup_by_phandle(ctx->cru_node,
|
||||
|
|
@ -417,6 +416,13 @@ void __init rockchip_clk_register_branches(
|
|||
list->mux_shift, list->mux_width,
|
||||
list->mux_flags, &ctx->lock);
|
||||
break;
|
||||
case branch_muxgrf:
|
||||
clk = rockchip_clk_register_muxgrf(list->name,
|
||||
list->parent_names, list->num_parents,
|
||||
flags, ctx->grf, list->muxdiv_offset,
|
||||
list->mux_shift, list->mux_width,
|
||||
list->mux_flags);
|
||||
break;
|
||||
case branch_divider:
|
||||
if (list->div_table)
|
||||
clk = clk_register_divider_table(NULL,
|
||||
|
|
|
|||
|
|
@ -91,6 +91,24 @@ struct clk;
|
|||
#define RK3288_EMMC_CON0 0x218
|
||||
#define RK3288_EMMC_CON1 0x21c
|
||||
|
||||
#define RK3328_PLL_CON(x) RK2928_PLL_CON(x)
|
||||
#define RK3328_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
|
||||
#define RK3328_CLKGATE_CON(x) ((x) * 0x4 + 0x200)
|
||||
#define RK3328_GRFCLKSEL_CON(x) ((x) * 0x4 + 0x100)
|
||||
#define RK3328_GLB_SRST_FST 0x9c
|
||||
#define RK3328_GLB_SRST_SND 0x98
|
||||
#define RK3328_SOFTRST_CON(x) ((x) * 0x4 + 0x300)
|
||||
#define RK3328_MODE_CON 0x80
|
||||
#define RK3328_MISC_CON 0x84
|
||||
#define RK3328_SDMMC_CON0 0x380
|
||||
#define RK3328_SDMMC_CON1 0x384
|
||||
#define RK3328_SDIO_CON0 0x388
|
||||
#define RK3328_SDIO_CON1 0x38c
|
||||
#define RK3328_EMMC_CON0 0x390
|
||||
#define RK3328_EMMC_CON1 0x394
|
||||
#define RK3328_SDMMC_EXT_CON0 0x398
|
||||
#define RK3328_SDMMC_EXT_CON1 0x39C
|
||||
|
||||
#define RK3368_PLL_CON(x) RK2928_PLL_CON(x)
|
||||
#define RK3368_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
|
||||
#define RK3368_CLKGATE_CON(x) ((x) * 0x4 + 0x200)
|
||||
|
|
@ -130,6 +148,7 @@ struct clk;
|
|||
enum rockchip_pll_type {
|
||||
pll_rk3036,
|
||||
pll_rk3066,
|
||||
pll_rk3328,
|
||||
pll_rk3399,
|
||||
};
|
||||
|
||||
|
|
@ -317,11 +336,17 @@ struct clk *rockchip_clk_register_inverter(const char *name,
|
|||
void __iomem *reg, int shift, int flags,
|
||||
spinlock_t *lock);
|
||||
|
||||
struct clk *rockchip_clk_register_muxgrf(const char *name,
|
||||
const char *const *parent_names, u8 num_parents,
|
||||
int flags, struct regmap *grf, int reg,
|
||||
int shift, int width, int mux_flags);
|
||||
|
||||
#define PNAME(x) static const char *const x[] __initconst
|
||||
|
||||
enum rockchip_clk_branch_type {
|
||||
branch_composite,
|
||||
branch_mux,
|
||||
branch_muxgrf,
|
||||
branch_divider,
|
||||
branch_fraction_divider,
|
||||
branch_gate,
|
||||
|
|
@ -551,6 +576,21 @@ struct rockchip_clk_branch {
|
|||
.gate_offset = -1, \
|
||||
}
|
||||
|
||||
#define MUXGRF(_id, cname, pnames, f, o, s, w, mf) \
|
||||
{ \
|
||||
.id = _id, \
|
||||
.branch_type = branch_muxgrf, \
|
||||
.name = cname, \
|
||||
.parent_names = pnames, \
|
||||
.num_parents = ARRAY_SIZE(pnames), \
|
||||
.flags = f, \
|
||||
.muxdiv_offset = o, \
|
||||
.mux_shift = s, \
|
||||
.mux_width = w, \
|
||||
.mux_flags = mf, \
|
||||
.gate_offset = -1, \
|
||||
}
|
||||
|
||||
#define DIV(_id, cname, pname, f, o, s, w, df) \
|
||||
{ \
|
||||
.id = _id, \
|
||||
|
|
|
|||
|
|
@ -108,6 +108,8 @@
|
|||
#define PCLK_TSADC 349
|
||||
#define PCLK_CPU 350
|
||||
#define PCLK_PERI 351
|
||||
#define PCLK_DDRUPCTL 352
|
||||
#define PCLK_PUBL 353
|
||||
|
||||
/* hclk gates */
|
||||
#define HCLK_SDMMC 448
|
||||
|
|
|
|||
|
|
@ -168,6 +168,7 @@
|
|||
#define PCLK_WDT 368
|
||||
#define PCLK_EFUSE256 369
|
||||
#define PCLK_EFUSE1024 370
|
||||
#define PCLK_ISP_IN 371
|
||||
|
||||
/* hclk gates */
|
||||
#define HCLK_GPS 448
|
||||
|
|
|
|||
|
|
@ -0,0 +1,400 @@
|
|||
/*
|
||||
* Copyright (c) 2016 Rockchip Electronics Co. Ltd.
|
||||
* Author: Elaine <zhangqing@rock-chips.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H
|
||||
#define _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H
|
||||
|
||||
/* core clocks */
|
||||
#define PLL_APLL 1
|
||||
#define PLL_DPLL 2
|
||||
#define PLL_CPLL 3
|
||||
#define PLL_GPLL 4
|
||||
#define PLL_NPLL 5
|
||||
#define ARMCLK 6
|
||||
|
||||
/* sclk gates (special clocks) */
|
||||
#define SCLK_RTC32K 30
|
||||
#define SCLK_SDMMC_EXT 31
|
||||
#define SCLK_SPI 32
|
||||
#define SCLK_SDMMC 33
|
||||
#define SCLK_SDIO 34
|
||||
#define SCLK_EMMC 35
|
||||
#define SCLK_TSADC 36
|
||||
#define SCLK_SARADC 37
|
||||
#define SCLK_UART0 38
|
||||
#define SCLK_UART1 39
|
||||
#define SCLK_UART2 40
|
||||
#define SCLK_I2S0 41
|
||||
#define SCLK_I2S1 42
|
||||
#define SCLK_I2S2 43
|
||||
#define SCLK_I2S1_OUT 44
|
||||
#define SCLK_I2S2_OUT 45
|
||||
#define SCLK_SPDIF 46
|
||||
#define SCLK_TIMER0 47
|
||||
#define SCLK_TIMER1 48
|
||||
#define SCLK_TIMER2 49
|
||||
#define SCLK_TIMER3 50
|
||||
#define SCLK_TIMER4 51
|
||||
#define SCLK_TIMER5 52
|
||||
#define SCLK_WIFI 53
|
||||
#define SCLK_CIF_OUT 54
|
||||
#define SCLK_I2C0 55
|
||||
#define SCLK_I2C1 56
|
||||
#define SCLK_I2C2 57
|
||||
#define SCLK_I2C3 58
|
||||
#define SCLK_CRYPTO 59
|
||||
#define SCLK_PWM 60
|
||||
#define SCLK_PDM 61
|
||||
#define SCLK_EFUSE 62
|
||||
#define SCLK_OTP 63
|
||||
#define SCLK_DDRCLK 64
|
||||
#define SCLK_VDEC_CABAC 65
|
||||
#define SCLK_VDEC_CORE 66
|
||||
#define SCLK_VENC_DSP 67
|
||||
#define SCLK_VENC_CORE 68
|
||||
#define SCLK_RGA 69
|
||||
#define SCLK_HDMI_SFC 70
|
||||
#define SCLK_HDMI_CEC 71
|
||||
#define SCLK_USB3_REF 72
|
||||
#define SCLK_USB3_SUSPEND 73
|
||||
#define SCLK_SDMMC_DRV 74
|
||||
#define SCLK_SDIO_DRV 75
|
||||
#define SCLK_EMMC_DRV 76
|
||||
#define SCLK_SDMMC_EXT_DRV 77
|
||||
#define SCLK_SDMMC_SAMPLE 78
|
||||
#define SCLK_SDIO_SAMPLE 79
|
||||
#define SCLK_EMMC_SAMPLE 80
|
||||
#define SCLK_SDMMC_EXT_SAMPLE 81
|
||||
#define SCLK_VOP 82
|
||||
#define SCLK_MAC2PHY_RXTX 83
|
||||
#define SCLK_MAC2PHY_SRC 84
|
||||
#define SCLK_MAC2PHY_REF 85
|
||||
#define SCLK_MAC2PHY_OUT 86
|
||||
#define SCLK_MAC2IO_RX 87
|
||||
#define SCLK_MAC2IO_TX 88
|
||||
#define SCLK_MAC2IO_REFOUT 89
|
||||
#define SCLK_MAC2IO_REF 90
|
||||
#define SCLK_MAC2IO_OUT 91
|
||||
#define SCLK_TSP 92
|
||||
#define SCLK_HSADC_TSP 93
|
||||
#define SCLK_USB3PHY_REF 94
|
||||
#define SCLK_REF_USB3OTG 95
|
||||
#define SCLK_USB3OTG_REF 96
|
||||
#define SCLK_USB3OTG_SUSPEND 97
|
||||
#define SCLK_REF_USB3OTG_SRC 98
|
||||
#define SCLK_MAC2IO_SRC 99
|
||||
#define SCLK_MAC2IO 100
|
||||
#define SCLK_MAC2PHY 101
|
||||
|
||||
/* dclk gates */
|
||||
#define DCLK_LCDC 120
|
||||
#define DCLK_HDMIPHY 121
|
||||
#define HDMIPHY 122
|
||||
#define USB480M 123
|
||||
#define DCLK_LCDC_SRC 124
|
||||
|
||||
/* aclk gates */
|
||||
#define ACLK_AXISRAM 130
|
||||
#define ACLK_VOP_PRE 131
|
||||
#define ACLK_USB3OTG 132
|
||||
#define ACLK_RGA_PRE 133
|
||||
#define ACLK_DMAC 134
|
||||
#define ACLK_GPU 135
|
||||
#define ACLK_BUS_PRE 136
|
||||
#define ACLK_PERI_PRE 137
|
||||
#define ACLK_RKVDEC_PRE 138
|
||||
#define ACLK_RKVDEC 139
|
||||
#define ACLK_RKVENC 140
|
||||
#define ACLK_VPU_PRE 141
|
||||
#define ACLK_VIO_PRE 142
|
||||
#define ACLK_VPU 143
|
||||
#define ACLK_VIO 144
|
||||
#define ACLK_VOP 145
|
||||
#define ACLK_GMAC 146
|
||||
#define ACLK_H265 147
|
||||
#define ACLK_H264 148
|
||||
#define ACLK_MAC2PHY 149
|
||||
#define ACLK_MAC2IO 150
|
||||
#define ACLK_DCF 151
|
||||
#define ACLK_TSP 152
|
||||
#define ACLK_PERI 153
|
||||
#define ACLK_RGA 154
|
||||
#define ACLK_IEP 155
|
||||
#define ACLK_CIF 156
|
||||
#define ACLK_HDCP 157
|
||||
|
||||
/* pclk gates */
|
||||
#define PCLK_GPIO0 200
|
||||
#define PCLK_GPIO1 201
|
||||
#define PCLK_GPIO2 202
|
||||
#define PCLK_GPIO3 203
|
||||
#define PCLK_GRF 204
|
||||
#define PCLK_I2C0 205
|
||||
#define PCLK_I2C1 206
|
||||
#define PCLK_I2C2 207
|
||||
#define PCLK_I2C3 208
|
||||
#define PCLK_SPI 209
|
||||
#define PCLK_UART0 210
|
||||
#define PCLK_UART1 211
|
||||
#define PCLK_UART2 212
|
||||
#define PCLK_TSADC 213
|
||||
#define PCLK_PWM 214
|
||||
#define PCLK_TIMER 215
|
||||
#define PCLK_BUS_PRE 216
|
||||
#define PCLK_PERI_PRE 217
|
||||
#define PCLK_HDMI_CTRL 218
|
||||
#define PCLK_HDMI_PHY 219
|
||||
#define PCLK_GMAC 220
|
||||
#define PCLK_H265 221
|
||||
#define PCLK_MAC2PHY 222
|
||||
#define PCLK_MAC2IO 223
|
||||
#define PCLK_USB3PHY_OTG 224
|
||||
#define PCLK_USB3PHY_PIPE 225
|
||||
#define PCLK_USB3_GRF 226
|
||||
#define PCLK_USB2_GRF 227
|
||||
#define PCLK_HDMIPHY 228
|
||||
#define PCLK_DDR 229
|
||||
#define PCLK_PERI 230
|
||||
#define PCLK_HDMI 231
|
||||
#define PCLK_HDCP 232
|
||||
#define PCLK_DCF 233
|
||||
#define PCLK_SARADC 234
|
||||
|
||||
/* hclk gates */
|
||||
#define HCLK_PERI 308
|
||||
#define HCLK_TSP 309
|
||||
#define HCLK_GMAC 310
|
||||
#define HCLK_I2S0_8CH 311
|
||||
#define HCLK_I2S1_8CH 313
|
||||
#define HCLK_I2S2_2CH 313
|
||||
#define HCLK_SPDIF_8CH 314
|
||||
#define HCLK_VOP 315
|
||||
#define HCLK_NANDC 316
|
||||
#define HCLK_SDMMC 317
|
||||
#define HCLK_SDIO 318
|
||||
#define HCLK_EMMC 319
|
||||
#define HCLK_SDMMC_EXT 320
|
||||
#define HCLK_RKVDEC_PRE 321
|
||||
#define HCLK_RKVDEC 322
|
||||
#define HCLK_RKVENC 323
|
||||
#define HCLK_VPU_PRE 324
|
||||
#define HCLK_VIO_PRE 325
|
||||
#define HCLK_VPU 326
|
||||
#define HCLK_VIO 327
|
||||
#define HCLK_BUS_PRE 328
|
||||
#define HCLK_PERI_PRE 329
|
||||
#define HCLK_H264 330
|
||||
#define HCLK_CIF 331
|
||||
#define HCLK_OTG_PMU 332
|
||||
#define HCLK_OTG 333
|
||||
#define HCLK_HOST0 334
|
||||
#define HCLK_HOST0_ARB 335
|
||||
#define HCLK_CRYPTO_MST 336
|
||||
#define HCLK_CRYPTO_SLV 337
|
||||
#define HCLK_PDM 338
|
||||
#define HCLK_IEP 339
|
||||
#define HCLK_RGA 340
|
||||
#define HCLK_HDCP 341
|
||||
|
||||
#define CLK_NR_CLKS (HCLK_HDCP + 1)
|
||||
|
||||
/* soft-reset indices */
|
||||
#define SRST_CORE0_PO 0
|
||||
#define SRST_CORE1_PO 1
|
||||
#define SRST_CORE2_PO 2
|
||||
#define SRST_CORE3_PO 3
|
||||
#define SRST_CORE0 4
|
||||
#define SRST_CORE1 5
|
||||
#define SRST_CORE2 6
|
||||
#define SRST_CORE3 7
|
||||
#define SRST_CORE0_DBG 8
|
||||
#define SRST_CORE1_DBG 9
|
||||
#define SRST_CORE2_DBG 10
|
||||
#define SRST_CORE3_DBG 11
|
||||
#define SRST_TOPDBG 12
|
||||
#define SRST_CORE_NIU 13
|
||||
#define SRST_STRC_A 14
|
||||
#define SRST_L2C 15
|
||||
|
||||
#define SRST_A53_GIC 18
|
||||
#define SRST_DAP 19
|
||||
#define SRST_PMU_P 21
|
||||
#define SRST_EFUSE 22
|
||||
#define SRST_BUSSYS_H 23
|
||||
#define SRST_BUSSYS_P 24
|
||||
#define SRST_SPDIF 25
|
||||
#define SRST_INTMEM 26
|
||||
#define SRST_ROM 27
|
||||
#define SRST_GPIO0 28
|
||||
#define SRST_GPIO1 29
|
||||
#define SRST_GPIO2 30
|
||||
#define SRST_GPIO3 31
|
||||
|
||||
#define SRST_I2S0 32
|
||||
#define SRST_I2S1 33
|
||||
#define SRST_I2S2 34
|
||||
#define SRST_I2S0_H 35
|
||||
#define SRST_I2S1_H 36
|
||||
#define SRST_I2S2_H 37
|
||||
#define SRST_UART0 38
|
||||
#define SRST_UART1 39
|
||||
#define SRST_UART2 40
|
||||
#define SRST_UART0_P 41
|
||||
#define SRST_UART1_P 42
|
||||
#define SRST_UART2_P 43
|
||||
#define SRST_I2C0 44
|
||||
#define SRST_I2C1 45
|
||||
#define SRST_I2C2 46
|
||||
#define SRST_I2C3 47
|
||||
|
||||
#define SRST_I2C0_P 48
|
||||
#define SRST_I2C1_P 49
|
||||
#define SRST_I2C2_P 50
|
||||
#define SRST_I2C3_P 51
|
||||
#define SRST_EFUSE_SE_P 52
|
||||
#define SRST_EFUSE_NS_P 53
|
||||
#define SRST_PWM0 54
|
||||
#define SRST_PWM0_P 55
|
||||
#define SRST_DMA 56
|
||||
#define SRST_TSP_A 57
|
||||
#define SRST_TSP_H 58
|
||||
#define SRST_TSP 59
|
||||
#define SRST_TSP_HSADC 60
|
||||
#define SRST_DCF_A 61
|
||||
#define SRST_DCF_P 62
|
||||
|
||||
#define SRST_SCR 64
|
||||
#define SRST_SPI 65
|
||||
#define SRST_TSADC 66
|
||||
#define SRST_TSADC_P 67
|
||||
#define SRST_CRYPTO 68
|
||||
#define SRST_SGRF 69
|
||||
#define SRST_GRF 70
|
||||
#define SRST_USB_GRF 71
|
||||
#define SRST_TIMER_6CH_P 72
|
||||
#define SRST_TIMER0 73
|
||||
#define SRST_TIMER1 74
|
||||
#define SRST_TIMER2 75
|
||||
#define SRST_TIMER3 76
|
||||
#define SRST_TIMER4 77
|
||||
#define SRST_TIMER5 78
|
||||
#define SRST_USB3GRF 79
|
||||
|
||||
#define SRST_PHYNIU 80
|
||||
#define SRST_HDMIPHY 81
|
||||
#define SRST_VDAC 82
|
||||
#define SRST_ACODEC_p 83
|
||||
#define SRST_SARADC 85
|
||||
#define SRST_SARADC_P 86
|
||||
#define SRST_GRF_DDR 87
|
||||
#define SRST_DFIMON 88
|
||||
#define SRST_MSCH 89
|
||||
#define SRST_DDRMSCH 91
|
||||
#define SRST_DDRCTRL 92
|
||||
#define SRST_DDRCTRL_P 93
|
||||
#define SRST_DDRPHY 94
|
||||
#define SRST_DDRPHY_P 95
|
||||
|
||||
#define SRST_GMAC_NIU_A 96
|
||||
#define SRST_GMAC_NIU_P 97
|
||||
#define SRST_GMAC2PHY_A 98
|
||||
#define SRST_GMAC2IO_A 99
|
||||
#define SRST_MACPHY 100
|
||||
#define SRST_OTP_PHY 101
|
||||
#define SRST_GPU_A 102
|
||||
#define SRST_GPU_NIU_A 103
|
||||
#define SRST_SDMMCEXT 104
|
||||
#define SRST_PERIPH_NIU_A 105
|
||||
#define SRST_PERIHP_NIU_H 106
|
||||
#define SRST_PERIHP_P 107
|
||||
#define SRST_PERIPHSYS_H 108
|
||||
#define SRST_MMC0 109
|
||||
#define SRST_SDIO 110
|
||||
#define SRST_EMMC 111
|
||||
|
||||
#define SRST_USB2OTG_H 112
|
||||
#define SRST_USB2OTG 113
|
||||
#define SRST_USB2OTG_ADP 114
|
||||
#define SRST_USB2HOST_H 115
|
||||
#define SRST_USB2HOST_ARB 116
|
||||
#define SRST_USB2HOST_AUX 117
|
||||
#define SRST_USB2HOST_EHCIPHY 118
|
||||
#define SRST_USB2HOST_UTMI 119
|
||||
#define SRST_USB3OTG 120
|
||||
#define SRST_USBPOR 121
|
||||
#define SRST_USB2OTG_UTMI 122
|
||||
#define SRST_USB2HOST_PHY_UTMI 123
|
||||
#define SRST_USB3OTG_UTMI 124
|
||||
#define SRST_USB3PHY_U2 125
|
||||
#define SRST_USB3PHY_U3 126
|
||||
#define SRST_USB3PHY_PIPE 127
|
||||
|
||||
#define SRST_VIO_A 128
|
||||
#define SRST_VIO_BUS_H 129
|
||||
#define SRST_VIO_H2P_H 130
|
||||
#define SRST_VIO_ARBI_H 131
|
||||
#define SRST_VOP_NIU_A 132
|
||||
#define SRST_VOP_A 133
|
||||
#define SRST_VOP_H 134
|
||||
#define SRST_VOP_D 135
|
||||
#define SRST_RGA 136
|
||||
#define SRST_RGA_NIU_A 137
|
||||
#define SRST_RGA_A 138
|
||||
#define SRST_RGA_H 139
|
||||
#define SRST_IEP_A 140
|
||||
#define SRST_IEP_H 141
|
||||
#define SRST_HDMI 142
|
||||
#define SRST_HDMI_P 143
|
||||
|
||||
#define SRST_HDCP_A 144
|
||||
#define SRST_HDCP 145
|
||||
#define SRST_HDCP_H 146
|
||||
#define SRST_CIF_A 147
|
||||
#define SRST_CIF_H 148
|
||||
#define SRST_CIF_P 149
|
||||
#define SRST_OTP_P 150
|
||||
#define SRST_OTP_SBPI 151
|
||||
#define SRST_OTP_USER 152
|
||||
#define SRST_DDRCTRL_A 153
|
||||
#define SRST_DDRSTDY_P 154
|
||||
#define SRST_DDRSTDY 155
|
||||
#define SRST_PDM_H 156
|
||||
#define SRST_PDM 157
|
||||
#define SRST_USB3PHY_OTG_P 158
|
||||
#define SRST_USB3PHY_PIPE_P 159
|
||||
|
||||
#define SRST_VCODEC_A 160
|
||||
#define SRST_VCODEC_NIU_A 161
|
||||
#define SRST_VCODEC_H 162
|
||||
#define SRST_VCODEC_NIU_H 163
|
||||
#define SRST_VDEC_A 164
|
||||
#define SRST_VDEC_NIU_A 165
|
||||
#define SRST_VDEC_H 166
|
||||
#define SRST_VDEC_NIU_H 167
|
||||
#define SRST_VDEC_CORE 168
|
||||
#define SRST_VDEC_CABAC 169
|
||||
#define SRST_DDRPHYDIV 175
|
||||
|
||||
#define SRST_RKVENC_NIU_A 176
|
||||
#define SRST_RKVENC_NIU_H 177
|
||||
#define SRST_RKVENC_H265_A 178
|
||||
#define SRST_RKVENC_H265_P 179
|
||||
#define SRST_RKVENC_H265_CORE 180
|
||||
#define SRST_RKVENC_H265_DSP 181
|
||||
#define SRST_RKVENC_H264_A 182
|
||||
#define SRST_RKVENC_H264_H 183
|
||||
#define SRST_RKVENC_INTMEM 184
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue