From 06d058e1a008e202addc3bff9ab025fbcb23040f Mon Sep 17 00:00:00 2001 From: Dhinakaran Pandiyan Date: Mon, 26 Feb 2018 19:27:23 -0800 Subject: [PATCH] drm/i915/psr: Check for power state control capability. eDP spec says - "If PSR/PSR2 is supported, the SET_POWER_CAPABLE bit in the EDP_GENERAL_CAPABILITY_1 register (DPCD Address 00701h, bit d7) must be set to 1." Reject PSR on panels without this cap bit set as such panels cannot be controlled via SET_POWER & SET_DP_PWR_VOLTAGE register and the DP source needs to be able to do that for PSR. Thanks to Nathan for debugging this. Panel cap checks like this can be done just once, let's fix this when PSR dpcd init movement lands. Cc: Nathan D Ciobanu Cc: Rodrigo Vivi Signed-off-by: Dhinakaran Pandiyan Tested-by: Nathan Ciobanu Reviewed-by: Rodrigo Vivi Signed-off-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/20180227032723.15474-1-dhinakaran.pandiyan@intel.com --- drivers/gpu/drm/i915/intel_psr.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index b7cc6dd45c9e..1f77633fe809 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -508,6 +508,11 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, return; } + if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) { + DRM_DEBUG_KMS("PSR condition failed: panel lacks power state control\n"); + return; + } + /* * FIXME psr2_support is messed up. It's both computed * dynamically during PSR enable, and extracted from sink