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net: mdio-ipq4019: add Clause 45 support
While up-streaming the IPQ4019 driver it was thought that the controller had no Clause 45 support, but it actually does and its activated by writing a bit to the mode register. So lets add it as newer SoC-s use the same controller and Clause 45 compliant PHY-s. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -12,6 +12,7 @@
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#include <linux/phy.h>
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#include <linux/platform_device.h>
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#define MDIO_MODE_REG 0x40
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#define MDIO_ADDR_REG 0x44
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#define MDIO_DATA_WRITE_REG 0x48
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#define MDIO_DATA_READ_REG 0x4c
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@ -20,6 +21,12 @@
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#define MDIO_CMD_ACCESS_START BIT(8)
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#define MDIO_CMD_ACCESS_CODE_READ 0
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#define MDIO_CMD_ACCESS_CODE_WRITE 1
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#define MDIO_CMD_ACCESS_CODE_C45_ADDR 0
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#define MDIO_CMD_ACCESS_CODE_C45_WRITE 1
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#define MDIO_CMD_ACCESS_CODE_C45_READ 2
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/* 0 = Clause 22, 1 = Clause 45 */
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#define MDIO_MODE_C45 BIT(8)
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#define IPQ4019_MDIO_TIMEOUT 10000
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#define IPQ4019_MDIO_SLEEP 10
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@ -41,19 +48,44 @@ static int ipq4019_mdio_wait_busy(struct mii_bus *bus)
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static int ipq4019_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
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{
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struct ipq4019_mdio_data *priv = bus->priv;
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unsigned int data;
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unsigned int cmd;
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/* Reject clause 45 */
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if (regnum & MII_ADDR_C45)
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return -EOPNOTSUPP;
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if (ipq4019_mdio_wait_busy(bus))
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return -ETIMEDOUT;
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/* issue the phy address and reg */
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writel((mii_id << 8) | regnum, priv->membase + MDIO_ADDR_REG);
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/* Clause 45 support */
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if (regnum & MII_ADDR_C45) {
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unsigned int mmd = (regnum >> 16) & 0x1F;
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unsigned int reg = regnum & 0xFFFF;
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cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_READ;
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/* Enter Clause 45 mode */
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data = readl(priv->membase + MDIO_MODE_REG);
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data |= MDIO_MODE_C45;
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writel(data, priv->membase + MDIO_MODE_REG);
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/* issue the phy address and mmd */
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writel((mii_id << 8) | mmd, priv->membase + MDIO_ADDR_REG);
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/* issue reg */
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writel(reg, priv->membase + MDIO_DATA_WRITE_REG);
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cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_C45_ADDR;
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} else {
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/* Enter Clause 22 mode */
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data = readl(priv->membase + MDIO_MODE_REG);
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data &= ~MDIO_MODE_C45;
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writel(data, priv->membase + MDIO_MODE_REG);
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/* issue the phy address and reg */
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writel((mii_id << 8) | regnum, priv->membase + MDIO_ADDR_REG);
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cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_READ;
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}
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/* issue read command */
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writel(cmd, priv->membase + MDIO_CMD_REG);
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@ -62,6 +94,15 @@ static int ipq4019_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
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if (ipq4019_mdio_wait_busy(bus))
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return -ETIMEDOUT;
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if (regnum & MII_ADDR_C45) {
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cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_C45_READ;
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writel(cmd, priv->membase + MDIO_CMD_REG);
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if (ipq4019_mdio_wait_busy(bus))
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return -ETIMEDOUT;
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}
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/* Read and return data */
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return readl(priv->membase + MDIO_DATA_READ_REG);
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}
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@ -70,23 +111,57 @@ static int ipq4019_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
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u16 value)
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{
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struct ipq4019_mdio_data *priv = bus->priv;
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unsigned int data;
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unsigned int cmd;
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/* Reject clause 45 */
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if (regnum & MII_ADDR_C45)
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return -EOPNOTSUPP;
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if (ipq4019_mdio_wait_busy(bus))
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return -ETIMEDOUT;
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/* issue the phy address and reg */
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writel((mii_id << 8) | regnum, priv->membase + MDIO_ADDR_REG);
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/* Clause 45 support */
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if (regnum & MII_ADDR_C45) {
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unsigned int mmd = (regnum >> 16) & 0x1F;
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unsigned int reg = regnum & 0xFFFF;
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/* Enter Clause 45 mode */
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data = readl(priv->membase + MDIO_MODE_REG);
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data |= MDIO_MODE_C45;
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writel(data, priv->membase + MDIO_MODE_REG);
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/* issue the phy address and mmd */
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writel((mii_id << 8) | mmd, priv->membase + MDIO_ADDR_REG);
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/* issue reg */
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writel(reg, priv->membase + MDIO_DATA_WRITE_REG);
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cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_C45_ADDR;
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writel(cmd, priv->membase + MDIO_CMD_REG);
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if (ipq4019_mdio_wait_busy(bus))
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return -ETIMEDOUT;
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} else {
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/* Enter Clause 22 mode */
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data = readl(priv->membase + MDIO_MODE_REG);
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data &= ~MDIO_MODE_C45;
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writel(data, priv->membase + MDIO_MODE_REG);
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/* issue the phy address and reg */
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writel((mii_id << 8) | regnum, priv->membase + MDIO_ADDR_REG);
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}
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/* issue write data */
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writel(value, priv->membase + MDIO_DATA_WRITE_REG);
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cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_WRITE;
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/* issue write command */
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if (regnum & MII_ADDR_C45)
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cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_C45_WRITE;
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else
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cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_WRITE;
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writel(cmd, priv->membase + MDIO_CMD_REG);
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/* Wait write complete */
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