From 499c8bf5865926174abb722bbaf1a621c56cc899 Mon Sep 17 00:00:00 2001 From: Denis Carikli Date: Wed, 15 Jan 2014 18:23:26 +0100 Subject: [PATCH 001/105] ARM: dts: mbimxsd35: Add sound support. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Eric Bénard Cc: Grant Likely Cc: Rob Herring Cc: Sascha Hauer Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Denis Carikli Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts b/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts index 1bdec21f4533..71197b926353 100644 --- a/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts +++ b/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts @@ -46,6 +46,14 @@ led1 { linux,default-trigger = "heartbeat"; }; }; + + sound { + compatible = "eukrea,asoc-tlv320"; + eukrea,model = "imx35-eukrea-tlv320aic23"; + ssi-controller = <&ssi1>; + fsl,mux-int-port = <1>; + fsl,mux-ext-port = <4>; + }; }; &audmux { @@ -124,6 +132,7 @@ MX35_PAD_CTS2__UART2_CTS 0x1c5 }; &ssi1 { + codec-handle = <&tlv320aic23>; fsl,mode = "i2s-slave"; status = "okay"; }; From 22970070e027cbbb9b2878f8f7c31d0d7f29e94d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 28 Feb 2014 12:58:41 +0100 Subject: [PATCH 002/105] ARM: dts: imx: Add alias for ethernet controller Add alias for FEC ethernet on i.MX to allow bootloaders (like U-Boot) patch-in the MAC address for FEC using this alias. Signed-off-by: Marek Vasut Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx25.dtsi | 1 + arch/arm/boot/dts/imx27.dtsi | 1 + arch/arm/boot/dts/imx35.dtsi | 1 + arch/arm/boot/dts/imx50.dtsi | 1 + arch/arm/boot/dts/imx51.dtsi | 1 + arch/arm/boot/dts/imx53.dtsi | 1 + arch/arm/boot/dts/imx6qdl.dtsi | 1 + arch/arm/boot/dts/imx6sl.dtsi | 1 + 8 files changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi index ea323f09dc78..413d8f0594cb 100644 --- a/arch/arm/boot/dts/imx25.dtsi +++ b/arch/arm/boot/dts/imx25.dtsi @@ -14,6 +14,7 @@ / { aliases { + ethernet0 = &fec; gpio0 = &gpio1; gpio1 = &gpio2; gpio2 = &gpio3; diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi index 137e010eab35..00cf66c1b8f3 100644 --- a/arch/arm/boot/dts/imx27.dtsi +++ b/arch/arm/boot/dts/imx27.dtsi @@ -16,6 +16,7 @@ / { aliases { + ethernet0 = &fec; gpio0 = &gpio1; gpio1 = &gpio2; gpio2 = &gpio3; diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi index 88b218f8f810..e59ccb4d98e3 100644 --- a/arch/arm/boot/dts/imx35.dtsi +++ b/arch/arm/boot/dts/imx35.dtsi @@ -13,6 +13,7 @@ / { aliases { + ethernet0 = &fec; gpio0 = &gpio1; gpio1 = &gpio2; gpio2 = &gpio3; diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi index 9c89d1ca97c2..6a201cf54366 100644 --- a/arch/arm/boot/dts/imx50.dtsi +++ b/arch/arm/boot/dts/imx50.dtsi @@ -17,6 +17,7 @@ / { aliases { + ethernet0 = &fec; gpio0 = &gpio1; gpio1 = &gpio2; gpio2 = &gpio3; diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 150bb4e2f744..51b86700cd88 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -19,6 +19,7 @@ / { aliases { + ethernet0 = &fec; gpio0 = &gpio1; gpio1 = &gpio2; gpio2 = &gpio3; diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 9c2bff2252d0..04815c66fef4 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -18,6 +18,7 @@ / { aliases { + ethernet0 = &fec; gpio0 = &gpio1; gpio1 = &gpio2; gpio2 = &gpio3; diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index eca0971d4db1..02a6afca7530 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -16,6 +16,7 @@ / { aliases { + ethernet0 = &fec; can0 = &can1; can1 = &can2; gpio0 = &gpio1; diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index d26b099260a3..2d4e5285f3f3 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -14,6 +14,7 @@ / { aliases { + ethernet0 = &fec; gpio0 = &gpio1; gpio1 = &gpio2; gpio2 = &gpio3; From e8e8d621f90204d8293fd52bfdc3e957990cfa8f Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Sun, 2 Mar 2014 13:18:38 +0400 Subject: [PATCH 003/105] ARM: dts: imx27-phytec-phycore-rdk: Add missing pinctrl definition for SPI CS1 This patch adds missing pinctrl definition for SPI chipselect 1. Signed-off-by: Alexander Shiyan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts index df3b2e731835..86510ede7ee2 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts +++ b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts @@ -15,6 +15,7 @@ / { }; &cspi1 { + pinctrl-0 = <&pinctrl_cspi1>, <&pinctrl_cspi1cs1>; fsl,spi-num-chipselects = <2>; cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>, <&gpio4 27 GPIO_ACTIVE_LOW>; @@ -36,6 +37,12 @@ camgpio: pca9536@41 { &iomuxc { imx27_phycore_rdk { + pinctrl_cspi1cs1: cspi1cs1grp { + fsl,pins = < + MX27_PAD_CSPI1_SS1__GPIO4_27 0x0 + >; + }; + pinctrl_i2c1: i2c1grp { /* Add pullup to DATA line */ fsl,pins = < From 2c40568937dbdc726876d22e84e138e3090a8082 Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Sun, 2 Mar 2014 13:18:39 +0400 Subject: [PATCH 004/105] ARM: dts: imx27-phytec-phycore-som: Enable SSI1 This patch adds pin group for Synchronous Serial Interface 1 (SSI1) for PCM-038 module and enables this interface. This change do nothing at the current stage but helps to continue develop sound support. Signed-off-by: Alexander Shiyan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi index cefaa6994623..8e10aeff946e 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi +++ b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi @@ -251,6 +251,15 @@ MX27_PAD_NFWE_B__NFWE_B 0x0 >; }; + pinctrl_ssi1: ssi1grp { + fsl,pins = < + MX27_PAD_SSI1_FS__SSI1_FS 0x0 + MX27_PAD_SSI1_RXDAT__SSI1_RXDAT 0x0 + MX27_PAD_SSI1_TXDAT__SSI1_TXDAT 0x0 + MX27_PAD_SSI1_CLK__SSI1_CLK 0x0 + >; + }; + pinctrl_usbotg: usbotggrp { fsl,pins = < MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0 @@ -279,6 +288,13 @@ &nfc { status = "okay"; }; +&ssi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssi1>; + fsl,mode = "i2s-slave"; + status = "okay"; +}; + &usbotg { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbotg>; From 702bfbef1c98c4ec15b311035ca74e713b68cf07 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Vincent=20Stehl=C3=A9?= Date: Wed, 5 Mar 2014 19:58:39 +0100 Subject: [PATCH 005/105] ARM: dts: imx6qdl-sabresd.dtsi: Add red led MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Make the red gpio led available to the user. This can be toggled with the sysfs for example, or used as a heartbeat or mmc activity light by changing the trigger. Signed-off-by: Vincent Stehlé Cc: Sascha Hauer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index 0d816d3be4b6..7a88d9ae8daa 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -105,6 +105,17 @@ backlight { default-brightness-level = <7>; status = "okay"; }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + red { + gpios = <&gpio1 2 0>; + default-state = "on"; + }; + }; }; &audmux { @@ -422,6 +433,14 @@ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 >; }; }; + + gpio_leds { + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 + >; + }; + }; }; &ldb { From 8617cb0b0fd836b208252b3636fc9861cd48cc0f Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 5 Mar 2014 17:30:35 -0300 Subject: [PATCH 006/105] ARM: dts: imx25-pdk: Sort the dt nodes Keep the dt nodes sorted for better readability. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx25-pdk.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/imx25-pdk.dts index f607ce520eda..88267c5c3ef4 100644 --- a/arch/arm/boot/dts/imx25-pdk.dts +++ b/arch/arm/boot/dts/imx25-pdk.dts @@ -21,10 +21,6 @@ memory { }; }; -&uart1 { - status = "okay"; -}; - &fec { phy-mode = "rmii"; status = "okay"; @@ -34,3 +30,7 @@ &nfc { nand-on-flash-bbt; status = "okay"; }; + +&uart1 { + status = "okay"; +}; From 53ba9c70a48a28054ebfdaad43a6681b570e3380 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 5 Mar 2014 17:30:36 -0300 Subject: [PATCH 007/105] ARM: dts: imx25-pdk: Add UART1 pins UART1 is the console port on mx25pdk board. Add the pin configuration for UART1 port and also pass 'fsl,uart-has-rtscts' to indicate that the port has RTS and CTS pins. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx25-pdk.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/imx25-pdk.dts index 88267c5c3ef4..d6429804cdb2 100644 --- a/arch/arm/boot/dts/imx25-pdk.dts +++ b/arch/arm/boot/dts/imx25-pdk.dts @@ -26,11 +26,27 @@ &fec { status = "okay"; }; +&iomuxc { + imx25-pdk { + pinctrl_uart1: uart1grp { + fsl,pins = < + MX25_PAD_UART1_RTS__UART1_RTS 0xe0 + MX25_PAD_UART1_CTS__UART1_CTS 0xe0 + MX25_PAD_UART1_TXD__UART1_TXD 0x80000000 + MX25_PAD_UART1_RXD__UART1_RXD 0xc0 + >; + }; + }; +}; + &nfc { nand-on-flash-bbt; status = "okay"; }; &uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + fsl,uart-has-rtscts; status = "okay"; }; From f0bd6881e8abc3660bb3e8e6b219ad9a21c88636 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 5 Mar 2014 17:30:37 -0300 Subject: [PATCH 008/105] ARM: dts: imx25-pdk: Add FEC pins Instead of relying on the bootloader for configuring the FEC pins, pass the FEC pin configuration via device tree instead. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx25-pdk.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/imx25-pdk.dts index d6429804cdb2..a97dd7305c46 100644 --- a/arch/arm/boot/dts/imx25-pdk.dts +++ b/arch/arm/boot/dts/imx25-pdk.dts @@ -23,11 +23,27 @@ memory { &fec { phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; status = "okay"; }; &iomuxc { imx25-pdk { + pinctrl_fec: fecgrp { + fsl,pins = < + MX25_PAD_FEC_MDC__FEC_MDC 0x80000000 + MX25_PAD_FEC_MDIO__FEC_MDIO 0x400001e0 + MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000 + MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000 + MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 + MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000 + MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000 + MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000 + MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1c0 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX25_PAD_UART1_RTS__UART1_RTS 0xe0 From 6e3ef2f66489d13e6ee3a26ed7bf9f920f97339b Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 5 Mar 2014 17:30:38 -0300 Subject: [PATCH 009/105] ARM: dts: imx25-pdk: Provide a regulator for Ethernet PHY GPIO2_3 controls the power to the Ethernet PHY, so provide a regulator node for this. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx25-pdk.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/imx25-pdk.dts index a97dd7305c46..d15349e12df9 100644 --- a/arch/arm/boot/dts/imx25-pdk.dts +++ b/arch/arm/boot/dts/imx25-pdk.dts @@ -19,12 +19,29 @@ / { memory { reg = <0x80000000 0x4000000>; }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_fec_3v3: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "fec-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 3 0>; + enable-active-high; + }; + }; }; &fec { phy-mode = "rmii"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec>; + phy-supply = <®_fec_3v3>; status = "okay"; }; @@ -41,6 +58,7 @@ MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000 MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000 MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000 MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1c0 + MX25_PAD_A17__GPIO_2_3 0x80000000 >; }; From c7b15c28250b209b0ef4aef650f8f216ad885448 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 5 Mar 2014 17:30:39 -0300 Subject: [PATCH 010/105] ARM: dts: imx25-pdk: Provide an Ethernet PHY reset GPIO4_8 is connected to the Ethernet PHY reset line, so populate the 'phy-reset-gpios' property accordingly. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx25-pdk.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/imx25-pdk.dts index d15349e12df9..9d14fbc155dc 100644 --- a/arch/arm/boot/dts/imx25-pdk.dts +++ b/arch/arm/boot/dts/imx25-pdk.dts @@ -42,6 +42,7 @@ &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec>; phy-supply = <®_fec_3v3>; + phy-reset-gpios = <&gpio4 8 0>; status = "okay"; }; @@ -59,6 +60,7 @@ MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000 MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000 MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1c0 MX25_PAD_A17__GPIO_2_3 0x80000000 + MX25_PAD_D12__GPIO_4_8 0x80000000 >; }; From 707e6906ee361f2385919e24058036f65655fd75 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 5 Mar 2014 17:30:40 -0300 Subject: [PATCH 011/105] ARM: dts: imx25-pdk: Add esdhc1 support Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx25-pdk.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/imx25-pdk.dts index 9d14fbc155dc..7a6d21fb6e6e 100644 --- a/arch/arm/boot/dts/imx25-pdk.dts +++ b/arch/arm/boot/dts/imx25-pdk.dts @@ -37,6 +37,14 @@ reg_fec_3v3: regulator@0 { }; }; +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + cd-gpios = <&gpio2 1 0>; + wp-gpios = <&gpio2 0 0>; + status = "okay"; +}; + &fec { phy-mode = "rmii"; pinctrl-names = "default"; @@ -48,6 +56,19 @@ &fec { &iomuxc { imx25-pdk { + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX25_PAD_SD1_CMD__SD1_CMD 0x80000000 + MX25_PAD_SD1_CLK__SD1_CLK 0x80000000 + MX25_PAD_SD1_DATA0__SD1_DATA0 0x80000000 + MX25_PAD_SD1_DATA1__SD1_DATA1 0x80000000 + MX25_PAD_SD1_DATA2__SD1_DATA2 0x80000000 + MX25_PAD_SD1_DATA3__SD1_DATA3 0x80000000 + MX25_PAD_A14__GPIO_2_0 0x80000000 + MX25_PAD_A15__GPIO_2_1 0x80000000 + >; + }; + pinctrl_fec: fecgrp { fsl,pins = < MX25_PAD_FEC_MDC__FEC_MDC 0x80000000 From 0517fe6aa8803e06b1e5984e79dbc70d29280899 Mon Sep 17 00:00:00 2001 From: Cosmin Stoica Date: Thu, 6 Mar 2014 18:40:34 +0200 Subject: [PATCH 012/105] ARM: dts: vf610-twr: Add support for sdhc1 The kernel was not able to boot from SD card because sdhc support was not present into the dts. A new entry for sdhc1 was added for vf610-twr board based on the compatible entry present on imx53. After applying these changes, the kernel is able to boot successfully from SD card. Signed-off-by: Cosmin Stoica Signed-off-by: Chircu Bogdan Signed-off-by: Eddy Petrisor Signed-off-by: Shawn Guo --- arch/arm/boot/dts/vf610-twr.dts | 19 +++++++++++++++++++ arch/arm/boot/dts/vf610.dtsi | 11 +++++++++++ 2 files changed, 30 insertions(+) diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts index ded361075aab..a55f803ef9cb 100644 --- a/arch/arm/boot/dts/vf610-twr.dts +++ b/arch/arm/boot/dts/vf610-twr.dts @@ -113,6 +113,13 @@ sflash: at26df081a@0 { }; }; +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + bus-width = <4>; + status = "okay"; +}; + &fec0 { phy-mode = "rmii"; pinctrl-names = "default"; @@ -160,6 +167,18 @@ VF610_PAD_PTB22__DSPI0_SCK 0x1182 >; }; + pinctrl_esdhc1: esdhc1grp { + fsl,fsl,pins = < + VF610_PAD_PTA24__ESDHC1_CLK 0x31ef + VF610_PAD_PTA25__ESDHC1_CMD 0x31ef + VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef + VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef + VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef + VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef + VF610_PAD_PTA7__GPIO_134 0x219d + >; + }; + pinctrl_fec0: fec0grp { fsl,pins = < VF610_PAD_PTA6__RMII_CLKIN 0x30d1 diff --git a/arch/arm/boot/dts/vf610.dtsi b/arch/arm/boot/dts/vf610.dtsi index b8ce0aa7b157..30286bcbe1d0 100644 --- a/arch/arm/boot/dts/vf610.dtsi +++ b/arch/arm/boot/dts/vf610.dtsi @@ -347,6 +347,17 @@ adc1: adc@400bb000 { status = "disabled"; }; + esdhc1: esdhc@400b2000 { + compatible = "fsl,imx53-esdhc"; + reg = <0x400b2000 0x4000>; + interrupts = <0 28 0x04>; + clocks = <&clks VF610_CLK_IPG_BUS>, + <&clks VF610_CLK_PLATFORM_BUS>, + <&clks VF610_CLK_ESDHC1>; + clock-names = "ipg", "ahb", "per"; + status = "disabled"; + }; + fec0: ethernet@400d0000 { compatible = "fsl,mvf600-fec"; reg = <0x400d0000 0x1000>; From 3937f66b9f7e728258d45b98853c7137e88e0cf8 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 13 Mar 2014 10:18:39 +0100 Subject: [PATCH 013/105] ARM: dts: mx25: USB block requires only one clock Like other imx SoCs only one USB clock is needed on mx25. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx25.dtsi | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi index 413d8f0594cb..cc441ec11818 100644 --- a/arch/arm/boot/dts/imx25.dtsi +++ b/arch/arm/boot/dts/imx25.dtsi @@ -497,8 +497,7 @@ usbotg: usb@53ff4000 { compatible = "fsl,imx25-usb", "fsl,imx27-usb"; reg = <0x53ff4000 0x0200>; interrupts = <37>; - clocks = <&clks 9>, <&clks 70>, <&clks 8>; - clock-names = "ipg", "ahb", "per"; + clocks = <&clks 70>; fsl,usbmisc = <&usbmisc 0>; status = "disabled"; }; @@ -507,8 +506,7 @@ usbhost1: usb@53ff4400 { compatible = "fsl,imx25-usb", "fsl,imx27-usb"; reg = <0x53ff4400 0x0200>; interrupts = <35>; - clocks = <&clks 9>, <&clks 70>, <&clks 8>; - clock-names = "ipg", "ahb", "per"; + clocks = <&clks 70>; fsl,usbmisc = <&usbmisc 1>; status = "disabled"; }; From 056c5a598ffdf3812d026365b726b2bbdc28983a Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 13 Mar 2014 10:18:40 +0100 Subject: [PATCH 014/105] ARM: dts: mx35: USB block requires only one clock Like other imx SoCs only one USB clock is needed on mx35. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx35.dtsi | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi index e59ccb4d98e3..474a73d78912 100644 --- a/arch/arm/boot/dts/imx35.dtsi +++ b/arch/arm/boot/dts/imx35.dtsi @@ -296,8 +296,7 @@ usbotg: usb@53ff4000 { compatible = "fsl,imx35-usb", "fsl,imx27-usb"; reg = <0x53ff4000 0x0200>; interrupts = <37>; - clocks = <&clks 9>, <&clks 73>, <&clks 28>; - clock-names = "ipg", "ahb", "per"; + clocks = <&clks 73>; fsl,usbmisc = <&usbmisc 0>; status = "disabled"; }; @@ -306,8 +305,7 @@ usbhost1: usb@53ff4400 { compatible = "fsl,imx35-usb", "fsl,imx27-usb"; reg = <0x53ff4400 0x0200>; interrupts = <35>; - clocks = <&clks 9>, <&clks 73>, <&clks 28>; - clock-names = "ipg", "ahb", "per"; + clocks = <&clks 73>; fsl,usbmisc = <&usbmisc 1>; status = "disabled"; }; From f415153c0ecaae1f4515df35d2c6d055ed97909c Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 13 Mar 2014 10:18:42 +0100 Subject: [PATCH 015/105] ARM: dts: imx25.dtsi: Fix USB support. Signed-off-by: Fabio Estevam Signed-off-by: Denis Carikli Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx25.dtsi | 29 ++++++++++++++++++----------- 1 file changed, 18 insertions(+), 11 deletions(-) diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi index cc441ec11818..9c092571d482 100644 --- a/arch/arm/boot/dts/imx25.dtsi +++ b/arch/arm/boot/dts/imx25.dtsi @@ -483,22 +483,13 @@ iim: iim@53ff0000 { clocks = <&clks 99>; }; - usbphy1: usbphy@1 { - compatible = "nop-usbphy"; - status = "disabled"; - }; - - usbphy2: usbphy@2 { - compatible = "nop-usbphy"; - status = "disabled"; - }; - usbotg: usb@53ff4000 { compatible = "fsl,imx25-usb", "fsl,imx27-usb"; reg = <0x53ff4000 0x0200>; interrupts = <37>; clocks = <&clks 70>; fsl,usbmisc = <&usbmisc 0>; + fsl,usbphy = <&usbphy0>; status = "disabled"; }; @@ -508,6 +499,7 @@ usbhost1: usb@53ff4400 { interrupts = <35>; clocks = <&clks 70>; fsl,usbmisc = <&usbmisc 1>; + fsl,usbphy = <&usbphy1>; status = "disabled"; }; @@ -517,7 +509,6 @@ usbmisc: usbmisc@53ff4600 { clocks = <&clks 9>, <&clks 70>, <&clks 8>; clock-names = "ipg", "ahb", "per"; reg = <0x53ff4600 0x00f>; - status = "disabled"; }; dryice@53ffc000 { @@ -549,4 +540,20 @@ nfc: nand@bb000000 { }; }; }; + + usbphy { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + usbphy0: usb-phy@0 { + reg = <0>; + compatible = "usb-nop-xceiv"; + }; + + usbphy1: usb-phy@1 { + reg = <1>; + compatible = "usb-nop-xceiv"; + }; + }; }; From 3b7af8839b5f7be3c1feaedd5ed9ed893d377429 Mon Sep 17 00:00:00 2001 From: Denis Carikli Date: Thu, 13 Mar 2014 10:18:43 +0100 Subject: [PATCH 016/105] ARM: dts: mbimxsd25 baseboard: Add USB support Signed-off-by: Denis Carikli Signed-off-by: Shawn Guo --- .../boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts index 62fb3da50bdb..ad12da38fc92 100644 --- a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts +++ b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts @@ -172,3 +172,16 @@ &uart2 { fsl,uart-has-rtscts; status = "okay"; }; + +&usbhost1 { + phy_type = "serial"; + dr_mode = "host"; + status = "okay"; +}; + +&usbotg { + phy_type = "utmi"; + dr_mode = "otg"; + external-vbus-divider; + status = "okay"; +}; From ff348251442584135950d64d0b7d53d6e0870611 Mon Sep 17 00:00:00 2001 From: Denis Carikli Date: Thu, 13 Mar 2014 10:18:44 +0100 Subject: [PATCH 017/105] ARM: dts: i.MX35: Add USB support. Signed-off-by: Denis Carikli Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx35.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi index 474a73d78912..4759abb49436 100644 --- a/arch/arm/boot/dts/imx35.dtsi +++ b/arch/arm/boot/dts/imx35.dtsi @@ -298,6 +298,7 @@ usbotg: usb@53ff4000 { interrupts = <37>; clocks = <&clks 73>; fsl,usbmisc = <&usbmisc 0>; + fsl,usbphy = <&usbphy0>; status = "disabled"; }; @@ -307,6 +308,7 @@ usbhost1: usb@53ff4400 { interrupts = <35>; clocks = <&clks 73>; fsl,usbmisc = <&usbmisc 1>; + fsl,usbphy = <&usbphy1>; status = "disabled"; }; @@ -355,4 +357,20 @@ weim: weim@b8002000 { }; }; }; + + usbphy { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + usbphy0: usb-phy@0 { + reg = <0>; + compatible = "usb-nop-xceiv"; + }; + + usbphy1: usb-phy@1 { + reg = <1>; + compatible = "usb-nop-xceiv"; + }; + }; }; From 9afe7d9dadad9aaf3de03fba1bc72ddb69d696af Mon Sep 17 00:00:00 2001 From: Denis Carikli Date: Thu, 13 Mar 2014 10:18:45 +0100 Subject: [PATCH 018/105] ARM: dts: mbimxsd35 baseboard: Add USB support. Signed-off-by: Denis Carikli Signed-off-by: Shawn Guo --- .../boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts b/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts index 71197b926353..f04ae91eea89 100644 --- a/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts +++ b/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts @@ -150,3 +150,16 @@ &uart2 { fsl,uart-has-rtscts; status = "okay"; }; + +&usbhost1 { + phy_type = "serial"; + dr_mode = "host"; + status = "okay"; +}; + +&usbotg { + phy_type = "utmi"; + dr_mode = "otg"; + external-vbus-divider; + status = "okay"; +}; From 35d2bc8c81cb16d0cc1df2ae0d19089bc241447b Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 12 Mar 2014 02:55:47 +0800 Subject: [PATCH 019/105] ARM: dts: imx25-pdk: Add audio support mx25pdk has a sgtl5000 codec connected to the I2C1 port. Add support for it. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx25-pdk.dts | 74 +++++++++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/imx25-pdk.dts index 7a6d21fb6e6e..71743a3f7d76 100644 --- a/arch/arm/boot/dts/imx25-pdk.dts +++ b/arch/arm/boot/dts/imx25-pdk.dts @@ -34,7 +34,44 @@ reg_fec_3v3: regulator@0 { gpio = <&gpio2 3 0>; enable-active-high; }; + + reg_2p5v: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + }; + + reg_3p3v: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + }; + + sound { + compatible = "fsl,imx25-pdk-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "imx25-pdk-sgtl5000"; + ssi-controller = <&ssi1>; + audio-codec = <&codec>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <4>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; }; &esdhc1 { @@ -54,8 +91,32 @@ &fec { status = "okay"; }; +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + codec: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&clks 129>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; +}; + &iomuxc { imx25-pdk { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX25_PAD_RW__AUD4_TXFS 0xe0 + MX25_PAD_OE__AUD4_TXC 0xe0 + MX25_PAD_EB0__AUD4_TXD 0xe0 + MX25_PAD_EB1__AUD4_RXD 0xe0 + >; + }; + pinctrl_esdhc1: esdhc1grp { fsl,pins = < MX25_PAD_SD1_CMD__SD1_CMD 0x80000000 @@ -85,6 +146,13 @@ MX25_PAD_D12__GPIO_4_8 0x80000000 >; }; + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX25_PAD_I2C1_CLK__I2C1_CLK 0x80000000 + MX25_PAD_I2C1_DAT__I2C1_DAT 0x80000000 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX25_PAD_UART1_RTS__UART1_RTS 0xe0 @@ -101,6 +169,12 @@ &nfc { status = "okay"; }; +&ssi1 { + codec-handle = <&codec>; + fsl,mode = "i2s-slave"; + status = "okay"; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; From 9223dd87380322b4af467410170750cf682ffd89 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 12 Mar 2014 10:19:24 -0300 Subject: [PATCH 020/105] ARM: dts: imx25-pdk: Add keypad support Tested with evtest. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx25-pdk.dts | 39 +++++++++++++++++++++++++++++++++ arch/arm/boot/dts/imx25.dtsi | 3 ++- 2 files changed, 41 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/imx25-pdk.dts index 71743a3f7d76..34de5e34814c 100644 --- a/arch/arm/boot/dts/imx25-pdk.dts +++ b/arch/arm/boot/dts/imx25-pdk.dts @@ -10,6 +10,7 @@ */ /dts-v1/; +#include #include "imx25.dtsi" / { @@ -153,6 +154,20 @@ MX25_PAD_I2C1_DAT__I2C1_DAT 0x80000000 >; }; + pinctrl_kpp: kppgrp { + fsl,pins = < + MX25_PAD_KPP_ROW0__KPP_ROW0 0x80000000 + MX25_PAD_KPP_ROW1__KPP_ROW1 0x80000000 + MX25_PAD_KPP_ROW2__KPP_ROW2 0x80000000 + MX25_PAD_KPP_ROW3__KPP_ROW3 0x80000000 + MX25_PAD_KPP_COL0__KPP_COL0 0x80000000 + MX25_PAD_KPP_COL1__KPP_COL1 0x80000000 + MX25_PAD_KPP_COL2__KPP_COL2 0x80000000 + MX25_PAD_KPP_COL3__KPP_COL3 0x80000000 + >; + }; + + pinctrl_uart1: uart1grp { fsl,pins = < MX25_PAD_UART1_RTS__UART1_RTS 0xe0 @@ -169,6 +184,30 @@ &nfc { status = "okay"; }; +&kpp { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_kpp>; + linux,keymap = < + MATRIX_KEY(0x0, 0x0, KEY_UP) + MATRIX_KEY(0x0, 0x1, KEY_DOWN) + MATRIX_KEY(0x0, 0x2, KEY_VOLUMEDOWN) + MATRIX_KEY(0x0, 0x3, KEY_HOME) + MATRIX_KEY(0x1, 0x0, KEY_RIGHT) + MATRIX_KEY(0x1, 0x1, KEY_LEFT) + MATRIX_KEY(0x1, 0x2, KEY_ENTER) + MATRIX_KEY(0x1, 0x3, KEY_VOLUMEUP) + MATRIX_KEY(0x2, 0x0, KEY_F6) + MATRIX_KEY(0x2, 0x1, KEY_F8) + MATRIX_KEY(0x2, 0x2, KEY_F9) + MATRIX_KEY(0x2, 0x3, KEY_F10) + MATRIX_KEY(0x3, 0x0, KEY_F1) + MATRIX_KEY(0x3, 0x1, KEY_F2) + MATRIX_KEY(0x3, 0x2, KEY_F3) + MATRIX_KEY(0x3, 0x2, KEY_POWER) + >; + status = "okay"; +}; + &ssi1 { codec-handle = <&codec>; fsl,mode = "i2s-slave"; diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi index 9c092571d482..563e168c88a0 100644 --- a/arch/arm/boot/dts/imx25.dtsi +++ b/arch/arm/boot/dts/imx25.dtsi @@ -166,9 +166,10 @@ spi1: cspi@43fa4000 { status = "disabled"; }; - kpp@43fa8000 { + kpp: kpp@43fa8000 { #address-cells = <1>; #size-cells = <0>; + compatible = "fsl,imx25-kpp", "fsl,imx21-kpp"; reg = <0x43fa8000 0x4000>; clocks = <&clks 102>; clock-names = ""; From b04415cf586627c3a42f57a39ed7b5fe8ddcec1f Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 12 Mar 2014 10:19:25 -0300 Subject: [PATCH 021/105] ARM: dts: imx25-pdk: Add CAN support Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx25-pdk.dts | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/imx25-pdk.dts index 34de5e34814c..ebaf48d564a0 100644 --- a/arch/arm/boot/dts/imx25-pdk.dts +++ b/arch/arm/boot/dts/imx25-pdk.dts @@ -52,6 +52,14 @@ reg_3p3v: regulator@2 { regulator-max-microvolt = <3300000>; }; + reg_can_3v3: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "can-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 6 0>; + }; }; sound { @@ -75,6 +83,13 @@ &audmux { status = "okay"; }; +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + xceiver-supply = <®_can_3v3>; + status = "okay"; +}; + &esdhc1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_esdhc1>; @@ -118,6 +133,14 @@ MX25_PAD_EB1__AUD4_RXD 0xe0 >; }; + pinctrl_can1: can1grp { + fsl,pins = < + MX25_PAD_GPIO_A__CAN1_TX 0x0 + MX25_PAD_GPIO_B__CAN1_RX 0x0 + MX25_PAD_D14__GPIO_4_6 0x80000000 + >; + }; + pinctrl_esdhc1: esdhc1grp { fsl,pins = < MX25_PAD_SD1_CMD__SD1_CMD 0x80000000 From 8994181a75d3e6e6e09afad99bda4373458b3a61 Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Sat, 15 Mar 2014 09:22:40 +0400 Subject: [PATCH 022/105] ARM: dts: imx27-phytec-phycore-rdk: Add display support This patch adds FB, Sharp-LQ035Q7 display (add-on module) and corresponded pinctrl devicetree nodes to the Phytec PCM970 RDK. Signed-off-by: Alexander Shiyan Signed-off-by: Shawn Guo --- .../arm/boot/dts/imx27-phytec-phycore-rdk.dts | 64 +++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts index 86510ede7ee2..4a43bfd0ced6 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts +++ b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts @@ -12,6 +12,27 @@ / { model = "Phytec pcm970"; compatible = "phytec,imx27-pcm970", "phytec,imx27-pcm038", "fsl,imx27"; + + display0: LQ035Q7 { + model = "Sharp-LQ035Q7"; + native-mode = <&timing0>; + bits-per-pixel = <16>; + fsl,pcr = <0xf00080c0>; + + display-timings { + timing0: 240x320 { + clock-frequency = <5500000>; + hactive = <240>; + vactive = <320>; + hback-porch = <5>; + hsync-len = <7>; + hfront-porch = <16>; + vback-porch = <7>; + vsync-len = <1>; + vfront-porch = <9>; + }; + }; + }; }; &cspi1 { @@ -21,6 +42,17 @@ &cspi1 { <&gpio4 27 GPIO_ACTIVE_LOW>; }; +&fb { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_imxfb1>; + display = <&display0>; + lcd-supply = <®_5v0>; + fsl,dmacr = <0x00020010>; + fsl,lscr1 = <0x00120300>; + fsl,lpccr = <0x00a903ff>; + status = "okay"; +}; + &i2c1 { clock-frequency = <400000>; pinctrl-names = "default"; @@ -43,6 +75,38 @@ MX27_PAD_CSPI1_SS1__GPIO4_27 0x0 >; }; + pinctrl_imxfb1: imxfbgrp { + fsl,pins = < + MX27_PAD_LD0__LD0 0x0 + MX27_PAD_LD1__LD1 0x0 + MX27_PAD_LD2__LD2 0x0 + MX27_PAD_LD3__LD3 0x0 + MX27_PAD_LD4__LD4 0x0 + MX27_PAD_LD5__LD5 0x0 + MX27_PAD_LD6__LD6 0x0 + MX27_PAD_LD7__LD7 0x0 + MX27_PAD_LD8__LD8 0x0 + MX27_PAD_LD9__LD9 0x0 + MX27_PAD_LD10__LD10 0x0 + MX27_PAD_LD11__LD11 0x0 + MX27_PAD_LD12__LD12 0x0 + MX27_PAD_LD13__LD13 0x0 + MX27_PAD_LD14__LD14 0x0 + MX27_PAD_LD15__LD15 0x0 + MX27_PAD_LD16__LD16 0x0 + MX27_PAD_LD17__LD17 0x0 + MX27_PAD_CLS__CLS 0x0 + MX27_PAD_CONTRAST__CONTRAST 0x0 + MX27_PAD_LSCLK__LSCLK 0x0 + MX27_PAD_OE_ACD__OE_ACD 0x0 + MX27_PAD_PS__PS 0x0 + MX27_PAD_REV__REV 0x0 + MX27_PAD_SPL_SPR__SPL_SPR 0x0 + MX27_PAD_HSYNC__HSYNC 0x0 + MX27_PAD_VSYNC__VSYNC 0x0 + >; + }; + pinctrl_i2c1: i2c1grp { /* Add pullup to DATA line */ fsl,pins = < From f0ee0450d1d27c767289e1f6a16d9c9880b56fde Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sun, 16 Mar 2014 18:09:20 -0300 Subject: [PATCH 023/105] ARM: dts: imx25-pdk: Add USB Host1 support Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx25-pdk.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/imx25-pdk.dts index ebaf48d564a0..c608942b8a3b 100644 --- a/arch/arm/boot/dts/imx25-pdk.dts +++ b/arch/arm/boot/dts/imx25-pdk.dts @@ -243,3 +243,9 @@ &uart1 { fsl,uart-has-rtscts; status = "okay"; }; + +&usbhost1 { + phy_type = "serial"; + dr_mode = "host"; + status = "okay"; +}; From c92578c6e58b55a829d8954b1b9327225d1367cd Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Wed, 19 Mar 2014 15:49:23 +0100 Subject: [PATCH 024/105] ARM: dts: i.MX53: Enable CODA7541 VPU This IP module is always present and has no external connections. There is no reason to disable it in the device tree. Signed-off-by: Philipp Zabel Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx53.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 04815c66fef4..39ea33a09c47 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -728,7 +728,6 @@ vpu: vpu@63ff4000 { <&clks IMX5_CLK_VPU_GATE>; clock-names = "per", "ahb"; iram = <&ocram>; - status = "disabled"; }; }; From b1e2e54610a4d6c98da3bc5a567f18976c0ce032 Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Wed, 19 Mar 2014 15:49:24 +0100 Subject: [PATCH 025/105] ARM: dts: i.MX53: Add reset line to VPU device node Signed-off-by: Philipp Zabel Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx53.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 39ea33a09c47..375e66fad578 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -727,6 +727,7 @@ vpu: vpu@63ff4000 { clocks = <&clks IMX5_CLK_VPU_GATE>, <&clks IMX5_CLK_VPU_GATE>; clock-names = "per", "ahb"; + resets = <&src 1>; iram = <&ocram>; }; }; From 7c978e0fd5dde01c69fc5c594424b017232e16da Mon Sep 17 00:00:00 2001 From: Xiubo Li Date: Mon, 24 Mar 2014 10:22:14 +0800 Subject: [PATCH 026/105] ARM: dts: vf610: Add Freescale FTM PWM node. This adds devicetree node for VF610, and there are 8 channels supported. Signed-off-by: Xiubo Li Reviewed-by: Sascha Hauer Reviewed-by: Yuan Yao Signed-off-by: Shawn Guo --- arch/arm/boot/dts/vf610.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/vf610.dtsi b/arch/arm/boot/dts/vf610.dtsi index 30286bcbe1d0..73355ddc5186 100644 --- a/arch/arm/boot/dts/vf610.dtsi +++ b/arch/arm/boot/dts/vf610.dtsi @@ -183,6 +183,19 @@ pit: pit@40037000 { clock-names = "pit"; }; + pwm0: pwm@40038000 { + compatible = "fsl,vf610-ftm-pwm"; + #pwm-cells = <3>; + reg = <0x40038000 0x1000>; + clock-names = "ftm_sys", "ftm_ext", + "ftm_fix", "ftm_cnt_clk_en"; + clocks = <&clks VF610_CLK_FTM0>, + <&clks VF610_CLK_FTM0_EXT_SEL>, + <&clks VF610_CLK_FTM0_FIX_SEL>, + <&clks VF610_CLK_FTM0_EXT_FIX_EN>; + status = "disabled"; + }; + adc0: adc@4003b000 { compatible = "fsl,vf610-adc"; reg = <0x4003b000 0x1000>; From f54c2fea24c5316f8adc64e277410a8bcb59d699 Mon Sep 17 00:00:00 2001 From: Xiubo Li Date: Mon, 24 Mar 2014 10:22:15 +0800 Subject: [PATCH 027/105] ARM: dts: vf610-twr: Add PWM0's pinctrl node Signed-off-by: Xiubo Li Signed-off-by: Shawn Guo --- arch/arm/boot/dts/vf610-twr.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts index a55f803ef9cb..3a334a5cf6e3 100644 --- a/arch/arm/boot/dts/vf610-twr.dts +++ b/arch/arm/boot/dts/vf610-twr.dts @@ -215,6 +215,17 @@ VF610_PAD_PTB15__I2C0_SDA 0x30d3 >; }; + pinctrl_pwm0: pwm0grp { + fsl,pins = < + VF610_PAD_PTB0__FTM0_CH0 0x1582 + VF610_PAD_PTB1__FTM0_CH1 0x1582 + VF610_PAD_PTB2__FTM0_CH2 0x1582 + VF610_PAD_PTB3__FTM0_CH3 0x1582 + VF610_PAD_PTB6__FTM0_CH6 0x1582 + VF610_PAD_PTB7__FTM0_CH7 0x1582 + >; + }; + pinctrl_sai2: sai2grp { fsl,pins = < VF610_PAD_PTA16__SAI2_TX_BCLK 0x02ed From 266a71b3d3add08b2832b54f9b8d986082639eda Mon Sep 17 00:00:00 2001 From: Xiubo Li Date: Mon, 24 Mar 2014 10:22:16 +0800 Subject: [PATCH 028/105] ARM: dts: vf610-twr: Enables FTM PWM device. Signed-off-by: Xiubo Li Reviewed-by: Sascha Hauer Reviewed-by: Yuan Yao Signed-off-by: Shawn Guo --- arch/arm/boot/dts/vf610-twr.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts index 3a334a5cf6e3..11d733406c7e 100644 --- a/arch/arm/boot/dts/vf610-twr.dts +++ b/arch/arm/boot/dts/vf610-twr.dts @@ -247,6 +247,12 @@ VF610_PAD_PTB5__UART1_RX 0x21a1 }; }; +&pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0>; + status = "okay"; +}; + &sai2 { #sound-dai-cells = <0>; pinctrl-names = "default"; From ebc374657b5a340d28b80aa4a42ad627d8045e01 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 25 Mar 2014 14:47:41 -0300 Subject: [PATCH 029/105] ARM: dts: imx35-pdk: Add initial device tree support Add support for UART, eSDHC and NAND. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx35-pdk.dts | 67 +++++++++++++++++++++++++++++++++ 2 files changed, 68 insertions(+) create mode 100644 arch/arm/boot/dts/imx35-pdk.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 377b7c364033..6807e3e2de24 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -157,6 +157,7 @@ dtb-$(CONFIG_ARCH_MXC) += \ imx27-phytec-phycard-s-rdk.dtb \ imx31-bug.dtb \ imx35-eukrea-mbimxsd35-baseboard.dtb \ + imx35-pdk.dtb \ imx50-evk.dtb \ imx51-apf51.dtb \ imx51-apf51dev.dtb \ diff --git a/arch/arm/boot/dts/imx35-pdk.dts b/arch/arm/boot/dts/imx35-pdk.dts new file mode 100644 index 000000000000..db69ff085e27 --- /dev/null +++ b/arch/arm/boot/dts/imx35-pdk.dts @@ -0,0 +1,67 @@ +/* + * Copyright 2013 Eukréa Electromatique + * Copyright 2014 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx35.dtsi" + +/ { + model = "Freescale i.MX35 Product Development Kit"; + compatible = "fsl,imx35-pdk", "fsl,imx35"; + + memory { + reg = <0x80000000 0x8000000>; + }; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + status = "okay"; +}; + +&iomuxc { + imx35-pdk { + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX35_PAD_SD1_CMD__ESDHC1_CMD 0x80000000 + MX35_PAD_SD1_CLK__ESDHC1_CLK 0x80000000 + MX35_PAD_SD1_DATA0__ESDHC1_DAT0 0x80000000 + MX35_PAD_SD1_DATA1__ESDHC1_DAT1 0x80000000 + MX35_PAD_SD1_DATA2__ESDHC1_DAT2 0x80000000 + MX35_PAD_SD1_DATA3__ESDHC1_DAT3 0x80000000 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX35_PAD_TXD1__UART1_TXD_MUX 0x1c5 + MX35_PAD_RXD1__UART1_RXD_MUX 0x1c5 + MX35_PAD_CTS1__UART1_CTS 0x1c5 + MX35_PAD_RTS1__UART1_RTS 0x1c5 + >; + }; + }; +}; + +&nfc { + nand-bus-width = <16>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + fsl,uart-has-rtscts; + status = "okay"; +}; From 9bf206a9d13be3aafc16092e036a1346b37e2a59 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 26 Mar 2014 11:54:38 -0300 Subject: [PATCH 030/105] ARM: dts: imx51-babbage: Add USB Host1 support Signed-off by: Dave Ebright Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-babbage.dts | 55 +++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts index 9e9deb244b76..b4ae6f80994e 100644 --- a/arch/arm/boot/dts/imx51-babbage.dts +++ b/arch/arm/boot/dts/imx51-babbage.dts @@ -129,6 +129,35 @@ clk_26M: codec_clock { gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; }; }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio2 5 0>; + enable-active-high; + }; + }; + + usbphy { + #address-cells = <1>; + #size-cells = <0>; + compatible = "simple-bus"; + + usbh1phy: usbh1phy@0 { + compatible = "usb-nop-xceiv"; + reg = <0>; + clocks = <&clks 0>; + clock-names = "main_clk"; + }; + }; }; &esdhc1 { @@ -479,6 +508,23 @@ MX51_PAD_EIM_D27__UART3_RTS 0x1c5 MX51_PAD_EIM_D24__UART3_CTS 0x1c5 >; }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX51_PAD_USBH1_CLK__USBH1_CLK 0x80000000 + MX51_PAD_USBH1_DIR__USBH1_DIR 0x80000000 + MX51_PAD_USBH1_NXT__USBH1_NXT 0x80000000 + MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x80000000 + MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x80000000 + MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x80000000 + MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x80000000 + MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x80000000 + MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x80000000 + MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x80000000 + MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x80000000 + MX51_PAD_EIM_D21__GPIO2_5 0x80000000 + >; + }; }; }; @@ -547,3 +593,12 @@ MATRIX_KEY(3, 3, KEY_POWER) >; status = "okay"; }; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + vbus-supply = <®_usb_vbus>; + fsl,usbphy = <&usbh1phy>; + phy_type = "ulpi"; + status = "okay"; +}; From 7538d4ff65a03b0b5b3938332feb32918c6df49b Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 26 Mar 2014 11:54:39 -0300 Subject: [PATCH 031/105] ARM: dts: imx51-babbage: Add USB OTG support Tested by pinging from the host PC to the imx51-babbage via a g_ether connection. Signed-off by: Dave Ebright Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-babbage.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts index b4ae6f80994e..2dda06be52a9 100644 --- a/arch/arm/boot/dts/imx51-babbage.dts +++ b/arch/arm/boot/dts/imx51-babbage.dts @@ -602,3 +602,10 @@ &usbh1 { phy_type = "ulpi"; status = "okay"; }; + +&usbotg { + dr_mode = "otg"; + disable-over-current; + phy_type = "utmi_wide"; + status = "okay"; +}; From 6a20770c12f24658e4ad36fefd68aab0f595709a Mon Sep 17 00:00:00 2001 From: Michael Heimpold Date: Thu, 27 Mar 2014 23:51:27 +0100 Subject: [PATCH 032/105] ARM: dts: imx28-duckbill: fix mmc settings I2SE's duckbills are only equipped with a micro SD card slot and thus only provide a 4-bit interface. Signed-off-by: Michael Heimpold Acked-by: Stefan Wahren Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx28-duckbill.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx28-duckbill.dts b/arch/arm/boot/dts/imx28-duckbill.dts index 5f326c1c1850..a697870ee7b6 100644 --- a/arch/arm/boot/dts/imx28-duckbill.dts +++ b/arch/arm/boot/dts/imx28-duckbill.dts @@ -25,9 +25,9 @@ apbh@80000000 { ssp0: ssp@80010000 { compatible = "fsl,imx28-mmc"; pinctrl-names = "default"; - pinctrl-0 = <&mmc0_8bit_pins_a + pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_cd_cfg &mmc0_sck_cfg>; - bus-width = <8>; + bus-width = <4>; vmmc-supply = <®_3p3v>; status = "okay"; }; From 25fc228ea9a41c3e8b5488f76833fb5b259df5bd Mon Sep 17 00:00:00 2001 From: Michael Heimpold Date: Thu, 27 Mar 2014 23:51:29 +0100 Subject: [PATCH 033/105] ARM: dts: imx28: include gpio.h to allow use of symbolic names Signed-off-by: Michael Heimpold Acked-by: Stefan Wahren Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx28.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index 90a579532b8b..a95cc5358ff4 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -9,6 +9,7 @@ * http://www.gnu.org/copyleft/gpl.html */ +#include #include "skeleton.dtsi" #include "imx28-pinfunc.h" From 99d1d68f4d6a24e9cd77e4f712cad37e93c63234 Mon Sep 17 00:00:00 2001 From: Michael Heimpold Date: Thu, 27 Mar 2014 23:51:28 +0100 Subject: [PATCH 034/105] ARM: dts: imx28-duckbill: fix phy reset gpio Fix a copy & paste error: on duckbills the GPIO used for resetting the ethernet phy differs from FSL's MX28EVK board. Reported-by: Stefan Wahren Signed-off-by: Michael Heimpold Acked-by: Stefan Wahren Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx28-duckbill.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx28-duckbill.dts b/arch/arm/boot/dts/imx28-duckbill.dts index a697870ee7b6..91c1a9a59c52 100644 --- a/arch/arm/boot/dts/imx28-duckbill.dts +++ b/arch/arm/boot/dts/imx28-duckbill.dts @@ -39,7 +39,7 @@ pinctrl@80018000 { hog_pins_a: hog@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_ENET0_RX_CLK__GPIO_4_13 /* PHY Reset */ + MX28_PAD_SSP0_DATA7__GPIO_2_7 /* PHY Reset */ >; fsl,drive-strength = ; fsl,voltage = ; @@ -82,7 +82,7 @@ mac0: ethernet@800f0000 { pinctrl-names = "default"; pinctrl-0 = <&mac0_pins_a>; phy-supply = <®_3p3v>; - phy-reset-gpios = <&gpio4 13 0>; + phy-reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; phy-reset-duration = <100>; status = "okay"; }; From 457c17e1aaf48a76b8be0d90283ec1ee05387616 Mon Sep 17 00:00:00 2001 From: Michael Heimpold Date: Thu, 27 Mar 2014 23:51:30 +0100 Subject: [PATCH 035/105] ARM: dts: imx28-duckbill: use symbolic names from gpio.h Use GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW instead of 0 and 1. Signed-off-by: Michael Heimpold Acked-by: Stefan Wahren Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx28-duckbill.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx28-duckbill.dts b/arch/arm/boot/dts/imx28-duckbill.dts index 91c1a9a59c52..ce1a7effba37 100644 --- a/arch/arm/boot/dts/imx28-duckbill.dts +++ b/arch/arm/boot/dts/imx28-duckbill.dts @@ -110,12 +110,12 @@ leds { status { label = "duckbill:green:status"; - gpios = <&gpio3 5 0>; + gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>; }; failure { label = "duckbill:red:status"; - gpios = <&gpio3 4 0>; + gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>; }; }; }; From 6a21e4bbd79269b0b61599c754e83b9a10c9290d Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Sat, 29 Mar 2014 10:48:25 +0400 Subject: [PATCH 036/105] ARM: dts: imx27-phytec-phycore-rdk: Add display control signal definitions This patch adds display control signal definitions. These fields are not used in the driver yet, but will be used for reference to indicate the polarity of the signals. Signed-off-by: Alexander Shiyan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts index 4a43bfd0ced6..9117a3c754ea 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts +++ b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts @@ -30,6 +30,10 @@ timing0: 240x320 { vback-porch = <7>; vsync-len = <1>; vfront-porch = <9>; + pixelclk-active = <1>; + hsync-active = <1>; + vsync-active = <1>; + de-active = <0>; }; }; }; From 88308edddeb934f9dca22476565301893f826587 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 2 Apr 2014 19:25:44 -0300 Subject: [PATCH 037/105] ARM: dts: imx27-pdk: Pass the memory range imx27-pdk has 128 MB of DRAM. Pass the memory range in dt. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx27-pdk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx27-pdk.dts b/arch/arm/boot/dts/imx27-pdk.dts index 5ce89aa275df..28c83bc851c1 100644 --- a/arch/arm/boot/dts/imx27-pdk.dts +++ b/arch/arm/boot/dts/imx27-pdk.dts @@ -17,7 +17,7 @@ / { compatible = "fsl,imx27-pdk", "fsl,imx27"; memory { - reg = <0x0 0x0>; + reg = <0xa0000000 0x08000000>; }; }; From 9d7bf297cb395c7a509e44df0e27a4cf6ba045e7 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Thu, 3 Apr 2014 17:47:09 +0200 Subject: [PATCH 038/105] of: add vendor prefix for Toradex AG Adds toradex to the list of DT vendor prefixes. Signed-off-by: Stefan Agner Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index abc308083acb..285500407a43 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -123,6 +123,7 @@ stericsson ST-Ericsson synology Synology, Inc. ti Texas Instruments tlm Trusted Logic Mobility +toradex Toradex AG toshiba Toshiba Corporation toumaz Toumaz usi Universal Scientifc Industrial Co., Ltd. From 99db3986407ba62601f8bd45c91bd9527e17d961 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Thu, 3 Apr 2014 17:47:10 +0200 Subject: [PATCH 039/105] ARM: dts: add initial Colibri VF61 board support Add initial Toradex Colibri VF61 board support. Ethernet, UART and SDHC cards are working. Cache latencies need to be a bit higher than vf610.dtsi suggests. Those values are validated by running multiple memory tests. Signed-off-by: Stefan Agner Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/vf610-colibri.dts | 123 ++++++++++++++++++++++++++++ 2 files changed, 124 insertions(+) create mode 100644 arch/arm/boot/dts/vf610-colibri.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 6807e3e2de24..b5cd7f215e39 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -204,6 +204,7 @@ dtb-$(CONFIG_ARCH_MXC) += \ imx6q-udoo.dtb \ imx6q-wandboard.dtb \ imx6sl-evk.dtb \ + vf610-colibri.dtb \ vf610-cosmic.dtb \ vf610-twr.dtb dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \ diff --git a/arch/arm/boot/dts/vf610-colibri.dts b/arch/arm/boot/dts/vf610-colibri.dts new file mode 100644 index 000000000000..aecc7dbc65e8 --- /dev/null +++ b/arch/arm/boot/dts/vf610-colibri.dts @@ -0,0 +1,123 @@ +/* + * Copyright 2014 Toradex AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +/dts-v1/; +#include "vf610.dtsi" + +/ { + model = "Toradex Colibri VF61 COM"; + compatible = "toradex,vf610-colibri", "fsl,vf610"; + + chosen { + bootargs = "console=ttyLP0,115200"; + }; + + memory { + reg = <0x80000000 0x10000000>; + }; + + clocks { + enet_ext { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; + }; + +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + bus-width = <4>; + status = "okay"; +}; + +&fec1 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + status = "okay"; +}; + +&L2 { + arm,data-latency = <2 1 2>; + arm,tag-latency = <3 2 3>; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&iomuxc { + vf610-colibri { + pinctrl_esdhc1: esdhc1grp { + fsl,fsl,pins = < + VF610_PAD_PTA24__ESDHC1_CLK 0x31ef + VF610_PAD_PTA25__ESDHC1_CMD 0x31ef + VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef + VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef + VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef + VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef + VF610_PAD_PTB20__GPIO_42 0x219d + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 + VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 + VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 + VF610_PAD_PTC12__ENET_RMII_RXD1 0x30d1 + VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 + VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 + VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 + VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 + VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 + >; + }; + + pinctrl_uart0: uart0grp { + fsl,pins = < + VF610_PAD_PTB10__UART0_TX 0x21a2 + VF610_PAD_PTB11__UART0_RX 0x21a1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + VF610_PAD_PTB4__UART1_TX 0x21a2 + VF610_PAD_PTB5__UART1_RX 0x21a1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + VF610_PAD_PTD0__UART2_TX 0x21a2 + VF610_PAD_PTD1__UART2_RX 0x21a1 + VF610_PAD_PTD2__UART2_RTS 0x21a2 + VF610_PAD_PTD3__UART2_CTS 0x21a1 + >; + }; + }; +}; From 9c72e2ad21eabcc0c54817b37ae4027fd6549a5e Mon Sep 17 00:00:00 2001 From: Denis Carikli Date: Mon, 7 Apr 2014 18:04:00 +0200 Subject: [PATCH 040/105] ARM: dts: mbimxsd51 baseboard: Add USB support. Signed-off-by: Denis Carikli Signed-off-by: Shawn Guo --- .../dts/imx51-eukrea-mbimxsd51-baseboard.dts | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts index 5cec4f322096..8b1098ebaf79 100644 --- a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts +++ b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts @@ -57,6 +57,20 @@ sound { fsl,mux-int-port = <2>; fsl,mux-ext-port = <3>; }; + + usbphy { + #address-cells = <1>; + #size-cells = <0>; + compatible = "simple-bus"; + + usbh1phy: usbh1phy@0 { + compatible = "usb-nop-xceiv"; + reg = <0>; + clocks = <&clks IMX5_CLK_USB_PHY_GATE>; + clock-names = "main_clk"; + clock-frequency = <19200000>; + }; + }; }; &audmux { @@ -151,6 +165,29 @@ pinctrl_reg_lcd_3v3: reg_lcd_3v3 { MX51_PAD_CSI1_D9__GPIO3_13 0x1f5 >; }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5 + MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5 + MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5 + MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5 + MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5 + MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5 + MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5 + MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5 + MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5 + MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5 + MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5 + MX51_PAD_USBH1_STP__USBH1_STP 0x1e5 + >; + }; + + pinctrl_usbh1_vbus: usbh1-vbusgrp { + fsl,pins = < + MX51_PAD_EIM_CS3__GPIO2_28 0x1f5 + >; + }; }; }; @@ -173,3 +210,24 @@ &uart3 { fsl,uart-has-rtscts; status = "okay"; }; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + fsl,usbphy = <&usbh1phy>; + dr_mode = "host"; + phy_type = "ulpi"; + status = "okay"; +}; + +&usbotg { + dr_mode = "otg"; + phy_type = "utmi_wide"; + status = "okay"; +}; + +&usbphy0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1_vbus>; + reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; +}; From 5ddbc1084ff2dae4136da1f7bfbd188275a37d02 Mon Sep 17 00:00:00 2001 From: Denis Carikli Date: Tue, 8 Apr 2014 18:22:41 +0200 Subject: [PATCH 041/105] ARM: dts: cpuimx35 Add touchscreen support. Signed-off-by: Denis Carikli Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi b/arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi index 906ae937b013..9c2b715ab8bf 100644 --- a/arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi +++ b/arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi @@ -37,6 +37,17 @@ pcf8563@51 { compatible = "nxp,pcf8563"; reg = <0x51>; }; + + tsc2007: tsc2007@48 { + compatible = "ti,tsc2007"; + gpios = <&gpio3 2 0>; + interrupt-parent = <&gpio3>; + interrupts = <0x2 0x8>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tsc2007_1>; + reg = <0x48>; + ti,x-plate-ohms = <180>; + }; }; &iomuxc { @@ -70,6 +81,10 @@ MX35_PAD_I2C1_CLK__I2C1_SCL 0x80000000 MX35_PAD_I2C1_DAT__I2C1_SDA 0x80000000 >; }; + + pinctrl_tsc2007_1: tsc2007grp-1 { + fsl,pins = ; + }; }; }; From a6901700443e473fec816069a4248d08bdd92187 Mon Sep 17 00:00:00 2001 From: Denis Carikli Date: Tue, 8 Apr 2014 18:22:42 +0200 Subject: [PATCH 042/105] ARM: dts: cpuimx51 Add touchscreen support. Signed-off-by: Denis Carikli Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi b/arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi index 9b3acf6e4282..63164266af83 100644 --- a/arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi +++ b/arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi @@ -42,6 +42,17 @@ pcf8563@51 { compatible = "nxp,pcf8563"; reg = <0x51>; }; + + tsc2007: tsc2007@49 { + compatible = "ti,tsc2007"; + gpios = <&gpio4 0 1>; + interrupt-parent = <&gpio4>; + interrupts = <0x0 0x8>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tsc2007_1>; + reg = <0x49>; + ti,x-plate-ohms = <180>; + }; }; &iomuxc { From 3c3ea296198b0ed4b5c7807a729c3022d284bafb Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Wed, 9 Apr 2014 19:08:16 +0400 Subject: [PATCH 043/105] ARM: dts: i.MX: Use single naming style for i.MX WEIM device This patch converts all i.MX WEIM users to use single naming style for devices. Signed-off-by: Alexander Shiyan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts | 2 +- arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts index 9117a3c754ea..8b4181b72596 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts +++ b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts @@ -280,7 +280,7 @@ &weim { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_weim>; - can@d4000000 { + can@4,0 { compatible = "nxp,sja1000"; reg = <4 0x00000000 0x00000100>; interrupt-parent = <&gpio5>; diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi index 8e10aeff946e..d7ed63c51c6c 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi +++ b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi @@ -311,7 +311,7 @@ &usbphy0 { &weim { status = "okay"; - nor: nor@c0000000 { + nor: nor@0,0 { compatible = "cfi-flash"; reg = <0 0x00000000 0x02000000>; bank-width = <2>; @@ -321,7 +321,7 @@ nor: nor@c0000000 { #size-cells = <1>; }; - sram: sram@c8000000 { + sram: sram@1,0 { compatible = "mtd-ram"; reg = <1 0x00000000 0x00800000>; bank-width = <2>; From 4090635410ce13e5117f9c0901882a4a7d02ac8a Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Sat, 12 Apr 2014 09:29:05 +0400 Subject: [PATCH 044/105] ARM i.MX51: Add Digi ConnectCore devicetree MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch adds support for Digi ConnectCore® i.MX51/Wi-i.MX51 SOM and basic support for the ConnectCore for i.MX51 JumpStart Kit. Signed-off-by: Alexander Shiyan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + .../boot/dts/imx51-digi-connectcore-jsk.dts | 108 +++++ .../boot/dts/imx51-digi-connectcore-som.dtsi | 379 ++++++++++++++++++ 3 files changed, 488 insertions(+) create mode 100644 arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts create mode 100644 arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index b5cd7f215e39..400e1941a3d5 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -162,6 +162,7 @@ dtb-$(CONFIG_ARCH_MXC) += \ imx51-apf51.dtb \ imx51-apf51dev.dtb \ imx51-babbage.dtb \ + imx51-digi-connectcore-jsk.dtb \ imx51-eukrea-mbimxsd51-baseboard.dtb \ imx53-ard.dtb \ imx53-m53evk.dtb \ diff --git a/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts b/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts new file mode 100644 index 000000000000..1db517d3d497 --- /dev/null +++ b/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts @@ -0,0 +1,108 @@ +/* + * Copyright (C) 2014 Alexander Shiyan + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include "imx51-digi-connectcore-som.dtsi" + +/ { + model = "Digi ConnectCore CC(W)-MX51 JSK"; + compatible = "digi,connectcore-ccxmx51-jsk", + "digi,connectcore-ccxmx51-som", "fsl,imx51"; + + chosen { + linux,stdout-path = &uart1; + }; +}; + +&owire { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_owire>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&usbotg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + dr_mode = "host"; + phy_type = "ulpi"; + disable-over-current; + status = "okay"; +}; + +&iomuxc { + imx51-digi-connectcore-jsk { + pinctrl_owire: owiregrp { + fsl,pins = < + MX51_PAD_OWIRE_LINE__OWIRE_LINE 0x40000000 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 + MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX51_PAD_UART2_RXD__UART2_RXD 0x1c5 + MX51_PAD_UART2_TXD__UART2_TXD 0x1c5 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 + MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5 + MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5 + MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5 + MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5 + MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5 + MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5 + MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5 + MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5 + MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5 + MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5 + MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5 + MX51_PAD_USBH1_STP__USBH1_STP 0x1e5 + >; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi b/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi new file mode 100644 index 000000000000..7787f46cc5b5 --- /dev/null +++ b/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi @@ -0,0 +1,379 @@ +/* + * Copyright (C) 2014 Alexander Shiyan + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx51.dtsi" + +/ { + model = "Digi ConnectCore CC(W)-MX51"; + compatible = "digi,connectcore-ccxmx51-som", "fsl,imx51"; + + memory { + reg = <0x90000000 0x08000000>; + }; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: mc13892@0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mc13892>; + compatible = "fsl,mc13892"; + spi-max-frequency = <16000000>; + spi-cs-high; + reg = <0>; + interrupt-parent = <&gpio1>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + fsl,mc13xxx-uses-rtc; + + regulators { + sw1_reg: sw1 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3_reg: sw3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { }; + + viohi_reg: viohi { + regulator-always-on; + }; + + vpll_reg: vpll { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vdig_reg: vdig { + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + }; + + vsd_reg: vsd { + regulator-min-microvolt = <3150000>; + regulator-max-microvolt = <3150000>; + regulator-always-on; + }; + + vusb2_reg: vusb2 { + regulator-min-microvolt = <2600000>; + regulator-max-microvolt = <2600000>; + regulator-always-on; + }; + + vvideo_reg: vvideo { + regulator-min-microvolt = <2775000>; + regulator-max-microvolt = <2775000>; + regulator-always-on; + }; + + vaudio_reg: vaudio { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + vcam_reg: vcam { + regulator-min-microvolt = <2750000>; + regulator-max-microvolt = <2750000>; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <3150000>; + regulator-max-microvolt = <3150000>; + regulator-always-on; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vusb_reg: vusb { + regulator-always-on; + }; + + gpo1_reg: gpo1 { }; + + gpo2_reg: gpo2 { }; + + gpo3_reg: gpo3 { }; + + gpo4_reg: gpo4 { }; + + pwgt2spi_reg: pwgt2spi { + regulator-always-on; + }; + + vcoincell_reg: vcoincell { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + }; + }; +}; + +&esdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc2>; + cap-sdio-irq; + enable-sdio-wakeup; + keep-power-in-suspend; + max-frequency = <50000000>; + no-1-8-v; + non-removable; + vmmc-supply = <&gpo4_reg>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "mii"; + phy-supply = <&gpo3_reg>; + /* Pins shared with LCD2, keep status disabled */ +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clock-frequency = <400000>; + status = "okay"; + + mma7455l@1d { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mma7455l>; + compatible = "fsl,mma7455l"; + reg = <0x1d>; + interrupt-parent = <&gpio1>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH>, <6 IRQ_TYPE_LEVEL_HIGH>; + }; +}; + +&nfc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nfc>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + #address-cells = <1>; + #size-cells = <1>; + status = "okay"; +}; + +&usbotg { + phy_type = "utmi_wide"; + disable-over-current; + /* Device role is not known, keep status disabled */ +}; + +&weim { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_weim>; + status = "okay"; + + lan9221: lan9221@5,0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lan9221>; + compatible = "smsc,lan9221", "smsc,lan9115"; + reg = <5 0x00000000 0x1000>; + fsl,weim-cs-timing = < + 0x00420081 0x00000000 + 0x32260000 0x00000000 + 0x72080f00 0x00000000 + >; + clocks = <&clks IMX5_CLK_DUMMY>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + phy-mode = "mii"; + reg-io-width = <2>; + smsc,irq-push-pull; + vdd33a-supply = <&gpo2_reg>; + vddvario-supply = <&gpo2_reg>; + }; +}; + +&iomuxc { + imx51-digi-connectcore-som { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 + MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 + MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 + MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */ + >; + }; + + pinctrl_esdhc2: esdhc2grp { + fsl,pins = < + MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5 + MX51_PAD_SD2_CLK__SD2_CLK 0x20d5 + MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5 + MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5 + MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5 + MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000 + MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000 + MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000 + MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000 + MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000 + MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000 + MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000 + MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000 + MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000 + MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000 + MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000 + MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000 + MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000 + MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000 + MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000 + MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000 + MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000 + MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX51_PAD_GPIO1_2__I2C2_SCL 0x400001ed + MX51_PAD_GPIO1_3__I2C2_SDA 0x400001ed + >; + }; + + pinctrl_nfc: nfcgrp { + fsl,pins = < + MX51_PAD_NANDF_D0__NANDF_D0 0x80000000 + MX51_PAD_NANDF_D1__NANDF_D1 0x80000000 + MX51_PAD_NANDF_D2__NANDF_D2 0x80000000 + MX51_PAD_NANDF_D3__NANDF_D3 0x80000000 + MX51_PAD_NANDF_D4__NANDF_D4 0x80000000 + MX51_PAD_NANDF_D5__NANDF_D5 0x80000000 + MX51_PAD_NANDF_D6__NANDF_D6 0x80000000 + MX51_PAD_NANDF_D7__NANDF_D7 0x80000000 + MX51_PAD_NANDF_ALE__NANDF_ALE 0x80000000 + MX51_PAD_NANDF_CLE__NANDF_CLE 0x80000000 + MX51_PAD_NANDF_RE_B__NANDF_RE_B 0x80000000 + MX51_PAD_NANDF_WE_B__NANDF_WE_B 0x80000000 + MX51_PAD_NANDF_WP_B__NANDF_WP_B 0x80000000 + MX51_PAD_NANDF_CS0__NANDF_CS0 0x80000000 + MX51_PAD_NANDF_RB0__NANDF_RB0 0x80000000 + >; + }; + + pinctrl_lan9221: lan9221grp { + fsl,pins = < + MX51_PAD_GPIO1_9__GPIO1_9 0xe5 /* IRQ */ + >; + }; + + pinctrl_mc13892: mc13892grp { + fsl,pins = < + MX51_PAD_GPIO1_5__GPIO1_5 0xe5 /* IRQ */ + >; + }; + + pinctrl_mma7455l: mma7455lgrp { + fsl,pins = < + MX51_PAD_GPIO1_7__GPIO1_7 0xe5 /* IRQ1 */ + MX51_PAD_GPIO1_6__GPIO1_6 0xe5 /* IRQ2 */ + >; + }; + + pinctrl_weim: weimgrp { + fsl,pins = < + MX51_PAD_EIM_DA0__EIM_DA0 0x80000000 + MX51_PAD_EIM_DA1__EIM_DA1 0x80000000 + MX51_PAD_EIM_DA2__EIM_DA2 0x80000000 + MX51_PAD_EIM_DA3__EIM_DA3 0x80000000 + MX51_PAD_EIM_DA4__EIM_DA4 0x80000000 + MX51_PAD_EIM_DA5__EIM_DA5 0x80000000 + MX51_PAD_EIM_DA6__EIM_DA6 0x80000000 + MX51_PAD_EIM_DA7__EIM_DA7 0x80000000 + MX51_PAD_EIM_DA8__EIM_DA8 0x80000000 + MX51_PAD_EIM_DA9__EIM_DA9 0x80000000 + MX51_PAD_EIM_DA10__EIM_DA10 0x80000000 + MX51_PAD_EIM_DA11__EIM_DA11 0x80000000 + MX51_PAD_EIM_DA12__EIM_DA12 0x80000000 + MX51_PAD_EIM_DA13__EIM_DA13 0x80000000 + MX51_PAD_EIM_DA14__EIM_DA14 0x80000000 + MX51_PAD_EIM_DA15__EIM_DA15 0x80000000 + MX51_PAD_EIM_A16__EIM_A16 0x80000000 + MX51_PAD_EIM_A17__EIM_A17 0x80000000 + MX51_PAD_EIM_A18__EIM_A18 0x80000000 + MX51_PAD_EIM_A19__EIM_A19 0x80000000 + MX51_PAD_EIM_A20__EIM_A20 0x80000000 + MX51_PAD_EIM_A21__EIM_A21 0x80000000 + MX51_PAD_EIM_A22__EIM_A22 0x80000000 + MX51_PAD_EIM_A23__EIM_A23 0x80000000 + MX51_PAD_EIM_A24__EIM_A24 0x80000000 + MX51_PAD_EIM_A25__EIM_A25 0x80000000 + MX51_PAD_EIM_A26__EIM_A26 0x80000000 + MX51_PAD_EIM_A27__EIM_A27 0x80000000 + MX51_PAD_EIM_D16__EIM_D16 0x80000000 + MX51_PAD_EIM_D17__EIM_D17 0x80000000 + MX51_PAD_EIM_D18__EIM_D18 0x80000000 + MX51_PAD_EIM_D19__EIM_D19 0x80000000 + MX51_PAD_EIM_D20__EIM_D20 0x80000000 + MX51_PAD_EIM_D21__EIM_D21 0x80000000 + MX51_PAD_EIM_D22__EIM_D22 0x80000000 + MX51_PAD_EIM_D23__EIM_D23 0x80000000 + MX51_PAD_EIM_D24__EIM_D24 0x80000000 + MX51_PAD_EIM_D25__EIM_D25 0x80000000 + MX51_PAD_EIM_D26__EIM_D26 0x80000000 + MX51_PAD_EIM_D27__EIM_D27 0x80000000 + MX51_PAD_EIM_D28__EIM_D28 0x80000000 + MX51_PAD_EIM_D29__EIM_D29 0x80000000 + MX51_PAD_EIM_D30__EIM_D30 0x80000000 + MX51_PAD_EIM_D31__EIM_D31 0x80000000 + MX51_PAD_EIM_OE__EIM_OE 0x80000000 + MX51_PAD_EIM_DTACK__EIM_DTACK 0x80000000 + MX51_PAD_EIM_LBA__EIM_LBA 0x80000000 + MX51_PAD_EIM_CS5__EIM_CS5 0x80000000 /* CS5 */ + >; + }; + }; +}; From 09c7450c274139ee772e7005869f7c5a8bc60895 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sun, 13 Apr 2014 11:48:41 -0300 Subject: [PATCH 045/105] ARM: dts: imx27-pdk: Keep the dt nodes sorted For better readability keep the dt nodes sorted. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx27-pdk.dts | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/imx27-pdk.dts b/arch/arm/boot/dts/imx27-pdk.dts index 28c83bc851c1..bd9526561f10 100644 --- a/arch/arm/boot/dts/imx27-pdk.dts +++ b/arch/arm/boot/dts/imx27-pdk.dts @@ -21,11 +21,12 @@ memory { }; }; -&uart1 { - fsl,uart-has-rtscts; - status = "okay"; -}; &fec { status = "okay"; }; + +&uart1 { + fsl,uart-has-rtscts; + status = "okay"; +}; From e58773268c38ac69c8998bd36bb2030d3414d630 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sun, 13 Apr 2014 11:48:42 -0300 Subject: [PATCH 046/105] ARM: dts: imx27-pdk: Pass the UART1 pin configuration Provide an entry for the UART1 pin muxing. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx27-pdk.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/imx27-pdk.dts b/arch/arm/boot/dts/imx27-pdk.dts index bd9526561f10..e0f42133f657 100644 --- a/arch/arm/boot/dts/imx27-pdk.dts +++ b/arch/arm/boot/dts/imx27-pdk.dts @@ -28,5 +28,20 @@ &fec { &uart1 { fsl,uart-has-rtscts; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; status = "okay"; }; + +&iomuxc { + imx27-pdk { + pinctrl_uart1: uart1grp { + fsl,pins = < + MX27_PAD_UART1_TXD__UART1_TXD 0x0 + MX27_PAD_UART1_RXD__UART1_RXD 0x0 + MX27_PAD_UART1_CTS__UART1_CTS 0x0 + MX27_PAD_UART1_RTS__UART1_RTS 0x0 + >; + }; + }; +}; From 702fbb89c54e7cbc8881b9b036c139801e862d66 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sun, 13 Apr 2014 11:48:43 -0300 Subject: [PATCH 047/105] ARM: dts: imx27-pdk: Pass the FEC pin configuration Provide an entry for the FEC pin muxing. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx27-pdk.dts | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm/boot/dts/imx27-pdk.dts b/arch/arm/boot/dts/imx27-pdk.dts index e0f42133f657..430b72b5bdb8 100644 --- a/arch/arm/boot/dts/imx27-pdk.dts +++ b/arch/arm/boot/dts/imx27-pdk.dts @@ -23,6 +23,9 @@ memory { &fec { + phy-mode = "mii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; status = "okay"; }; @@ -35,6 +38,29 @@ &uart1 { &iomuxc { imx27-pdk { + pinctrl_fec: fecgrp { + fsl,pins = < + MX27_PAD_SD3_CMD__FEC_TXD0 0x0 + MX27_PAD_SD3_CLK__FEC_TXD1 0x0 + MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 + MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 + MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 + MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 + MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 + MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 + MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 + MX27_PAD_ATA_DATA7__FEC_MDC 0x0 + MX27_PAD_ATA_DATA8__FEC_CRS 0x0 + MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 + MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 + MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 + MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 + MX27_PAD_ATA_DATA13__FEC_COL 0x0 + MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 + MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX27_PAD_UART1_TXD__UART1_TXD 0x0 From 4fe69a934b1f0bf10bede3ecaa1983fe23591012 Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Mon, 14 Apr 2014 17:37:23 +0200 Subject: [PATCH 048/105] ARM: dts: Add Phytec pfla02 with i.MX6 DualLite/Solo Signed-off-by: Philipp Zabel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-phytec-pfla02.dtsi | 22 ++ arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi | 307 +----------------- arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi | 323 +++++++++++++++++++ 3 files changed, 347 insertions(+), 305 deletions(-) create mode 100644 arch/arm/boot/dts/imx6dl-phytec-pfla02.dtsi create mode 100644 arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi diff --git a/arch/arm/boot/dts/imx6dl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6dl-phytec-pfla02.dtsi new file mode 100644 index 000000000000..964bc2ad3c5d --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-phytec-pfla02.dtsi @@ -0,0 +1,22 @@ +/* + * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include "imx6dl.dtsi" +#include "imx6qdl-phytec-pfla02.dtsi" + +/ { + model = "Phytec phyFLEX-i.MX6 DualLite/Solo"; + compatible = "phytec,imx6dl-pfla02", "fsl,imx6dl"; + + memory { + reg = <0x10000000 0x20000000>; + }; +}; diff --git a/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi index 324f1550976b..cd20d0a948de 100644 --- a/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi +++ b/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi @@ -10,316 +10,13 @@ */ #include "imx6q.dtsi" +#include "imx6qdl-phytec-pfla02.dtsi" / { - model = "Phytec phyFLEX-i.MX6 Ouad"; + model = "Phytec phyFLEX-i.MX6 Quad"; compatible = "phytec,imx6q-pfla02", "fsl,imx6q"; memory { reg = <0x10000000 0x80000000>; }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_usb_otg_vbus: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio4 15 0>; - }; - - reg_usb_h1_vbus: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 0 0>; - }; - }; -}; - -&ecspi3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3>; - status = "okay"; - fsl,spi-num-chipselects = <1>; - cs-gpios = <&gpio4 24 0>; - - flash@0 { - compatible = "m25p80"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c32"; - reg = <0x50>; - }; - - pmic@58 { - compatible = "dialog,da9063"; - reg = <0x58>; - interrupt-parent = <&gpio4>; - interrupts = <17 0x8>; /* active-low GPIO4_17 */ - - regulators { - vddcore_reg: bcore1 { - regulator-min-microvolt = <730000>; - regulator-max-microvolt = <1380000>; - regulator-always-on; - }; - - vddsoc_reg: bcore2 { - regulator-min-microvolt = <730000>; - regulator-max-microvolt = <1380000>; - regulator-always-on; - }; - - vdd_ddr3_reg: bpro { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - }; - - vdd_3v3_reg: bperi { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_buckmem_reg: bmem { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_eth_reg: bio { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vdd_eth_io_reg: ldo4 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - vdd_mx6_snvs_reg: ldo5 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - vdd_3v3_pmic_io_reg: ldo6 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_sd0_reg: ldo9 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vdd_sd1_reg: ldo10 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vdd_mx6_high_reg: ldo11 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - }; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx6q-phytec-pfla02 { - pinctrl_hog: hoggrp { - fsl,pins = < - MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 - MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */ - MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x80000000 /* PMIC interrupt */ - >; - }; - - pinctrl_ecspi3: ecspi3grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 - MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 - MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 - MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbh1: usbh1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x80000000 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - >; - }; - - pinctrl_usdhc3_cdwp: usdhc3cdwp { - fsl,pins = < - MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 - >; - }; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - phy-reset-gpios = <&gpio3 23 0>; - status = "disabled"; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; - status = "disabled"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "disabled"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1>; - status = "disabled"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "disabled"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - cd-gpios = <&gpio1 4 0>; - wp-gpios = <&gpio1 2 0>; - status = "disabled"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3 - &pinctrl_usdhc3_cdwp>; - cd-gpios = <&gpio1 27 0>; - wp-gpios = <&gpio1 29 0>; - status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi new file mode 100644 index 000000000000..8ab2c448b56c --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi @@ -0,0 +1,323 @@ +/* + * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/ { + model = "Phytec phyFLEX-i.MX6 Ouad"; + compatible = "phytec,imx6q-pfla02", "fsl,imx6q"; + + memory { + reg = <0x10000000 0x80000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb_otg_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 15 0>; + }; + + reg_usb_h1_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 0 0>; + }; + }; +}; + +&ecspi3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + status = "okay"; + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio4 24 0>; + + flash@0 { + compatible = "m25p80"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + }; + + pmic@58 { + compatible = "dialog,da9063"; + reg = <0x58>; + interrupt-parent = <&gpio4>; + interrupts = <17 0x8>; /* active-low GPIO4_17 */ + + regulators { + vddcore_reg: bcore1 { + regulator-min-microvolt = <730000>; + regulator-max-microvolt = <1380000>; + regulator-always-on; + }; + + vddsoc_reg: bcore2 { + regulator-min-microvolt = <730000>; + regulator-max-microvolt = <1380000>; + regulator-always-on; + }; + + vdd_ddr3_reg: bpro { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + + vdd_3v3_reg: bperi { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_buckmem_reg: bmem { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_eth_reg: bio { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vdd_eth_io_reg: ldo4 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + vdd_mx6_snvs_reg: ldo5 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + vdd_3v3_pmic_io_reg: ldo6 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_sd0_reg: ldo9 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vdd_sd1_reg: ldo10 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vdd_mx6_high_reg: ldo11 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx6q-phytec-pfla02 { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */ + MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x80000000 /* PMIC interrupt */ + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 + MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x80000000 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + >; + }; + + pinctrl_usdhc3_cdwp: usdhc3cdwp { + fsl,pins = < + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 + >; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + phy-reset-gpios = <&gpio3 23 0>; + status = "disabled"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + nand-on-flash-bbt; + status = "disabled"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "disabled"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + status = "disabled"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "disabled"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + cd-gpios = <&gpio1 4 0>; + wp-gpios = <&gpio1 2 0>; + status = "disabled"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3 + &pinctrl_usdhc3_cdwp>; + cd-gpios = <&gpio1 27 0>; + wp-gpios = <&gpio1 29 0>; + status = "disabled"; +}; From 7ed47ef1c98ca7f846b75f45cb927b8ee27f78e5 Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Mon, 14 Apr 2014 17:37:24 +0200 Subject: [PATCH 049/105] ARM: dts: Add Phytec pbab01 with i.MX6 DualLite/Solo The PBA-B-01 carrier board can be equipped with either Quad or DualLite/Solo phyFLEX i.MX6 modules (PFL-A-02). This moves all common devices into imx6qdl-phytec-pbab01.dtsi. The SoC specific device trees then just include the pfla01 and pbab01 dtsi files corresponding to the SoC variant. Signed-off-by: Philipp Zabel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx6dl-phytec-pbab01.dts | 19 ++++++++++ arch/arm/boot/dts/imx6q-phytec-pbab01.dts | 31 ++-------------- arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi | 38 ++++++++++++++++++++ 4 files changed, 60 insertions(+), 29 deletions(-) create mode 100644 arch/arm/boot/dts/imx6dl-phytec-pbab01.dts create mode 100644 arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 400e1941a3d5..917ff4487f2c 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -181,6 +181,7 @@ dtb-$(CONFIG_ARCH_MXC) += \ imx6dl-gw54xx.dtb \ imx6dl-hummingboard.dtb \ imx6dl-nitrogen6x.dtb \ + imx6dl-phytec-pbab01.dtb \ imx6dl-sabreauto.dtb \ imx6dl-sabrelite.dtb \ imx6dl-sabresd.dtb \ diff --git a/arch/arm/boot/dts/imx6dl-phytec-pbab01.dts b/arch/arm/boot/dts/imx6dl-phytec-pbab01.dts new file mode 100644 index 000000000000..08e97801494e --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-phytec-pbab01.dts @@ -0,0 +1,19 @@ +/* + * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx6dl-phytec-pfla02.dtsi" +#include "imx6qdl-phytec-pbab01.dtsi" + +/ { + model = "Phytec phyFLEX-i.MX6 DualLite/Solo Carrier-Board"; + compatible = "phytec,imx6dl-pbab01", "phytec,imx6dl-pfla02", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/imx6q-phytec-pbab01.dts b/arch/arm/boot/dts/imx6q-phytec-pbab01.dts index 5607c331fca8..3a43dab728a8 100644 --- a/arch/arm/boot/dts/imx6q-phytec-pbab01.dts +++ b/arch/arm/boot/dts/imx6q-phytec-pbab01.dts @@ -11,40 +11,13 @@ /dts-v1/; #include "imx6q-phytec-pfla02.dtsi" +#include "imx6qdl-phytec-pbab01.dtsi" / { model = "Phytec phyFLEX-i.MX6 Quad Carrier-Board"; compatible = "phytec,imx6q-pbab01", "phytec,imx6q-pfla02", "fsl,imx6q"; }; -&fec { - status = "okay"; -}; - -&gpmi { - status = "okay"; -}; - &sata { - status = "okay"; -}; - -&uart4 { - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&usbotg { - status = "okay"; -}; - -&usdhc2 { - status = "okay"; -}; - -&usdhc3 { - status = "okay"; + status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi new file mode 100644 index 000000000000..cd2d4af2f519 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi @@ -0,0 +1,38 @@ +/* + * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +&fec { + status = "okay"; +}; + +&gpmi { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + status = "okay"; +}; + +&usdhc2 { + status = "okay"; +}; + +&usdhc3 { + status = "okay"; +}; From 94a1bbf85ac6d49d1e1452c8f8fe4db20e48d139 Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Mon, 14 Apr 2014 17:37:25 +0200 Subject: [PATCH 050/105] ARM: dts: pfla02: Add GPIO LEDs This patch enables the red and green GPIO LEDs on Phytec phyFLEX i.MX6 modules. Signed-off-by: Philipp Zabel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi index 8ab2c448b56c..713893702122 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi @@ -40,6 +40,20 @@ reg_usb_h1_vbus: regulator@1 { gpio = <&gpio1 0 0>; }; }; + + gpio_leds: leds { + compatible = "gpio-leds"; + + green { + label = "phyflex:green"; + gpios = <&gpio1 30 0>; + }; + + red { + label = "phyflex:red"; + gpios = <&gpio2 31 0>; + }; + }; }; &ecspi3 { @@ -156,6 +170,8 @@ pinctrl_hog: hoggrp { MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */ MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x80000000 /* PMIC interrupt */ + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* Green LED */ + MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000 /* Red LED */ >; }; From 26888190cb0f62ca29f1ebf1d67dad4fe51891ec Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Mon, 14 Apr 2014 17:37:26 +0200 Subject: [PATCH 051/105] ARM: dts: pfla02: PHY reset is active-low Note that the fec driver code currently hard-codes an active-low reset, regardless of the flags in the device tree. Signed-off-by: Philipp Zabel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi index 713893702122..69361771274c 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi @@ -9,6 +9,8 @@ * http://www.gnu.org/copyleft/gpl.html */ +#include + / { model = "Phytec phyFLEX-i.MX6 Ouad"; compatible = "phytec,imx6q-pfla02", "fsl,imx6q"; @@ -289,7 +291,7 @@ &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii"; - phy-reset-gpios = <&gpio3 23 0>; + phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; status = "disabled"; }; From 057b3d3cc1b20b7428e1497db3340615db6c02ce Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Mon, 14 Apr 2014 17:37:27 +0200 Subject: [PATCH 052/105] ARM: dts: pbab01: Set linux,stdout-path to UART4 Signed-off-by: Philipp Zabel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi index cd2d4af2f519..4e36aef5190d 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi @@ -9,6 +9,12 @@ * http://www.gnu.org/copyleft/gpl.html */ +/ { + chosen { + linux,stdout-path = &uart4; + }; +}; + &fec { status = "okay"; }; From c3a0940657fa16706efe83dd733c5ceff32de3bb Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Mon, 14 Apr 2014 17:37:28 +0200 Subject: [PATCH 053/105] ARM: dts: pbab01: Add I2C2 and I2C3 Signed-off-by: Philipp Zabel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi | 30 ++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi index 4e36aef5190d..a449a58023e2 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi @@ -23,6 +23,20 @@ &gpmi { status = "okay"; }; +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clock-frequency = <100000>; + status = "okay"; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clock-frequency = <100000>; + status = "okay"; +}; + &uart4 { status = "okay"; }; @@ -42,3 +56,19 @@ &usdhc2 { &usdhc3 { status = "okay"; }; + +&iomuxc { + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 + >; + }; +}; From bcdd334398e5f07ac52c02bc6b4297a0ad00904b Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Mon, 14 Apr 2014 17:37:29 +0200 Subject: [PATCH 054/105] ARM: dts: pbab01: Add I2C devices This patch adds the TLV320, STMPE811, RTC8564, and MX1037 ICs to the I2C2 bus. Signed-off-by: Philipp Zabel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi index a449a58023e2..c6ab762918aa 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi @@ -28,6 +28,26 @@ &i2c2 { pinctrl-0 = <&pinctrl_i2c2>; clock-frequency = <100000>; status = "okay"; + + tlv320@18 { + compatible = "ti,tlv320aic3x"; + reg = <0x18>; + }; + + stmpe@41 { + compatible = "st,stmpe811"; + reg = <0x41>; + }; + + rtc@51 { + compatible = "nxp,rtc8564"; + reg = <0x51>; + }; + + adc@64 { + compatible = "maxim,max1037"; + reg = <0x64>; + }; }; &i2c3 { From 14e2833da3811805dbf1a5276adcb21398e93ab6 Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Mon, 14 Apr 2014 17:37:30 +0200 Subject: [PATCH 055/105] ARM: dts: pfla02: Add UART1 (uart3) The pins labeled UART1 on the module connector are wired to i.MX6 uart3. Signed-off-by: Philipp Zabel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi index 69361771274c..faa3494a69d4 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi @@ -235,6 +235,15 @@ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 >; }; + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x1b0b1 + >; + }; + pinctrl_uart4: uart4grp { fsl,pins = < MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 @@ -302,6 +311,12 @@ &gpmi { status = "disabled"; }; +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "disabled"; +}; + &uart4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart4>; From b6b9439bf8ef3773deed7c39d71c9fdd6f36ce4b Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Mon, 14 Apr 2014 17:37:31 +0200 Subject: [PATCH 056/105] ARM: dts: pbab01: Enable UART1 This patch enables UART1 on the phyFLEX connector (i.MX6 uart3). Signed-off-by: Philipp Zabel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi index c6ab762918aa..323a6479ce37 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi @@ -57,6 +57,10 @@ &i2c3 { status = "okay"; }; +&uart3 { + status = "okay"; +}; + &uart4 { status = "okay"; }; From 25c349c424742a5e431a11c3bb6d8de6ad9fd250 Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Mon, 14 Apr 2014 17:37:32 +0200 Subject: [PATCH 057/105] ARM: dts: pbab01: Enable DVI Signed-off-by: Philipp Zabel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi index 323a6479ce37..584721264121 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi @@ -23,6 +23,10 @@ &gpmi { status = "okay"; }; +&hdmi { + status = "okay"; +}; + &i2c2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; From f0e3f89e686ff0b1464d67e27811a69348a9e3cf Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Wed, 16 Apr 2014 11:24:50 +0400 Subject: [PATCH 058/105] ARM: dts: i.MX51: Allow to define partitions onto NFC This patch allow to define partitions onto NFC in user defined devicetrees. Signed-off-by: Alexander Shiyan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi | 2 -- arch/arm/boot/dts/imx51.dtsi | 2 ++ 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi b/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi index 7787f46cc5b5..321662f53e33 100644 --- a/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi +++ b/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi @@ -195,8 +195,6 @@ &nfc { nand-bus-width = <8>; nand-ecc-mode = "hw"; nand-on-flash-bbt; - #address-cells = <1>; - #size-cells = <1>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 51b86700cd88..bebbf3ba0d5e 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -538,6 +538,8 @@ weim: weim@83fda000 { }; nfc: nand@83fdb000 { + #address-cells = <1>; + #size-cells = <1>; compatible = "fsl,imx51-nand"; reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>; interrupts = <8>; From 2ccc447cd5f91157e91e5835483dbdc8b7c0ad76 Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Wed, 16 Apr 2014 11:24:51 +0400 Subject: [PATCH 059/105] ARM: dts: imx51-babbage: Move "hog" pins into corresponded pin groups Move "hog" pins into corresponded pin groups for eSDHC1, eSDHC2, eCSPI1, gpio-keys, regulator-fixed and codec clock. Additionally, this patch fixes GPIO active level definition for USB regulator. Signed-off-by: Alexander Shiyan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-babbage.dts | 49 ++++++++++++++++++----------- 1 file changed, 31 insertions(+), 18 deletions(-) diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts index 2dda06be52a9..ad143eb9b5a9 100644 --- a/arch/arm/boot/dts/imx51-babbage.dts +++ b/arch/arm/boot/dts/imx51-babbage.dts @@ -82,6 +82,8 @@ display1_in: endpoint { gpio-keys { compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; power { label = "Power Button"; @@ -137,11 +139,13 @@ regulators { reg_usb_vbus: regulator@0 { compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbreg>; reg = <0>; regulator-name = "usb_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - gpio = <&gpio2 5 0>; + gpio = <&gpio2 5 GPIO_ACTIVE_HIGH>; enable-active-high; }; }; @@ -323,23 +327,7 @@ &ssi2 { }; &iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - imx51-babbage { - pinctrl_hog: hoggrp { - fsl,pins = < - MX51_PAD_GPIO1_0__SD1_CD 0x20d5 - MX51_PAD_GPIO1_1__SD1_WP 0x20d5 - MX51_PAD_GPIO1_5__GPIO1_5 0x100 - MX51_PAD_GPIO1_6__GPIO1_6 0x100 - MX51_PAD_EIM_A27__GPIO2_21 0x5 - MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 - MX51_PAD_CSPI1_SS1__GPIO4_25 0x85 - MX51_PAD_CSPI1_RDY__GPIO4_26 0x80000000 - >; - }; - pinctrl_audmux: audmuxgrp { fsl,pins = < MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000 @@ -349,11 +337,19 @@ MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000 >; }; + pinctrl_clkcodec: clkcodecgrp { + fsl,pins = < + MX51_PAD_CSPI1_RDY__GPIO4_26 0x80000000 + >; + }; + pinctrl_ecspi1: ecspi1grp { fsl,pins = < MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 + MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */ + MX51_PAD_CSPI1_SS1__GPIO4_25 0x85 /* CS1 */ >; }; @@ -365,6 +361,8 @@ MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 + MX51_PAD_GPIO1_0__SD1_CD 0x20d5 + MX51_PAD_GPIO1_1__SD1_WP 0x20d5 >; }; @@ -376,6 +374,8 @@ MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5 MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5 MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5 MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5 + MX51_PAD_GPIO1_5__GPIO1_5 0x100 /* WP */ + MX51_PAD_GPIO1_6__GPIO1_6 0x100 /* CD */ >; }; @@ -402,6 +402,12 @@ MX51_PAD_EIM_A20__GPIO2_14 0x85 /* Reset */ >; }; + pinctrl_gpio_keys: gpiokeysgrp { + fsl,pins = < + MX51_PAD_EIM_A27__GPIO2_21 0x5 + >; + }; + pinctrl_gpio_leds: gpioledsgrp { fsl,pins = < MX51_PAD_EIM_D22__GPIO2_6 0x80000000 @@ -522,7 +528,12 @@ MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x80000000 MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x80000000 MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x80000000 MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x80000000 - MX51_PAD_EIM_D21__GPIO2_5 0x80000000 + >; + }; + + pinctrl_usbreg: usbreggrp { + fsl,pins = < + MX51_PAD_EIM_D21__GPIO2_5 0x85 >; }; }; @@ -548,6 +559,8 @@ &i2c2 { sgtl5000: codec@0a { compatible = "fsl,sgtl5000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_clkcodec>; reg = <0x0a>; clocks = <&clk_26M>; VDDA-supply = <&vdig_reg>; From 1ddcff4b52c99aaf501deb9a9f72ed1effa90627 Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Wed, 16 Apr 2014 11:24:52 +0400 Subject: [PATCH 060/105] ARM: dts: imx51-babbage: Add missing pingroup for PMIC This patch adds missing pin definition for PMIC IRQ GPIO. Signed-off-by: Alexander Shiyan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-babbage.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts index ad143eb9b5a9..1652f6aa1036 100644 --- a/arch/arm/boot/dts/imx51-babbage.dts +++ b/arch/arm/boot/dts/imx51-babbage.dts @@ -199,6 +199,8 @@ pmic: mc13892@0 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,mc13892"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; spi-max-frequency = <6000000>; spi-cs-high; reg = <0>; @@ -490,6 +492,12 @@ MX51_PAD_KEY_COL3__KEY_COL3 0xe8 >; }; + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX51_PAD_GPIO1_8__GPIO1_8 0xe5 /* IRQ */ + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 From 02134e77e84905a302bc3a2b2ad4dcca913c4cc5 Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Wed, 16 Apr 2014 11:24:53 +0400 Subject: [PATCH 061/105] ARM: dts: imx51-babbage: Use predefined constants for keys definition Signed-off-by: Alexander Shiyan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-babbage.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts index 1652f6aa1036..a8d6168c5133 100644 --- a/arch/arm/boot/dts/imx51-babbage.dts +++ b/arch/arm/boot/dts/imx51-babbage.dts @@ -88,7 +88,7 @@ gpio-keys { power { label = "Power Button"; gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; - linux,code = <116>; /* KEY_POWER */ + linux,code = ; gpio-key,wakeup; }; }; From db8235ec6ecb7b3d8d27e02ba3b4d1a2c0354910 Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Wed, 16 Apr 2014 11:24:54 +0400 Subject: [PATCH 062/105] ARM: dts: imx51-babbage: Add USB OTG regulator node This patch adds a regulator node and pinctrl group for USB OTG. Signed-off-by: Alexander Shiyan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-babbage.dts | 29 ++++++++++++++++++++++++----- 1 file changed, 24 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts index a8d6168c5133..ed9d769b1a23 100644 --- a/arch/arm/boot/dts/imx51-babbage.dts +++ b/arch/arm/boot/dts/imx51-babbage.dts @@ -137,17 +137,29 @@ regulators { #address-cells = <1>; #size-cells = <0>; - reg_usb_vbus: regulator@0 { + reg_usbh1_vbus: regulator@0 { compatible = "regulator-fixed"; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbreg>; + pinctrl-0 = <&pinctrl_usbh1reg>; reg = <0>; - regulator-name = "usb_vbus"; + regulator-name = "usbh1_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; gpio = <&gpio2 5 GPIO_ACTIVE_HIGH>; enable-active-high; }; + + reg_usbotg_vbus: regulator@1 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotgreg>; + reg = <1>; + regulator-name = "usbotg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; }; usbphy { @@ -539,11 +551,17 @@ MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x80000000 >; }; - pinctrl_usbreg: usbreggrp { + pinctrl_usbh1reg: usbh1reggrp { fsl,pins = < MX51_PAD_EIM_D21__GPIO2_5 0x85 >; }; + + pinctrl_usbotgreg: usbotgreggrp { + fsl,pins = < + MX51_PAD_GPIO1_7__GPIO1_7 0x85 + >; + }; }; }; @@ -618,7 +636,7 @@ MATRIX_KEY(3, 3, KEY_POWER) &usbh1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbh1>; - vbus-supply = <®_usb_vbus>; + vbus-supply = <®_usbh1_vbus>; fsl,usbphy = <&usbh1phy>; phy_type = "ulpi"; status = "okay"; @@ -628,5 +646,6 @@ &usbotg { dr_mode = "otg"; disable-over-current; phy_type = "utmi_wide"; + vbus-supply = <®_usbotg_vbus>; status = "okay"; }; From 1c0daab7653b7530fc697e1b327f05a0269f18cc Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Wed, 16 Apr 2014 11:24:55 +0400 Subject: [PATCH 063/105] ARM: dts: imx51-babbage: Sort nodes by name This patch sorts nodes by name and moves "iomux" configuration at the bottom of file. Signed-off-by: Alexander Shiyan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-babbage.dts | 266 ++++++++++++++-------------- 1 file changed, 133 insertions(+), 133 deletions(-) diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts index ed9d769b1a23..6484b739ae37 100644 --- a/arch/arm/boot/dts/imx51-babbage.dts +++ b/arch/arm/boot/dts/imx51-babbage.dts @@ -21,6 +21,20 @@ memory { reg = <0x90000000 0x20000000>; }; + clocks { + ckih1 { + clock-frequency = <22579200>; + }; + + clk_26M: codec_clock { + compatible = "fixed-clock"; + reg=<0>; + #clock-cells = <0>; + clock-frequency = <26000000>; + gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; + }; + }; + display0: display@di0 { compatible = "fsl,imx-parallel-display"; interface-pix-fmt = "rgb24"; @@ -104,34 +118,6 @@ led-diagnostic { }; }; - sound { - compatible = "fsl,imx51-babbage-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "imx51-babbage-sgtl5000"; - ssi-controller = <&ssi2>; - audio-codec = <&sgtl5000>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <2>; - mux-ext-port = <3>; - }; - - clocks { - ckih1 { - clock-frequency = <22579200>; - }; - - clk_26M: codec_clock { - compatible = "fixed-clock"; - reg=<0>; - #clock-cells = <0>; - clock-frequency = <26000000>; - gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; - }; - }; - regulators { compatible = "simple-bus"; #address-cells = <1>; @@ -162,6 +148,20 @@ reg_usbotg_vbus: regulator@1 { }; }; + sound { + compatible = "fsl,imx51-babbage-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "imx51-babbage-sgtl5000"; + ssi-controller = <&ssi2>; + audio-codec = <&sgtl5000>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <2>; + mux-ext-port = <3>; + }; + usbphy { #address-cells = <1>; #size-cells = <0>; @@ -176,26 +176,9 @@ usbh1phy: usbh1phy@0 { }; }; -&esdhc1 { +&audmux { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - fsl,cd-controller; - fsl,wp-controller; - status = "okay"; -}; - -&esdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc2>; - cd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; - wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - fsl,uart-has-rtscts; + pinctrl-0 = <&pinctrl_audmux>; status = "okay"; }; @@ -327,6 +310,47 @@ partition@40000 { }; }; +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + fsl,cd-controller; + fsl,wp-controller; + status = "okay"; +}; + +&esdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc2>; + cd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "mii"; + phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; + phy-reset-duration = <1>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + sgtl5000: codec@0a { + compatible = "fsl,sgtl5000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_clkcodec>; + reg = <0x0a>; + clocks = <&clk_26M>; + VDDA-supply = <&vdig_reg>; + VDDIO-supply = <&vvideo_reg>; + }; +}; + &ipu_di0_disp0 { remote-endpoint = <&display0_in>; }; @@ -335,11 +359,72 @@ &ipu_di1_disp1 { remote-endpoint = <&display1_in>; }; +&kpp { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_kpp>; + linux,keymap = < + MATRIX_KEY(0, 0, KEY_UP) + MATRIX_KEY(0, 1, KEY_DOWN) + MATRIX_KEY(0, 2, KEY_VOLUMEDOWN) + MATRIX_KEY(0, 3, KEY_HOME) + MATRIX_KEY(1, 0, KEY_RIGHT) + MATRIX_KEY(1, 1, KEY_LEFT) + MATRIX_KEY(1, 2, KEY_ENTER) + MATRIX_KEY(1, 3, KEY_VOLUMEUP) + MATRIX_KEY(2, 0, KEY_F6) + MATRIX_KEY(2, 1, KEY_F8) + MATRIX_KEY(2, 2, KEY_F9) + MATRIX_KEY(2, 3, KEY_F10) + MATRIX_KEY(3, 0, KEY_F1) + MATRIX_KEY(3, 1, KEY_F2) + MATRIX_KEY(3, 2, KEY_F3) + MATRIX_KEY(3, 3, KEY_POWER) + >; + status = "okay"; +}; + &ssi2 { fsl,mode = "i2s-slave"; status = "okay"; }; +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + vbus-supply = <®_usbh1_vbus>; + fsl,usbphy = <&usbh1phy>; + phy_type = "ulpi"; + status = "okay"; +}; + +&usbotg { + dr_mode = "otg"; + disable-over-current; + phy_type = "utmi_wide"; + vbus-supply = <®_usbotg_vbus>; + status = "okay"; +}; + &iomuxc { imx51-babbage { pinctrl_audmux: audmuxgrp { @@ -412,7 +497,7 @@ MX51_PAD_NANDF_CS5__FEC_TDATA2 0x80000000 MX51_PAD_NANDF_CS6__FEC_TDATA3 0x80000000 MX51_PAD_NANDF_CS7__FEC_TX_EN 0x80000000 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000 - MX51_PAD_EIM_A20__GPIO2_14 0x85 /* Reset */ + MX51_PAD_EIM_A20__GPIO2_14 0x85 /* Reset */ >; }; @@ -564,88 +649,3 @@ MX51_PAD_GPIO1_7__GPIO1_7 0x85 }; }; }; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - fsl,uart-has-rtscts; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - sgtl5000: codec@0a { - compatible = "fsl,sgtl5000"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_clkcodec>; - reg = <0x0a>; - clocks = <&clk_26M>; - VDDA-supply = <&vdig_reg>; - VDDIO-supply = <&vvideo_reg>; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "mii"; - phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; - phy-reset-duration = <1>; - status = "okay"; -}; - -&kpp { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_kpp>; - linux,keymap = < - MATRIX_KEY(0, 0, KEY_UP) - MATRIX_KEY(0, 1, KEY_DOWN) - MATRIX_KEY(0, 2, KEY_VOLUMEDOWN) - MATRIX_KEY(0, 3, KEY_HOME) - MATRIX_KEY(1, 0, KEY_RIGHT) - MATRIX_KEY(1, 1, KEY_LEFT) - MATRIX_KEY(1, 2, KEY_ENTER) - MATRIX_KEY(1, 3, KEY_VOLUMEUP) - MATRIX_KEY(2, 0, KEY_F6) - MATRIX_KEY(2, 1, KEY_F8) - MATRIX_KEY(2, 2, KEY_F9) - MATRIX_KEY(2, 3, KEY_F10) - MATRIX_KEY(3, 0, KEY_F1) - MATRIX_KEY(3, 1, KEY_F2) - MATRIX_KEY(3, 2, KEY_F3) - MATRIX_KEY(3, 3, KEY_POWER) - >; - status = "okay"; -}; - -&usbh1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1>; - vbus-supply = <®_usbh1_vbus>; - fsl,usbphy = <&usbh1phy>; - phy_type = "ulpi"; - status = "okay"; -}; - -&usbotg { - dr_mode = "otg"; - disable-over-current; - phy_type = "utmi_wide"; - vbus-supply = <®_usbotg_vbus>; - status = "okay"; -}; From dd0c672a635e483a5164a04bdda3e4cc6cf784df Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Wed, 16 Apr 2014 11:24:56 +0400 Subject: [PATCH 064/105] ARM: dts: imx51-babbage: Add devicetree node for I2C1 This patch adds devicetree node and pinctrl group for I2C1. Signed-off-by: Alexander Shiyan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-babbage.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts index 6484b739ae37..5a50bbf45976 100644 --- a/arch/arm/boot/dts/imx51-babbage.dts +++ b/arch/arm/boot/dts/imx51-babbage.dts @@ -335,6 +335,12 @@ &fec { status = "okay"; }; +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + &i2c2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; @@ -513,6 +519,13 @@ MX51_PAD_EIM_D22__GPIO2_6 0x80000000 >; }; + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX51_PAD_EIM_D19__I2C1_SCL 0x400001ed + MX51_PAD_EIM_D16__I2C1_SDA 0x400001ed + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed From 6b2732847caefeaae01e511108a3d7ff8d80296b Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Wed, 16 Apr 2014 11:24:57 +0400 Subject: [PATCH 065/105] ARM: dts: imx51-babbage: Use predefined constants for clock definition Signed-off-by: Alexander Shiyan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-babbage.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts index 5a50bbf45976..e9ce0c04b8af 100644 --- a/arch/arm/boot/dts/imx51-babbage.dts +++ b/arch/arm/boot/dts/imx51-babbage.dts @@ -170,7 +170,7 @@ usbphy { usbh1phy: usbh1phy@0 { compatible = "usb-nop-xceiv"; reg = <0>; - clocks = <&clks 0>; + clocks = <&clks IMX5_CLK_DUMMY>; clock-names = "main_clk"; }; }; From 2636c1e27fef19e337b8dd7dcc79dd443399fe1a Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 15 Apr 2014 18:55:12 -0300 Subject: [PATCH 066/105] ARM: dts: imx27-pdk: Add PMIC support imx27-pdk has a MC13783 PMIC connected to CSPI2 port. Add support for it. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx27-pdk.dts | 52 +++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/arch/arm/boot/dts/imx27-pdk.dts b/arch/arm/boot/dts/imx27-pdk.dts index 430b72b5bdb8..a4f3e87b43fa 100644 --- a/arch/arm/boot/dts/imx27-pdk.dts +++ b/arch/arm/boot/dts/imx27-pdk.dts @@ -21,6 +21,48 @@ memory { }; }; +&cspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cspi2>; + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: mc13783@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,mc13783"; + reg = <0>; + spi-cs-high; + spi-max-frequency = <1000000>; + interrupt-parent = <&gpio3>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; + + regulators { + vgen_reg: vgen { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + vmmc1_reg: vmmc1 { + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3000000>; + }; + + gpo1_reg: gpo1 { + regulator-always-on; + regulator-boot-on; + }; + + gpo3_reg: gpo3 { + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; &fec { phy-mode = "mii"; @@ -38,6 +80,16 @@ &uart1 { &iomuxc { imx27-pdk { + pinctrl_cspi2: cspi2grp { + fsl,pins = < + MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x0 + MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x0 + MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x0 + MX27_PAD_CSPI2_SS0__GPIO4_21 0x0 /* SPI2 CS0 */ + MX27_PAD_TOUT__GPIO3_14 0x0 /* PMIC IRQ */ + >; + }; + pinctrl_fec: fecgrp { fsl,pins = < MX27_PAD_SD3_CMD__FEC_TXD0 0x0 From 22869087463b31c73daf32f5570b928403469656 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 16 Apr 2014 08:25:56 -0300 Subject: [PATCH 067/105] ARM: dts: imx27-phytec-phycore-som: Move PMIC IRQ GPIO into a separate pin group The hardware is better described if we place the PMIC IRQ GPIO into its own pingroup. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi index d7ed63c51c6c..33c5dc2be89b 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi +++ b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi @@ -69,6 +69,8 @@ pmic: mc13783@0 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,mc13783"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; reg = <0>; spi-cs-high; spi-max-frequency = <20000000>; @@ -204,7 +206,6 @@ MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0 MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0 MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0 MX27_PAD_CSPI1_SS0__GPIO4_28 0x0 /* SPI1 CS0 */ - MX27_PAD_USB_PWR__GPIO2_23 0x0 /* PMIC IRQ */ >; }; @@ -251,6 +252,12 @@ MX27_PAD_NFWE_B__NFWE_B 0x0 >; }; + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX27_PAD_USB_PWR__GPIO2_23 0x0 /* PMIC IRQ */ + >; + }; + pinctrl_ssi1: ssi1grp { fsl,pins = < MX27_PAD_SSI1_FS__SSI1_FS 0x0 From b67b19447eb4f60d4f004f48298154630d4bed39 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 16 Apr 2014 14:53:18 -0300 Subject: [PATCH 068/105] ARM: dts: imx27: Use the correct usb clock gate USB Host1, Host2 and OTG are gated via 'usb_ipg_gate' clock, so fix it in order to avoid the following kernel oops: usbcore: registered new interface driver usb-storage 10024000.usb supply vbus not found, using dummy regulator Unhandled fault: external abort on non-linefetch (0x808) at 0xf4424184 Internal error: : 808 [#1] PREEMPT ARM Modules linked in: CPU: 0 PID: 1 Comm: swapper Not tainted 3.15.0-rc1-26325-g971f9fd-dirty #64 task: c7829aa0 ti: c7836000 task.ti: c7836000 PC is at ci_hdrc_probe+0x3a4/0x634 LR is at ci_hdrc_probe+0x100/0x634 pc : [] lr : [] psr: 60000013 sp : c7837d48 ip : 00000001 fp : 00000000 r10: 00000000 r9 : 00000000 r8 : c791b6c0 r7 : c7945000 r6 : f4424000 r5 : c7945010 r4 : c794e010 r3 : f4424184 r2 : 00000000 r1 : 8c000004 r0 : 0c000004 Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment kernel Control: 0005317f Table: a0004000 DAC: 00000017 Process swapper (pid: 1, stack limit = 0xc78361c0) Stack: (0xc7837d48 to 0xc7838000) Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx27.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi index 00cf66c1b8f3..948354e2c2a3 100644 --- a/arch/arm/boot/dts/imx27.dtsi +++ b/arch/arm/boot/dts/imx27.dtsi @@ -465,7 +465,7 @@ usbotg: usb@10024000 { compatible = "fsl,imx27-usb"; reg = <0x10024000 0x200>; interrupts = <56>; - clocks = <&clks 15>; + clocks = <&clks 75>; fsl,usbmisc = <&usbmisc 0>; fsl,usbphy = <&usbphy0>; status = "disabled"; @@ -475,7 +475,7 @@ usbh1: usb@10024200 { compatible = "fsl,imx27-usb"; reg = <0x10024200 0x200>; interrupts = <54>; - clocks = <&clks 15>; + clocks = <&clks 75>; fsl,usbmisc = <&usbmisc 1>; status = "disabled"; }; @@ -484,7 +484,7 @@ usbh2: usb@10024400 { compatible = "fsl,imx27-usb"; reg = <0x10024400 0x200>; interrupts = <55>; - clocks = <&clks 15>; + clocks = <&clks 75>; fsl,usbmisc = <&usbmisc 2>; fsl,usbphy = <&usbphy2>; status = "disabled"; From af38a00378247a3dc29acf7b482586442b71fafb Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 16 Apr 2014 14:53:19 -0300 Subject: [PATCH 069/105] ARM: dts: imx27: Place the usb phy nodes in the board dts files It is not a good approach to have the USB PHY nodes inside imx27.dtsi since the USB PHYs on mx27 are not internal to the SoC. Place the USB PHY nodes in the board dts files instead. Also, each board may have a different clock source for the USB PHY, so do not hardcode it. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- .../arm/boot/dts/imx27-phytec-phycore-rdk.dts | 19 ++++++++++++---- .../boot/dts/imx27-phytec-phycore-som.dtsi | 19 ++++++++++++---- arch/arm/boot/dts/imx27.dtsi | 22 ------------------- 3 files changed, 30 insertions(+), 30 deletions(-) diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts index 8b4181b72596..0875327bea74 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts +++ b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts @@ -37,6 +37,20 @@ timing0: 240x320 { }; }; }; + + usbphy { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + usbphy2: usbphy@2 { + compatible = "usb-nop-xceiv"; + reg = <0>; + vcc-supply = <®_5v0>; + clocks = <&clks 0>; + clock-names = "main_clk"; + }; + }; }; &cspi1 { @@ -268,14 +282,11 @@ &usbh2 { dr_mode = "host"; phy_type = "ulpi"; vbus-supply = <®_5v0>; + fsl,usbphy = <&usbphy2>; disable-over-current; status = "okay"; }; -&usbphy2 { - vcc-supply = <®_5v0>; -}; - &weim { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_weim>; diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi index 33c5dc2be89b..32cc7dac9ab6 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi +++ b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi @@ -41,6 +41,20 @@ reg_5v0: regulator@1 { regulator-max-microvolt = <5000000>; }; }; + + usbphy { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + usbphy0: usbphy@0 { + compatible = "usb-nop-xceiv"; + reg = <0>; + vcc-supply = <&sw3_reg>; + clocks = <&clks 0>; + clock-names = "main_clk"; + }; + }; }; &audmux { @@ -307,14 +321,11 @@ &usbotg { pinctrl-0 = <&pinctrl_usbotg>; dr_mode = "otg"; phy_type = "ulpi"; + fsl,usbphy = <&usbphy0>; vbus-supply = <&sw3_reg>; status = "okay"; }; -&usbphy0 { - vcc-supply = <&sw3_reg>; -}; - &weim { status = "okay"; diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi index 948354e2c2a3..b2c103e13281 100644 --- a/arch/arm/boot/dts/imx27.dtsi +++ b/arch/arm/boot/dts/imx27.dtsi @@ -72,26 +72,6 @@ cpu: cpu@0 { }; }; - usbphy { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - usbphy0: usbphy@0 { - compatible = "usb-nop-xceiv"; - reg = <0>; - clocks = <&clks 75>; - clock-names = "main_clk"; - }; - - usbphy2: usbphy@2 { - compatible = "usb-nop-xceiv"; - reg = <2>; - clocks = <&clks 75>; - clock-names = "main_clk"; - }; - }; - soc { #address-cells = <1>; #size-cells = <1>; @@ -467,7 +447,6 @@ usbotg: usb@10024000 { interrupts = <56>; clocks = <&clks 75>; fsl,usbmisc = <&usbmisc 0>; - fsl,usbphy = <&usbphy0>; status = "disabled"; }; @@ -486,7 +465,6 @@ usbh2: usb@10024400 { interrupts = <55>; clocks = <&clks 75>; fsl,usbmisc = <&usbmisc 2>; - fsl,usbphy = <&usbphy2>; status = "disabled"; }; From dd860a9a31386ea85fb208d8d68a4b14add74fbf Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 16 Apr 2014 14:53:20 -0300 Subject: [PATCH 070/105] ARM: dts: imx27-pdk: Add USB OTG support Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx27-pdk.dts | 39 +++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm/boot/dts/imx27-pdk.dts b/arch/arm/boot/dts/imx27-pdk.dts index a4f3e87b43fa..971961f8eef5 100644 --- a/arch/arm/boot/dts/imx27-pdk.dts +++ b/arch/arm/boot/dts/imx27-pdk.dts @@ -19,6 +19,19 @@ / { memory { reg = <0xa0000000 0x08000000>; }; + + usbphy { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + usbphy0: usbphy@0 { + compatible = "usb-nop-xceiv"; + reg = <0>; + clocks = <&clks 0>; + clock-names = "main_clk"; + }; + }; }; &cspi2 { @@ -78,6 +91,15 @@ &uart1 { status = "okay"; }; +&usbotg { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + dr_mode = "otg"; + fsl,usbphy = <&usbphy0>; + phy_type = "ulpi"; + status = "okay"; +}; + &iomuxc { imx27-pdk { pinctrl_cspi2: cspi2grp { @@ -121,5 +143,22 @@ MX27_PAD_UART1_CTS__UART1_CTS 0x0 MX27_PAD_UART1_RTS__UART1_RTS 0x0 >; }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0 + MX27_PAD_USBOTG_STP__USBOTG_STP 0x0 + MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0 + MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0 + MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0 + MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0 + MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0 + MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0 + MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0 + MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0 + MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0 + MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0 + >; + }; }; }; From 126b469677762aecc7cc4ed164421a8e4b3dc1c0 Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Wed, 16 Apr 2014 23:23:50 +0200 Subject: [PATCH 071/105] ARM: dts: imx6q-gk802: Enable HDMI Signed-off-by: Philipp Zabel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-gk802.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/imx6q-gk802.dts b/arch/arm/boot/dts/imx6q-gk802.dts index 4a9b4dc9afc0..0f0c50be8859 100644 --- a/arch/arm/boot/dts/imx6q-gk802.dts +++ b/arch/arm/boot/dts/imx6q-gk802.dts @@ -48,6 +48,11 @@ recovery-button { }; }; +&hdmi { + ddc-i2c-bus = <&i2c3>; + status = "okay"; +}; + /* Internal I2C */ &i2c2 { pinctrl-names = "default"; From b41331ecebb2e1bbaeb96d2a5b7bfd79834b0137 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 17 Apr 2014 15:23:30 -0300 Subject: [PATCH 072/105] ARM: dts: imx27-pdk: Add NAND support Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx27-pdk.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/imx27-pdk.dts b/arch/arm/boot/dts/imx27-pdk.dts index 971961f8eef5..042d7ffdffee 100644 --- a/arch/arm/boot/dts/imx27-pdk.dts +++ b/arch/arm/boot/dts/imx27-pdk.dts @@ -84,6 +84,14 @@ &fec { status = "okay"; }; +&nfc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + status = "okay"; +}; + &uart1 { fsl,uart-has-rtscts; pinctrl-names = "default"; @@ -135,6 +143,18 @@ MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0 >; }; + pinctrl_nand: nandgrp { + fsl,pins = < + MX27_PAD_NFRB__NFRB 0x0 + MX27_PAD_NFCLE__NFCLE 0x0 + MX27_PAD_NFWP_B__NFWP_B 0x0 + MX27_PAD_NFCE_B__NFCE_B 0x0 + MX27_PAD_NFALE__NFALE 0x0 + MX27_PAD_NFRE_B__NFRE_B 0x0 + MX27_PAD_NFWE_B__NFWE_B 0x0 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX27_PAD_UART1_TXD__UART1_TXD 0x0 From f6bd3f3087991a85fdf2216fe25784c31f01793b Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 17 Apr 2014 15:23:31 -0300 Subject: [PATCH 073/105] ARM: dts: imx27-pdk: Add keypad support Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx27-pdk.dts | 15 +++++++++++++++ arch/arm/boot/dts/imx27.dtsi | 1 + 2 files changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/imx27-pdk.dts b/arch/arm/boot/dts/imx27-pdk.dts index 042d7ffdffee..764cf798b915 100644 --- a/arch/arm/boot/dts/imx27-pdk.dts +++ b/arch/arm/boot/dts/imx27-pdk.dts @@ -84,6 +84,21 @@ &fec { status = "okay"; }; +&kpp { + linux,keymap = < + MATRIX_KEY(0, 0, KEY_UP) + MATRIX_KEY(0, 1, KEY_DOWN) + MATRIX_KEY(1, 0, KEY_RIGHT) + MATRIX_KEY(1, 1, KEY_LEFT) + MATRIX_KEY(1, 2, KEY_ENTER) + MATRIX_KEY(2, 0, KEY_F6) + MATRIX_KEY(2, 1, KEY_F8) + MATRIX_KEY(2, 2, KEY_F9) + MATRIX_KEY(2, 3, KEY_F10) + >; + status = "okay"; +}; + &nfc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand>; diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi index b2c103e13281..a75555c39533 100644 --- a/arch/arm/boot/dts/imx27.dtsi +++ b/arch/arm/boot/dts/imx27.dtsi @@ -11,6 +11,7 @@ #include "skeleton.dtsi" #include "imx27-pinfunc.h" +#include #include #include From ad704567ff4420253e59d1ed6d58f4a81674b0eb Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 22 Apr 2014 10:04:59 -0300 Subject: [PATCH 074/105] ARM: dts: imx6qdl-sabresd: Add HDMI support Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index 7a88d9ae8daa..7c141f3fea63 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -148,6 +148,11 @@ &fec { status = "okay"; }; +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + &i2c1 { clock-frequency = <100000>; pinctrl-names = "default"; From fed687c526a4e93a9605f779537bf654cda1a36f Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 22 Apr 2014 11:26:22 -0300 Subject: [PATCH 075/105] ARM: dts: imx6qdl-wandboard: Add HDMI support Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-wandboard.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi index bdfdf89d405f..5c6f10c43f65 100644 --- a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi +++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi @@ -62,6 +62,18 @@ &audmux { status = "okay"; }; +&hdmi { + ddc-i2c-bus = <&i2c1>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + &i2c2 { clock-frequency = <100000>; pinctrl-names = "default"; @@ -127,6 +139,13 @@ MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 >; }; + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 From 9d4ebb36a6823c64a8091f293dd5131857e596ec Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 21 Apr 2014 22:56:49 +0200 Subject: [PATCH 076/105] ARM: dts: imx6qdl-sabresd: Add PCIe support Add support for the PCI express bus available on MX6 SabreSDP. Signed-off-by: Marek Vasut Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index 7c141f3fea63..dbbd35b89985 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -389,6 +389,13 @@ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 >; }; + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 + >; + }; + pinctrl_pwm1: pwm1grp { fsl,pins = < MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 @@ -473,6 +480,14 @@ timing0: hsd100pxn1 { }; }; +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + power-on-gpio = <&gpio3 19 0>; + reset-gpio = <&gpio7 12 0>; + status = "okay"; +}; + &pwm1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; From aef15dbaf43db2b8803f28b5d47ccaedbf32c962 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Wed, 23 Apr 2014 00:47:51 -0700 Subject: [PATCH 077/105] ARM: dts: ventana: Add HDMI support Configure ddc and enable HDMI Signed-off-by: Tim Harvey Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-gw5400-a.dts | 5 +++++ arch/arm/boot/dts/imx6qdl-gw51xx.dtsi | 5 +++++ arch/arm/boot/dts/imx6qdl-gw52xx.dtsi | 5 +++++ arch/arm/boot/dts/imx6qdl-gw53xx.dtsi | 5 +++++ arch/arm/boot/dts/imx6qdl-gw54xx.dtsi | 5 +++++ 5 files changed, 25 insertions(+) diff --git a/arch/arm/boot/dts/imx6q-gw5400-a.dts b/arch/arm/boot/dts/imx6q-gw5400-a.dts index e51bb3f0fd56..3689eaa58826 100644 --- a/arch/arm/boot/dts/imx6q-gw5400-a.dts +++ b/arch/arm/boot/dts/imx6q-gw5400-a.dts @@ -157,6 +157,11 @@ &fec { status = "okay"; }; +&hdmi { + ddc-i2c-bus = <&i2c3>; + status = "okay"; +}; + &i2c1 { clock-frequency = <100000>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi index 98a422153ce7..31665adcbf39 100644 --- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi @@ -101,6 +101,11 @@ &gpmi { status = "okay"; }; +&hdmi { + ddc-i2c-bus = <&i2c3>; + status = "okay"; +}; + &i2c1 { clock-frequency = <100000>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi index 035d3a85c318..102219761b20 100644 --- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi @@ -148,6 +148,11 @@ &gpmi { status = "okay"; }; +&hdmi { + ddc-i2c-bus = <&i2c3>; + status = "okay"; +}; + &i2c1 { clock-frequency = <100000>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi index c8e5ae06deaf..523f26f11eea 100644 --- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi @@ -157,6 +157,11 @@ &gpmi { status = "okay"; }; +&hdmi { + ddc-i2c-bus = <&i2c3>; + status = "okay"; +}; + &i2c1 { clock-frequency = <100000>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi index 2795dfc8c926..cab94bfdf691 100644 --- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi @@ -147,6 +147,11 @@ &gpmi { status = "okay"; }; +&hdmi { + ddc-i2c-bus = <&i2c3>; + status = "okay"; +}; + &i2c1 { clock-frequency = <100000>; pinctrl-names = "default"; From 560723a54965155be9360ea031956082e947184d Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Sat, 26 Apr 2014 08:52:06 +0400 Subject: [PATCH 078/105] ARM: dts: imx27-phytec-phycore-rdk: Remove duplicate entries for USB PHY "compatible", "#address-cells" and "#size-cells" for USB PHY are already described in the SOM DTS. Remove these duplicate entries. Signed-off-by: Alexander Shiyan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts index 0875327bea74..ac18ccfa9309 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts +++ b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts @@ -39,10 +39,6 @@ timing0: 240x320 { }; usbphy { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - usbphy2: usbphy@2 { compatible = "usb-nop-xceiv"; reg = <0>; From 198e31d08bd3caeb58c54232f1a06a9097715158 Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Sat, 26 Apr 2014 08:52:07 +0400 Subject: [PATCH 079/105] ARM: dts: imx27-phytec-phycore-som: Fix active level for FEC reset FEC reset GPIO is active low. Fix this typo. Signed-off-by: Alexander Shiyan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi index 32cc7dac9ab6..93482e9d2c93 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi +++ b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi @@ -182,7 +182,7 @@ pwgt1spi_reg: pwgt1spi { &fec { phy-mode = "mii"; - phy-reset-gpios = <&gpio3 30 GPIO_ACTIVE_HIGH>; + phy-reset-gpios = <&gpio3 30 GPIO_ACTIVE_LOW>; phy-supply = <®_3v3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec1>; From 4ee927ed6b183d62965b590e2fd0de125f8d6656 Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Sat, 26 Apr 2014 08:52:08 +0400 Subject: [PATCH 080/105] ARM: dts: imx27-phytec-phycore-som: Disable PM pins for USB OTG USB PWR and OC pins are used as GPIOs for different purposes, so add "disable-over-current" property for OTG node to indicate this. Signed-off-by: Alexander Shiyan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi index 93482e9d2c93..b81796c453b8 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi +++ b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi @@ -323,6 +323,7 @@ &usbotg { phy_type = "ulpi"; fsl,usbphy = <&usbphy0>; vbus-supply = <&sw3_reg>; + disable-over-current; status = "okay"; }; From 388130b07e23c19a0f138361c5e0a8fc5df0b199 Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Sat, 26 Apr 2014 08:52:09 +0400 Subject: [PATCH 081/105] ARM: dts: imx: Remove excess entries for PMIC This patch removes excess "#address-cells" and "#size-cells" entries for PMIC, since these entries is not used. Signed-off-by: Alexander Shiyan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx27-pdk.dts | 2 -- arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi | 2 -- arch/arm/boot/dts/imx51-babbage.dts | 2 -- 3 files changed, 6 deletions(-) diff --git a/arch/arm/boot/dts/imx27-pdk.dts b/arch/arm/boot/dts/imx27-pdk.dts index 764cf798b915..4c317716b510 100644 --- a/arch/arm/boot/dts/imx27-pdk.dts +++ b/arch/arm/boot/dts/imx27-pdk.dts @@ -42,8 +42,6 @@ &cspi2 { status = "okay"; pmic: mc13783@0 { - #address-cells = <1>; - #size-cells = <0>; compatible = "fsl,mc13783"; reg = <0>; spi-cs-high; diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi index b81796c453b8..31e9f7049f73 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi +++ b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi @@ -80,8 +80,6 @@ &cspi1 { status = "okay"; pmic: mc13783@0 { - #address-cells = <1>; - #size-cells = <0>; compatible = "fsl,mc13783"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pmic>; diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts index e9ce0c04b8af..89470bfca160 100644 --- a/arch/arm/boot/dts/imx51-babbage.dts +++ b/arch/arm/boot/dts/imx51-babbage.dts @@ -191,8 +191,6 @@ &ecspi1 { status = "okay"; pmic: mc13892@0 { - #address-cells = <1>; - #size-cells = <0>; compatible = "fsl,mc13892"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pmic>; From 09e96a896e10d1dc2b48ce13e9f5b26f65690382 Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Sat, 26 Apr 2014 08:52:10 +0400 Subject: [PATCH 082/105] ARM: dts: imx27-phytec-phycore-rdk: Add CSI enable switch This patch adds a GPIO fixed regulator which used on RDK to enable CSI bus. Signed-off-by: Alexander Shiyan Signed-off-by: Shawn Guo --- .../arm/boot/dts/imx27-phytec-phycore-rdk.dts | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts index ac18ccfa9309..72c773e2bf98 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts +++ b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts @@ -38,6 +38,20 @@ timing0: 240x320 { }; }; + regulators { + regulator@2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csien>; + reg = <2>; + regulator-name = "CSI_EN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 24 GPIO_ACTIVE_LOW>; + regulator-always-on; + }; + }; + usbphy { usbphy2: usbphy@2 { compatible = "usb-nop-xceiv"; @@ -83,6 +97,12 @@ camgpio: pca9536@41 { &iomuxc { imx27_phycore_rdk { + pinctrl_csien: csiengrp { + fsl,pins = < + MX27_PAD_USB_OC_B__GPIO2_24 0x0 + >; + }; + pinctrl_cspi1cs1: cspi1cs1grp { fsl,pins = < MX27_PAD_CSPI1_SS1__GPIO4_27 0x0 From 9af1187393a3b1b7d2e6b821b76890e47995de84 Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Sat, 26 Apr 2014 08:52:11 +0400 Subject: [PATCH 083/105] ARM: dts: imx27-phytec-phycore-rdk: Fix "reg" property for USBH2 PHY Signed-off-by: Alexander Shiyan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts index 72c773e2bf98..d0b693f12cd2 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts +++ b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts @@ -55,7 +55,7 @@ regulator@2 { usbphy { usbphy2: usbphy@2 { compatible = "usb-nop-xceiv"; - reg = <0>; + reg = <2>; vcc-supply = <®_5v0>; clocks = <&clks 0>; clock-names = "main_clk"; From 204d156a81f4825ec7569ec3074cd652a8f1948b Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 29 Apr 2014 01:59:36 -0300 Subject: [PATCH 084/105] ARM: dts: imx53-qsb-common: Add TVE support Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx53-qsb-common.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/boot/dts/imx53-qsb-common.dtsi b/arch/arm/boot/dts/imx53-qsb-common.dtsi index ede04fa4161f..df9cd9d41c4f 100644 --- a/arch/arm/boot/dts/imx53-qsb-common.dtsi +++ b/arch/arm/boot/dts/imx53-qsb-common.dtsi @@ -272,6 +272,14 @@ MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5 >; }; + pinctrl_vga_sync: vgasync-grp { + fsl,pins = < + /* VGA_HSYNC, VSYNC with max drive strength */ + MX53_PAD_EIM_OE__IPU_DI1_PIN7 0xe6 + MX53_PAD_EIM_RW__IPU_DI1_PIN8 0xe6 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4 @@ -281,6 +289,15 @@ MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4 }; }; +&tve { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_vga_sync>; + fsl,tve-mode = "vga"; + fsl,hsync-pin = <4>; + fsl,vsync-pin = <6>; + status = "okay"; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; From 92a7eb7c7e7f59d818274418a24897339fc5bfc7 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Wed, 30 Apr 2014 13:58:15 +0800 Subject: [PATCH 085/105] ARM: dts: imx6: update pcie to bring in line with new binding The new bindings drops one clock, renames the others and drops the old interrupt mapping. Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl.dtsi | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 02a6afca7530..ce0599134a69 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -141,15 +141,16 @@ pcie: pcie@0x01000000 { 0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */ 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */ num-lanes = <1>; - interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; + interrupt-names = "msi"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks 189>, <&clks 187>, <&clks 206>, <&clks 144>; - clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi"; + clocks = <&clks 144>, <&clks 206>, <&clks 189>; + clock-names = "pcie", "pcie_bus", "pcie_phy"; status = "disabled"; }; From 13d9ab5e8761986a8c24d225cca8e4b4e4a73ef1 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Wed, 30 Apr 2014 12:47:09 +0200 Subject: [PATCH 086/105] ARM: dts: imx6qdl-sabresd: remove power-on gpio from pcie This isn't compatible with the new binding and should be handled via a proper regulator. It shouldn't be needed as the driver has always ignored this property. Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index dbbd35b89985..3db4ca4dd70c 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -391,7 +391,6 @@ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 pinctrl_pcie: pciegrp { fsl,pins = < - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 >; }; @@ -483,7 +482,6 @@ timing0: hsd100pxn1 { &pcie { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie>; - power-on-gpio = <&gpio3 19 0>; reset-gpio = <&gpio7 12 0>; status = "okay"; }; From b3253241fd37a45fae2b25a2892145bed323d224 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Wed, 30 Apr 2014 23:32:30 -0700 Subject: [PATCH 087/105] ARM: dts: imx: add LVDS backlight for Ventana The GW54xx/GW53xx/GW52xx all support LVDS with a PWM controlled backlight. Signed-off-by: Tim Harvey Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-gw52xx.dtsi | 19 +++++++++++++++++++ arch/arm/boot/dts/imx6qdl-gw53xx.dtsi | 19 +++++++++++++++++++ arch/arm/boot/dts/imx6qdl-gw54xx.dtsi | 19 +++++++++++++++++++ 3 files changed, 57 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi index 102219761b20..62f533ab3693 100644 --- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi @@ -27,6 +27,13 @@ chosen { bootargs = "console=ttymxc1,115200"; }; + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + }; + leds { compatible = "gpio-leds"; @@ -399,6 +406,12 @@ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 >; }; + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 @@ -448,6 +461,12 @@ &pcie { status = "okay"; }; +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + &ssi1 { fsl,mode = "i2s-slave"; status = "okay"; diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi index 523f26f11eea..c91b5a6c769b 100644 --- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi @@ -30,6 +30,13 @@ chosen { bootargs = "console=ttymxc1,115200"; }; + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + }; + leds { compatible = "gpio-leds"; @@ -439,6 +446,12 @@ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 >; }; + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 @@ -513,6 +526,12 @@ eth1: sky2@8 { /* MAC/PHY on bus 8 */ }; }; +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + &ssi1 { fsl,mode = "i2s-slave"; status = "okay"; diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi index cab94bfdf691..698d3063b295 100644 --- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi @@ -30,6 +30,13 @@ chosen { bootargs = "console=ttymxc1,115200"; }; + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + }; + leds { compatible = "gpio-leds"; @@ -461,6 +468,12 @@ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 >; }; + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 @@ -535,6 +548,12 @@ eth1: sky2@8 { /* MAC/PHY on bus 8 */ }; }; +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + &ssi1 { fsl,mode = "i2s-slave"; status = "okay"; From c5d2fbd0fd3a813517095fbc59339ed1003da79f Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Wed, 30 Apr 2014 23:34:04 -0700 Subject: [PATCH 088/105] ARM: dts: imx: Fix LVDS mapping for Ventana GW52xx The GW52xx supports LVDS on channel 0. Remove the obsolete crtcs node and add display timings for the HanStar HSD100PXN1 display. Signed-off-by: Tim Harvey Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-gw52xx.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi index 62f533ab3693..367af3ec9435 100644 --- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi @@ -454,6 +454,27 @@ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 &ldb { status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + display-timings { + native-mode = <&timing0>; + timing0: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + }; + }; }; &pcie { From 48f51963641b30add337b4edb6d48ec351c6daf7 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 7 May 2014 15:19:00 +0200 Subject: [PATCH 089/105] ARM: dts: Add stdout-path property to i.MX boards This adds the stdout-path property to various i.MX boards. Values of the property have been taken from barebox, so they should be correct. Also, the older linux,stdout-path property is converted to stdout-path. Signed-off-by: Sascha Hauer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx25-karo-tx25.dts | 4 ++++ arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts | 4 ++++ arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts | 4 ++++ arch/arm/boot/dts/imx51-babbage.dts | 4 ++++ arch/arm/boot/dts/imx53-mba53.dts | 4 ++++ arch/arm/boot/dts/imx53-qsb-common.dtsi | 4 ++++ arch/arm/boot/dts/imx6dl-hummingboard.dts | 4 ++++ arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts | 4 ++++ arch/arm/boot/dts/imx6q-gk802.dts | 2 +- arch/arm/boot/dts/imx6q-phytec-pbab01.dts | 4 ++++ arch/arm/boot/dts/imx6q-udoo.dts | 4 ++++ arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi | 4 ++++ arch/arm/boot/dts/imx6qdl-sabrelite.dtsi | 4 ++++ arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 4 ++++ 15 files changed, 54 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx25-karo-tx25.dts b/arch/arm/boot/dts/imx25-karo-tx25.dts index f8db366c46ff..c83dce9880f9 100644 --- a/arch/arm/boot/dts/imx25-karo-tx25.dts +++ b/arch/arm/boot/dts/imx25-karo-tx25.dts @@ -16,6 +16,10 @@ / { model = "Ka-Ro TX25"; compatible = "karo,imx25-tx25", "fsl,imx25"; + chosen { + stdout-path = &uart1; + }; + memory { reg = <0x80000000 0x02000000 0x90000000 0x02000000>; }; diff --git a/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts index 3c3964a99637..7c869fe3c30b 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts +++ b/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts @@ -15,6 +15,10 @@ / { model = "Phytec pca100 rapid development kit"; compatible = "phytec,imx27-pca100-rdk", "phytec,imx27-pca100", "fsl,imx27"; + chosen { + stdout-path = &uart1; + }; + display: display { model = "Primeview-PD050VL1"; native-mode = <&timing0>; diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts index d0b693f12cd2..fe02bc7a24fd 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts +++ b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts @@ -13,6 +13,10 @@ / { model = "Phytec pcm970"; compatible = "phytec,imx27-pcm970", "phytec,imx27-pcm038", "fsl,imx27"; + chosen { + stdout-path = &uart1; + }; + display0: LQ035Q7 { model = "Sharp-LQ035Q7"; native-mode = <&timing0>; diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts index 89470bfca160..15062a3164a3 100644 --- a/arch/arm/boot/dts/imx51-babbage.dts +++ b/arch/arm/boot/dts/imx51-babbage.dts @@ -17,6 +17,10 @@ / { model = "Freescale i.MX51 Babbage Board"; compatible = "fsl,imx51-babbage", "fsl,imx51"; + chosen { + stdout-path = &uart1; + }; + memory { reg = <0x90000000 0x20000000>; }; diff --git a/arch/arm/boot/dts/imx53-mba53.dts b/arch/arm/boot/dts/imx53-mba53.dts index 7c8c12969892..3f2400b8560b 100644 --- a/arch/arm/boot/dts/imx53-mba53.dts +++ b/arch/arm/boot/dts/imx53-mba53.dts @@ -17,6 +17,10 @@ / { model = "TQ MBa53 starter kit"; compatible = "tq,mba53", "tq,tqma53", "fsl,imx53"; + chosen { + stdout-path = &uart2; + }; + backlight { compatible = "pwm-backlight"; pwms = <&pwm2 0 50000>; diff --git a/arch/arm/boot/dts/imx53-qsb-common.dtsi b/arch/arm/boot/dts/imx53-qsb-common.dtsi index df9cd9d41c4f..fd8c60dde7de 100644 --- a/arch/arm/boot/dts/imx53-qsb-common.dtsi +++ b/arch/arm/boot/dts/imx53-qsb-common.dtsi @@ -13,6 +13,10 @@ #include "imx53.dtsi" / { + chosen { + stdout-path = &uart1; + }; + memory { reg = <0x70000000 0x20000000>, <0xb0000000 0x20000000>; diff --git a/arch/arm/boot/dts/imx6dl-hummingboard.dts b/arch/arm/boot/dts/imx6dl-hummingboard.dts index 5bfae54fb780..121991c6da82 100644 --- a/arch/arm/boot/dts/imx6dl-hummingboard.dts +++ b/arch/arm/boot/dts/imx6dl-hummingboard.dts @@ -11,6 +11,10 @@ / { model = "SolidRun HummingBoard DL/Solo"; compatible = "solidrun,hummingboard", "fsl,imx6dl"; + chosen { + stdout-path = &uart1; + }; + ir_recv: ir-receiver { compatible = "gpio-ir-receiver"; gpios = <&gpio1 2 1>; diff --git a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts index e4ae38fd0269..52446ea4e4c7 100644 --- a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts +++ b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts @@ -18,6 +18,10 @@ / { model = "Data Modul eDM-QMX6 Board"; compatible = "dmo,imx6q-edmqmx6", "fsl,imx6q"; + chosen { + stdout-path = &uart2; + }; + aliases { gpio7 = &stmpe_gpio1; gpio8 = &stmpe_gpio2; diff --git a/arch/arm/boot/dts/imx6q-gk802.dts b/arch/arm/boot/dts/imx6q-gk802.dts index 0f0c50be8859..703539cf36d3 100644 --- a/arch/arm/boot/dts/imx6q-gk802.dts +++ b/arch/arm/boot/dts/imx6q-gk802.dts @@ -14,7 +14,7 @@ / { compatible = "zealz,imx6q-gk802", "fsl,imx6q"; chosen { - linux,stdout-path = &uart4; + stdout-path = &uart4; }; memory { diff --git a/arch/arm/boot/dts/imx6q-phytec-pbab01.dts b/arch/arm/boot/dts/imx6q-phytec-pbab01.dts index 3a43dab728a8..c139ac0ebe15 100644 --- a/arch/arm/boot/dts/imx6q-phytec-pbab01.dts +++ b/arch/arm/boot/dts/imx6q-phytec-pbab01.dts @@ -16,6 +16,10 @@ / { model = "Phytec phyFLEX-i.MX6 Quad Carrier-Board"; compatible = "phytec,imx6q-pbab01", "phytec,imx6q-pfla02", "fsl,imx6q"; + + chosen { + stdout-path = &uart4; + }; }; &sata { diff --git a/arch/arm/boot/dts/imx6q-udoo.dts b/arch/arm/boot/dts/imx6q-udoo.dts index ed397d149ab6..7cc026753392 100644 --- a/arch/arm/boot/dts/imx6q-udoo.dts +++ b/arch/arm/boot/dts/imx6q-udoo.dts @@ -16,6 +16,10 @@ / { model = "Udoo i.MX6 Quad Board"; compatible = "udoo,imx6q-udoo", "fsl,imx6q"; + chosen { + stdout-path = &uart2; + }; + memory { reg = <0x10000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi b/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi index 25cf035dd36e..2c253d6d20bd 100644 --- a/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi +++ b/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi @@ -22,7 +22,7 @@ reg_usb_otg_vbus: regulator@1 { }; chosen { - linux,stdout-path = &uart1; + stdout-path = &uart1; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi index 99be301b5232..4c4b17596c8b 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi @@ -14,6 +14,10 @@ #include / { + chosen { + stdout-path = &uart2; + }; + memory { reg = <0x10000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi index 3bec128c7971..6df6127bf835 100644 --- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi @@ -13,6 +13,10 @@ #include / { + chosen { + stdout-path = &uart2; + }; + memory { reg = <0x10000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index 3db4ca4dd70c..a39217496acc 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -14,6 +14,10 @@ #include / { + chosen { + stdout-path = &uart1; + }; + memory { reg = <0x10000000 0x40000000>; }; From dbfcaed6f0ce14edada9f3a38b896efc44341eba Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 6 May 2014 13:34:19 -0300 Subject: [PATCH 090/105] ARM: dts: imx6q-udoo: Add HDMI support Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-udoo.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm/boot/dts/imx6q-udoo.dts b/arch/arm/boot/dts/imx6q-udoo.dts index 7cc026753392..6c561060bf5c 100644 --- a/arch/arm/boot/dts/imx6q-udoo.dts +++ b/arch/arm/boot/dts/imx6q-udoo.dts @@ -32,6 +32,18 @@ &fec { status = "okay"; }; +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + &iomuxc { imx6q-udoo { pinctrl_enet: enetgrp { @@ -55,6 +67,13 @@ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 >; }; + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + pinctrl_uart2: uart2grp { fsl,pins = < MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 From d02f74aa75241cc8aee65214db16cf4fdd6cf301 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Wed, 7 May 2014 20:09:04 +0200 Subject: [PATCH 091/105] ARM: dts: imx6: edmqmx6: add pinctrl for pfuze irq gpio Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts index 52446ea4e4c7..aac4690afed3 100644 --- a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts +++ b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts @@ -109,7 +109,8 @@ &i2c2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2 &pinctrl_stmpe1 - &pinctrl_stmpe2>; + &pinctrl_stmpe2 + &pinctrl_pfuze>; status = "okay"; pmic: pfuze100@08 { @@ -295,6 +296,12 @@ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 >; }; + pinctrl_pfuze: pfuze100grp1 { + fsl,pins = < + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x80000000 + >; + }; + pinctrl_stmpe1: stmpe1grp { fsl,pins = ; }; From 819826a1586395be4810960cf333a12674466b90 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Wed, 7 May 2014 20:09:05 +0200 Subject: [PATCH 092/105] ARM: dts: imx6: edmqmx6: add SPI bus and flash Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts index aac4690afed3..5b45270e1176 100644 --- a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts +++ b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts @@ -95,6 +95,20 @@ led-red { }; }; +&ecspi5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi5>; + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio1 12 0>; + status = "okay"; + + flash: m25p80@0 { + compatible = "m25p80"; + spi-max-frequency = <40000000>; + reg = <0>; + }; +}; + &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; @@ -268,6 +282,15 @@ MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x80000000 >; }; + pinctrl_ecspi5: ecspi5rp-1 { + fsl,pins = < + MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x80000000 + MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0x80000000 + MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x80000000 + MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x80000000 + >; + }; + pinctrl_enet: enetgrp { fsl,pins = < MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 From f34d0d5dd86e794477c8d23622111f9709085041 Mon Sep 17 00:00:00 2001 From: Russell King Date: Fri, 18 Apr 2014 11:01:27 +0100 Subject: [PATCH 093/105] ARM: imx: add HDMI support for SolidRun HummingBoard and Cubox-i Add the HDMI DT configuration for the SolidRun HummingBoard and Cubox-i. Signed-off-by: Russell King Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-hummingboard.dts | 27 +++++++++++++++++++++++ arch/arm/boot/dts/imx6qdl-cubox-i.dtsi | 27 +++++++++++++++++++++++ 2 files changed, 54 insertions(+) diff --git a/arch/arm/boot/dts/imx6dl-hummingboard.dts b/arch/arm/boot/dts/imx6dl-hummingboard.dts index 121991c6da82..5373a5f2782b 100644 --- a/arch/arm/boot/dts/imx6dl-hummingboard.dts +++ b/arch/arm/boot/dts/imx6dl-hummingboard.dts @@ -71,6 +71,13 @@ &can1 { status = "okay"; }; +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard_hdmi>; + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + &i2c1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hummingboard_i2c1>; @@ -86,6 +93,13 @@ rtc: pcf8523@68 { */ }; +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard_i2c2>; + status = "okay"; +}; + &iomuxc { hummingboard { pinctrl_hummingboard_flexcan1: hummingboard-flexcan1 { @@ -101,6 +115,12 @@ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 >; }; + pinctrl_hummingboard_hdmi: hummingboard-hdmi { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + pinctrl_hummingboard_i2c1: hummingboard-i2c1 { fsl,pins = < MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 @@ -108,6 +128,13 @@ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 >; }; + pinctrl_hummingboard_i2c2: hummingboard-i2c2 { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + pinctrl_hummingboard_spdif: hummingboard-spdif { fsl,pins = ; }; diff --git a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi index c2a24888a276..25da82a03110 100644 --- a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi +++ b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi @@ -55,6 +55,20 @@ sound-spdif { }; }; +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cubox_i_hdmi>; + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cubox_i_i2c2>; + status = "okay"; +}; + &i2c3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_cubox_i_i2c3>; @@ -69,6 +83,19 @@ rtc: pcf8523@68 { &iomuxc { cubox_i { + pinctrl_cubox_i_hdmi: cubox-i-hdmi { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + + pinctrl_cubox_i_i2c2: cubox-i-i2c2 { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + pinctrl_cubox_i_i2c3: cubox-i-i2c3 { fsl,pins = < MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 From e02ab39a2edf95aed487f7d25daa39a93eaf746c Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 8 May 2014 11:10:56 -0300 Subject: [PATCH 094/105] ARM: dts: imx6qdl-sabresd: Add USDHC4 support USDHC4 is connected to a DDR MMC. Add support for it. Signed-off-by: Dong Aisheng Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index a39217496acc..40ea36534643 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -447,6 +447,21 @@ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 >; }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 + >; + }; }; gpio_leds { @@ -537,3 +552,12 @@ &usdhc3 { wp-gpios = <&gpio2 1 0>; status = "okay"; }; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <8>; + non-removable; + no-1-8-v; + status = "okay"; +}; From c73dbd71117bc2a6eb0253add0dbcedf4b097e8b Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 8 May 2014 08:17:30 +0200 Subject: [PATCH 095/105] ARM: dts: i.MX51 babbage: Fix FEC pad ctrl settings The dts relied on the FEC pad ctrl settings from the bootloader by using the NO_PAD_CTRL option. This breaks once the bootloader starts initializing the pad ctrl settings from the same dts file. Change to real pad ctrl settings taken from the platform based babbage support. Signed-off-by: Sascha Hauer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-babbage.dts | 37 +++++++++++++++-------------- 1 file changed, 19 insertions(+), 18 deletions(-) diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts index 15062a3164a3..6bc3243a80d3 100644 --- a/arch/arm/boot/dts/imx51-babbage.dts +++ b/arch/arm/boot/dts/imx51-babbage.dts @@ -488,24 +488,25 @@ MX51_PAD_GPIO1_6__GPIO1_6 0x100 /* CD */ pinctrl_fec: fecgrp { fsl,pins = < - MX51_PAD_EIM_EB2__FEC_MDIO 0x80000000 - MX51_PAD_EIM_EB3__FEC_RDATA1 0x80000000 - MX51_PAD_EIM_CS2__FEC_RDATA2 0x80000000 - MX51_PAD_EIM_CS3__FEC_RDATA3 0x80000000 - MX51_PAD_EIM_CS4__FEC_RX_ER 0x80000000 - MX51_PAD_EIM_CS5__FEC_CRS 0x80000000 - MX51_PAD_NANDF_RB2__FEC_COL 0x80000000 - MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x80000000 - MX51_PAD_NANDF_D9__FEC_RDATA0 0x80000000 - MX51_PAD_NANDF_D8__FEC_TDATA0 0x80000000 - MX51_PAD_NANDF_CS2__FEC_TX_ER 0x80000000 - MX51_PAD_NANDF_CS3__FEC_MDC 0x80000000 - MX51_PAD_NANDF_CS4__FEC_TDATA1 0x80000000 - MX51_PAD_NANDF_CS5__FEC_TDATA2 0x80000000 - MX51_PAD_NANDF_CS6__FEC_TDATA3 0x80000000 - MX51_PAD_NANDF_CS7__FEC_TX_EN 0x80000000 - MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000 - MX51_PAD_EIM_A20__GPIO2_14 0x85 /* Reset */ + MX51_PAD_EIM_EB2__FEC_MDIO 0x000001f5 + MX51_PAD_EIM_EB3__FEC_RDATA1 0x00000085 + MX51_PAD_EIM_CS2__FEC_RDATA2 0x00000085 + MX51_PAD_EIM_CS3__FEC_RDATA3 0x00000085 + MX51_PAD_EIM_CS4__FEC_RX_ER 0x00000180 + MX51_PAD_EIM_CS5__FEC_CRS 0x00000180 + MX51_PAD_NANDF_RB2__FEC_COL 0x00000180 + MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x00000180 + MX51_PAD_NANDF_D9__FEC_RDATA0 0x00002180 + MX51_PAD_NANDF_D8__FEC_TDATA0 0x00002004 + MX51_PAD_NANDF_CS2__FEC_TX_ER 0x00002004 + MX51_PAD_NANDF_CS3__FEC_MDC 0x00002004 + MX51_PAD_NANDF_CS4__FEC_TDATA1 0x00002004 + MX51_PAD_NANDF_CS5__FEC_TDATA2 0x00002004 + MX51_PAD_NANDF_CS6__FEC_TDATA3 0x00002004 + MX51_PAD_NANDF_CS7__FEC_TX_EN 0x00002004 + MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x00002180 + MX51_PAD_NANDF_D11__FEC_RX_DV 0x000020a4 + MX51_PAD_EIM_A20__GPIO2_14 0x00000085 /* Phy Reset */ >; }; From 9e3a424b8ab98726ffc8b2e69e4406d2bb5f5629 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 9 May 2014 08:11:14 +0200 Subject: [PATCH 096/105] ARM: dts: i.MX25: Add mmc aliases Signed-off-by: Sascha Hauer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx25.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi index 563e168c88a0..7f887d63afe5 100644 --- a/arch/arm/boot/dts/imx25.dtsi +++ b/arch/arm/boot/dts/imx25.dtsi @@ -22,6 +22,8 @@ aliases { i2c0 = &i2c1; i2c1 = &i2c2; i2c2 = &i2c3; + mmc0 = &esdhc1; + mmc1 = &esdhc2; serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; From 41707314e7ee6735c797ba3ac42579df471c1a3b Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 9 May 2014 08:11:16 +0200 Subject: [PATCH 097/105] ARM: dts: i.MX25: Add IRAM node Signed-off-by: Sascha Hauer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx25.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi index 7f887d63afe5..bb74d9582b7e 100644 --- a/arch/arm/boot/dts/imx25.dtsi +++ b/arch/arm/boot/dts/imx25.dtsi @@ -523,6 +523,11 @@ dryice@53ffc000 { }; }; + iram: sram@78000000 { + compatible = "mmio-sram"; + reg = <0x78000000 0x20000>; + }; + emi@80000000 { compatible = "fsl,emi-bus", "simple-bus"; #address-cells = <1>; From 8d69043d9950d276bb8553eb57a9b2c24833cf76 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 9 May 2014 08:11:17 +0200 Subject: [PATCH 098/105] ARM: dts: Karo TX25: Add pinctrl nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Sascha Hauer Acked-by: Lothar Waßmann Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx25-karo-tx25.dts | 53 +++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/arch/arm/boot/dts/imx25-karo-tx25.dts b/arch/arm/boot/dts/imx25-karo-tx25.dts index c83dce9880f9..c84d5c932a99 100644 --- a/arch/arm/boot/dts/imx25-karo-tx25.dts +++ b/arch/arm/boot/dts/imx25-karo-tx25.dts @@ -25,16 +25,69 @@ memory { }; }; +&iomuxc { + pinctrl_uart1: uart1grp { + fsl,pins = < + MX25_PAD_UART1_TXD__UART1_TXD 0x80000000 + MX25_PAD_UART1_RXD__UART1_RXD 0x80000000 + MX25_PAD_UART1_CTS__UART1_CTS 0x80000000 + MX25_PAD_UART1_RTS__UART1_RTS 0x80000000 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX25_PAD_D11__GPIO_4_9 0x80000000 /* FEC PHY power on pin */ + MX25_PAD_D13__GPIO_4_7 0x80000000 /* FEC reset */ + MX25_PAD_FEC_MDC__FEC_MDC 0x80000000 + MX25_PAD_FEC_MDIO__FEC_MDIO 0x80000000 + MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000 + MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000 + MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 + MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000 + MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000 + MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000 + MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x80000000 + >; + }; + + pinctrl_nfc: nfcgrp { + fsl,pins = < + MX25_PAD_NF_CE0__NF_CE0 0x80000000 + MX25_PAD_NFWE_B__NFWE_B 0x80000000 + MX25_PAD_NFRE_B__NFRE_B 0x80000000 + MX25_PAD_NFALE__NFALE 0x80000000 + MX25_PAD_NFCLE__NFCLE 0x80000000 + MX25_PAD_NFWP_B__NFWP_B 0x80000000 + MX25_PAD_NFRB__NFRB 0x80000000 + MX25_PAD_D7__D7 0x80000000 + MX25_PAD_D6__D6 0x80000000 + MX25_PAD_D5__D5 0x80000000 + MX25_PAD_D4__D4 0x80000000 + MX25_PAD_D3__D3 0x80000000 + MX25_PAD_D2__D2 0x80000000 + MX25_PAD_D1__D1 0x80000000 + MX25_PAD_D0__D0 0x80000000 + >; + }; +}; + &uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; status = "okay"; }; &fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; phy-mode = "rmii"; status = "okay"; }; &nfc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nfc>; nand-on-flash-bbt; status = "okay"; }; From 974e5872013dce84ad7c5bbbc954fc550eecc467 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 9 May 2014 19:59:55 +0800 Subject: [PATCH 099/105] ARM: dts: Karo TX25: Add phy reset gpio and supply for FEC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Sascha Hauer Acked-by: Lothar Waßmann Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx25-karo-tx25.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/boot/dts/imx25-karo-tx25.dts b/arch/arm/boot/dts/imx25-karo-tx25.dts index c84d5c932a99..69d421790d2f 100644 --- a/arch/arm/boot/dts/imx25-karo-tx25.dts +++ b/arch/arm/boot/dts/imx25-karo-tx25.dts @@ -20,6 +20,22 @@ chosen { stdout-path = &uart1; }; + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_fec_phy: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "fec-phy"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 9 0>; + enable-active-high; + }; + }; + memory { reg = <0x80000000 0x02000000 0x90000000 0x02000000>; }; @@ -81,7 +97,9 @@ &uart1 { &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec>; + phy-reset-gpios = <&gpio3 7 0>; phy-mode = "rmii"; + phy-supply = <®_fec_phy>; status = "okay"; }; From 1885e5de3009d6d3c25a851fe9bc41dc6a81a09d Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 9 May 2014 08:11:19 +0200 Subject: [PATCH 100/105] ARM: dts: Karo TX25: use hardware ecc MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We should use hardware ecc on i.MX. While at it, add the optional nand-bus-width property. Signed-off-by: Sascha Hauer Acked-by: Lothar Waßmann Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx25-karo-tx25.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/imx25-karo-tx25.dts b/arch/arm/boot/dts/imx25-karo-tx25.dts index 69d421790d2f..9b31faa96377 100644 --- a/arch/arm/boot/dts/imx25-karo-tx25.dts +++ b/arch/arm/boot/dts/imx25-karo-tx25.dts @@ -107,5 +107,7 @@ &nfc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nfc>; nand-on-flash-bbt; + nand-ecc-mode = "hw"; + nand-bus-width = <8>; status = "okay"; }; From e59d28e896c5518be84bdddb32e00c46159bdd81 Mon Sep 17 00:00:00 2001 From: Silvio Fricke Date: Thu, 17 Apr 2014 15:28:06 +0200 Subject: [PATCH 101/105] ARM: dts: imx6: edmqmx6: add vcc and vio power supplies to stmpe Signed-off-by: Silvio Fricke Acked-by: Linus Walleij Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts index 5b45270e1176..e0302636aff5 100644 --- a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts +++ b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts @@ -235,6 +235,8 @@ stmpe1: stmpe1601@40 { reg = <0x40>; interrupts = <30 0>; interrupt-parent = <&gpio3>; + vcc-supply = <&sw2_reg>; + vio-supply = <&sw2_reg>; stmpe_gpio1: stmpe_gpio { #gpio-cells = <2>; @@ -247,6 +249,8 @@ stmpe2: stmpe1601@44 { reg = <0x44>; interrupts = <2 0>; interrupt-parent = <&gpio5>; + vcc-supply = <&sw2_reg>; + vio-supply = <&sw2_reg>; stmpe_gpio2: stmpe_gpio { #gpio-cells = <2>; From b92d77639246f19d41af9dab6e368ed0d54fba0c Mon Sep 17 00:00:00 2001 From: Iain Paton Date: Fri, 9 May 2014 16:01:56 +0100 Subject: [PATCH 102/105] ARM: dts: imx6: i2c4 cleanup add missing i2c4 clock and correct the compatible string to match other imx6 i2c blocks Signed-off-by: Iain Paton Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi index 5c5f574330f9..0a9c49d69d41 100644 --- a/arch/arm/boot/dts/imx6dl.dtsi +++ b/arch/arm/boot/dts/imx6dl.dtsi @@ -84,9 +84,10 @@ aips2: aips-bus@02100000 { i2c4: i2c@021f8000 { #address-cells = <1>; #size-cells = <0>; - compatible = "fsl,imx1-i2c"; + compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; reg = <0x021f8000 0x4000>; interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 116>; status = "disabled"; }; }; From ec55b150879fe97f9fd62befcac95119f5467e79 Mon Sep 17 00:00:00 2001 From: Iain Paton Date: Fri, 9 May 2014 16:02:11 +0100 Subject: [PATCH 103/105] ARM: dts: imx6: add new board RIoTboard add element14s RIoTboard http://www.riotboard.org which is an i.MX6Solo based design targeted at makers. Signed-off-by: Iain Paton Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx6dl-riotboard.dts | 539 +++++++++++++++++++++++++ 2 files changed, 540 insertions(+) create mode 100644 arch/arm/boot/dts/imx6dl-riotboard.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 917ff4487f2c..bdd5f700cb06 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -182,6 +182,7 @@ dtb-$(CONFIG_ARCH_MXC) += \ imx6dl-hummingboard.dtb \ imx6dl-nitrogen6x.dtb \ imx6dl-phytec-pbab01.dtb \ + imx6dl-riotboard.dtb \ imx6dl-sabreauto.dtb \ imx6dl-sabrelite.dtb \ imx6dl-sabresd.dtb \ diff --git a/arch/arm/boot/dts/imx6dl-riotboard.dts b/arch/arm/boot/dts/imx6dl-riotboard.dts new file mode 100644 index 000000000000..909fafc0b650 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-riotboard.dts @@ -0,0 +1,539 @@ +/* + * Copyright 2014 Iain Paton + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include + +/ { + model = "RIoTboard i.MX6S"; + compatible = "riot,imx6s-riotboard", "fsl,imx6dl"; + + memory { + reg = <0x10000000 0x40000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_2p5v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + }; + + reg_3p3v: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_usb_otg_vbus: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 0>; + enable-active-high; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led>; + + led0: user1 { + label = "user1"; + gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led1: user2 { + label = "user2"; + gpios = <&gpio3 28 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + sound { + compatible = "fsl,imx-audio-sgtl5000"; + model = "imx6-riotboard-sgtl5000"; + ssi-controller = <&ssi1>; + audio-codec = <&codec>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <3>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + phy-reset-gpios = <&gpio3 31 0>; + interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, + <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + codec: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&clks 201>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; + + pmic: pf0100@08 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + interrupt-parent = <&gpio5>; + interrupts = <16 8>; + + regulators { + reg_vddcore: sw1ab { /* VDDARM_IN */ + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + reg_vddsoc: sw1c { /* VDDSOC_IN */ + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + reg_gen_3v3: sw2 { /* VDDHIGH_IN */ + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_ddr_1v5a: sw3a { /* NVCC_DRAM, NVCC_RGMII */ + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + reg_ddr_1v5b: sw3b { /* NVCC_DRAM, NVCC_RGMII */ + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + reg_ddr_vtt: sw4 { /* MIPI conn */ + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + reg_5v_600mA: swbst { /* not used */ + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + reg_snvs_3v: vsnvs { /* VDD_SNVS_IN */ + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + vref_reg: vrefddr { /* VREF_DDR */ + regulator-boot-on; + regulator-always-on; + }; + + reg_vgen1_1v5: vgen1 { /* not used */ + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + reg_vgen2_1v2_eth: vgen2 { /* pcie ? */ + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + reg_vgen3_2v8: vgen3 { /* not used */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + reg_vgen4_1v8: vgen4 { /* NVCC_SD3 */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_vgen5_2v5_sgtl: vgen5 { /* Pwr LED & 5V0_delayed enable */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_vgen6_3v3: vgen6 { /* #V#_DELAYED enable, MIPI */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + clocks = <&clks 116>; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbh1 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + dr_mode = "otg"; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + cd-gpios = <&gpio1 4 0>; + wp-gpios = <&gpio1 2 0>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + cd-gpios = <&gpio7 0 0>; + wp-gpios = <&gpio7 1 0>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + vmmc-supply = <®_3p3v>; + non-removable; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + + imx6-riotboard { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x8000000 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x8000000 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x8000000 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x8000000 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* CAM_MCLK */ + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x000b1 /* CS0 */ + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x000b1 /* CS1 */ + MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x000b1 /* CS0 */ + MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x100b1 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 + MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x000b1 /* CS0 */ + MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x000b1 /* CS1 */ + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x80000000 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1 /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 /* AR8035 pin strapping: IO voltage: pull up */ + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x130b0 /* AR8035 pin strapping: PHYADDR#0: pull down */ + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x130b0 /* AR8035 pin strapping: PHYADDR#1: pull down */ + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 /* AR8035 pin strapping: MODE#1: pull up */ + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 /* AR8035 pin strapping: MODE#3: pull up */ + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0 /* AR8035 pin strapping: MODE#0: pull down */ + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0xc0000000 /* GPIO16 -> AR8035 25MHz */ + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0 /* RGMII_nRST */ + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* AR8035 interrupt */ + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1 + >; + }; + + pinctrl_led: ledgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000 /* user led0 */ + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x80000000 /* user led1 */ + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* MX6QDL_PAD_EIM_D22__USB_OTG_PWR */ + MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x80000000 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000 /* SD2 CD */ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* SD2 WP */ + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000 /* SD3 CD */ + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x80000000 /* SD3 WP */ + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x80000000 /* SD4 RST (eMMC) */ + >; + }; + }; +}; From 75416cfebc9ae5d35689fcc0a72d384a26871f8e Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sat, 10 May 2014 12:47:35 -0300 Subject: [PATCH 104/105] ARM: dts: imx51-eukrea-mbimxsd51-baseboard: Add CAN support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support for CAN based on a MCP2515 connected to ECSPI1. Signed-off-by: Fabio Estevam Reviewed-by: Eric Bénard Signed-off-by: Shawn Guo --- .../dts/imx51-eukrea-mbimxsd51-baseboard.dts | 62 +++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts index 8b1098ebaf79..75e66c9c6144 100644 --- a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts +++ b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts @@ -24,6 +24,14 @@ / { model = "Eukrea CPUIMX51"; compatible = "eukrea,mbimxsd51","eukrea,cpuimx51", "fsl,imx51"; + clocks { + clk24M: can_clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + }; + gpio_keys { compatible = "gpio-keys"; pinctrl-names = "default"; @@ -50,6 +58,23 @@ led1 { }; }; + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_can: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "CAN_RST"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; + startup-delay-us = <20000>; + enable-active-high; + }; + }; + sound { compatible = "eukrea,asoc-tlv320"; eukrea,model = "imx51-eukrea-tlv320aic23"; @@ -86,6 +111,26 @@ &esdhc1 { status = "okay"; }; +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; + status = "okay"; + + can0: can@0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can>; + compatible = "microchip,mcp2515"; + reg = <0>; + clocks = <&clk24M>; + spi-max-frequency = <10000000>; + interrupt-parent = <&gpio1>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + vdd-supply = <®_can>; + }; +}; + &i2c1 { tlv320aic23: codec@1a { compatible = "ti,tlv320aic23"; @@ -104,6 +149,23 @@ MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000 >; }; + + pinctrl_can: cangrp { + fsl,pins = < + MX51_PAD_CSI2_PIXCLK__GPIO4_15 0x80000000 /* nReset */ + MX51_PAD_GPIO1_1__GPIO1_1 0x80000000 /* IRQ */ + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 + MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 + MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 + MX51_PAD_CSPI1_SS0__GPIO4_24 0x80000000 /* CS0 */ + >; + }; + pinctrl_esdhc1: esdhc1grp { fsl,pins = < MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 From c6f0b878f9b56a755431c74e217830f6550f62b4 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 12 May 2014 22:04:24 -0300 Subject: [PATCH 105/105] ARM: dts: imx35-pdk: Fix memory region description On imx35pdk there are two DRAM chip selects that are used: CS0 at 0x80000000 CS1 at 0x90000000 Each bank is connected to 128MB of DRAM, giving a total of 256MB of system DRAM. Fix the memory layout to describe the hardware appropriately. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx35-pdk.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx35-pdk.dts b/arch/arm/boot/dts/imx35-pdk.dts index db69ff085e27..8d715523708f 100644 --- a/arch/arm/boot/dts/imx35-pdk.dts +++ b/arch/arm/boot/dts/imx35-pdk.dts @@ -18,7 +18,8 @@ / { compatible = "fsl,imx35-pdk", "fsl,imx35"; memory { - reg = <0x80000000 0x8000000>; + reg = <0x80000000 0x8000000>, + <0x90000000 0x8000000>; }; };