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perf/x86: Implement cycles:p for SNB/IVB
Now that there's finally a chip with working PEBS (IvyBridge), we can enable the hardware and implement cycles:p for SNB/IVB. Cc: Stephane Eranian <eranian@google.com> Requested-and-tested-by: Linus Torvalds <torvalds@linux-foundation.org> Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Link: http://lkml.kernel.org/r/1338884803.28282.153.camel@twins Signed-off-by: Ingo Molnar <mingo@kernel.org>
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@ -365,6 +365,7 @@ struct x86_pmu {
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int pebs_record_size;
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int pebs_record_size;
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void (*drain_pebs)(struct pt_regs *regs);
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void (*drain_pebs)(struct pt_regs *regs);
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struct event_constraint *pebs_constraints;
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struct event_constraint *pebs_constraints;
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void (*pebs_aliases)(struct perf_event *event);
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/*
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/*
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* Intel LBR
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* Intel LBR
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@ -1336,15 +1336,9 @@ static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
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intel_put_shared_regs_event_constraints(cpuc, event);
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intel_put_shared_regs_event_constraints(cpuc, event);
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}
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}
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static int intel_pmu_hw_config(struct perf_event *event)
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static void intel_pebs_aliases_core2(struct perf_event *event)
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{
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{
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int ret = x86_pmu_hw_config(event);
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if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
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if (ret)
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return ret;
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if (event->attr.precise_ip &&
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(event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
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/*
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/*
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* Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
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* Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
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* (0x003c) so that we can use it with PEBS.
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* (0x003c) so that we can use it with PEBS.
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@ -1365,10 +1359,48 @@ static int intel_pmu_hw_config(struct perf_event *event)
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*/
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*/
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u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16);
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u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16);
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alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
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event->hw.config = alt_config;
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}
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}
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static void intel_pebs_aliases_snb(struct perf_event *event)
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{
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if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
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/*
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* Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
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* (0x003c) so that we can use it with PEBS.
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*
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* The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
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* PEBS capable. However we can use UOPS_RETIRED.ALL
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* (0x01c2), which is a PEBS capable event, to get the same
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* count.
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*
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* UOPS_RETIRED.ALL counts the number of cycles that retires
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* CNTMASK micro-ops. By setting CNTMASK to a value (16)
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* larger than the maximum number of micro-ops that can be
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* retired per cycle (4) and then inverting the condition, we
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* count all cycles that retire 16 or less micro-ops, which
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* is every cycle.
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*
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* Thereby we gain a PEBS capable cycle counter.
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*/
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u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16);
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alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
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alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
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event->hw.config = alt_config;
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event->hw.config = alt_config;
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}
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}
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}
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static int intel_pmu_hw_config(struct perf_event *event)
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{
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int ret = x86_pmu_hw_config(event);
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if (ret)
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return ret;
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if (event->attr.precise_ip && x86_pmu.pebs_aliases)
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x86_pmu.pebs_aliases(event);
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if (intel_pmu_needs_lbr_smpl(event)) {
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if (intel_pmu_needs_lbr_smpl(event)) {
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ret = intel_pmu_setup_lbr_filter(event);
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ret = intel_pmu_setup_lbr_filter(event);
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@ -1643,6 +1675,7 @@ static __initconst const struct x86_pmu intel_pmu = {
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.max_period = (1ULL << 31) - 1,
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.max_period = (1ULL << 31) - 1,
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.get_event_constraints = intel_get_event_constraints,
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.get_event_constraints = intel_get_event_constraints,
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.put_event_constraints = intel_put_event_constraints,
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.put_event_constraints = intel_put_event_constraints,
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.pebs_aliases = intel_pebs_aliases_core2,
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.format_attrs = intel_arch3_formats_attr,
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.format_attrs = intel_arch3_formats_attr,
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@ -1885,6 +1918,7 @@ __init int intel_pmu_init(void)
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x86_pmu.event_constraints = intel_snb_event_constraints;
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x86_pmu.event_constraints = intel_snb_event_constraints;
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x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
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x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
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x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
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x86_pmu.extra_regs = intel_snb_extra_regs;
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x86_pmu.extra_regs = intel_snb_extra_regs;
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/* all extra regs are per-cpu when HT is on */
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/* all extra regs are per-cpu when HT is on */
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x86_pmu.er_flags |= ERF_HAS_RSP_1;
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x86_pmu.er_flags |= ERF_HAS_RSP_1;
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