mirror of https://gitee.com/openkylin/linux.git
staging: comedi: s626: rename CamelCase in struct s626_private
Rename the CamelCase members of `struct s626_private`. Signed-off-by: Ian Abbott <abbotti@mev.co.uk> Reviewed-by: H Hartley Sweeten <hsweeten@visionengravers.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Ian Abbott
Greg Kroah-Hartman
parent
3a3875067e
commit
07a36d66fa
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@ -81,18 +81,18 @@ struct s626_private {
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int ai_convert_count; /* conversion counter */
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unsigned int ai_convert_timer; /* time between conversion in
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* units of the timer */
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uint16_t CounterIntEnabs; /* counter interrupt enable mask
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uint16_t counter_int_enabs; /* counter interrupt enable mask
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* for MISC2 register */
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uint8_t AdcItems; /* number of items in ADC poll list */
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struct buffer_dma RPSBuf; /* DMA buffer used to hold ADC (RPS1)
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uint8_t adc_items; /* number of items in ADC poll list */
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struct buffer_dma rps_buf; /* DMA buffer used to hold ADC (RPS1)
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* program */
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struct buffer_dma ANABuf; /* DMA buffer used to receive ADC data
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struct buffer_dma ana_buf; /* DMA buffer used to receive ADC data
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* and hold DAC data */
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uint32_t *pDacWBuf; /* pointer to logical adrs of DMA buffer
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uint32_t *dac_wbuf; /* pointer to logical adrs of DMA buffer
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* used to hold DAC data */
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uint16_t Dacpol; /* image of DAC polarity register */
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uint8_t TrimSetpoint[12]; /* images of TrimDAC setpoints */
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uint32_t I2CAdrs; /* I2C device address for onboard EEPROM
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uint16_t dacpol; /* image of DAC polarity register */
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uint8_t trim_setpoint[12]; /* images of TrimDAC setpoints */
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uint32_t i2c_adrs; /* I2C device address for onboard EEPROM
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* (board rev dependent) */
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unsigned int ao_readback[S626_DAC_CHANNELS];
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};
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@ -304,7 +304,7 @@ static uint8_t I2Cread(struct comedi_device *dev, uint8_t addr)
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* Byte1 = EEPROM internal target address.
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* Byte0 = Not sent.
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*/
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if (I2Chandshake(dev, I2C_B2(I2C_ATTRSTART, devpriv->I2CAdrs) |
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if (I2Chandshake(dev, I2C_B2(I2C_ATTRSTART, devpriv->i2c_adrs) |
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I2C_B1(I2C_ATTRSTOP, addr) |
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I2C_B0(I2C_ATTRNOP, 0)))
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/* Abort function and declare error if handshake failed. */
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@ -316,7 +316,7 @@ static uint8_t I2Cread(struct comedi_device *dev, uint8_t addr)
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* Byte1 receives uint8_t from EEPROM.
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* Byte0 = Not sent.
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*/
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if (I2Chandshake(dev, I2C_B2(I2C_ATTRSTART, (devpriv->I2CAdrs | 1)) |
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if (I2Chandshake(dev, I2C_B2(I2C_ATTRSTART, (devpriv->i2c_adrs | 1)) |
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I2C_B1(I2C_ATTRSTOP, 0) |
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I2C_B0(I2C_ATTRNOP, 0)))
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/* Abort function and declare error if handshake failed. */
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@ -342,7 +342,7 @@ static uint8_t trimadrs[] = {
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/*
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* Private helper function: Transmit serial data to DAC via Audio
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* channel 2. Assumes: (1) TSL2 slot records initialized, and (2)
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* Dacpol contains valid target image.
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* dacpol contains valid target image.
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*/
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static void SendDAC(struct comedi_device *dev, uint32_t val)
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{
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@ -360,13 +360,13 @@ static void SendDAC(struct comedi_device *dev, uint32_t val)
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* trailing edge of WS1/WS3 (which turns off the signals), thus
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* causing the signals to be inactive during the DAC write.
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*/
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DEBIwrite(dev, LP_DACPOL, devpriv->Dacpol);
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DEBIwrite(dev, LP_DACPOL, devpriv->dacpol);
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/* TRANSFER OUTPUT DWORD VALUE INTO A2'S OUTPUT FIFO ---------------- */
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/* Copy DAC setpoint value to DAC's output DMA buffer. */
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/* writel(val, devpriv->mmio + (uint32_t)devpriv->pDacWBuf); */
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*devpriv->pDacWBuf = val;
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/* writel(val, devpriv->mmio + (uint32_t)devpriv->dac_wbuf); */
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*devpriv->dac_wbuf = val;
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/*
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* Enable the output DMA transfer. This will cause the DMAC to copy
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@ -492,9 +492,9 @@ static void SetDAC(struct comedi_device *dev, uint16_t chan, short dacdata)
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signmask = 1 << chan;
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if (dacdata < 0) {
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dacdata = -dacdata;
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devpriv->Dacpol |= signmask;
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devpriv->dacpol |= signmask;
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} else {
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devpriv->Dacpol &= ~signmask;
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devpriv->dacpol &= ~signmask;
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}
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/* Limit DAC setpoint value to valid range. */
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@ -550,7 +550,7 @@ static void WriteTrimDAC(struct comedi_device *dev, uint8_t LogicalChan,
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* Save the new setpoint in case the application needs to read it back
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* later.
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*/
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devpriv->TrimSetpoint[LogicalChan] = (uint8_t)DacData;
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devpriv->trim_setpoint[LogicalChan] = (uint8_t)DacData;
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/* Map logical channel number to physical channel number. */
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chan = trimchan[LogicalChan];
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@ -857,7 +857,7 @@ static bool handle_eos_interrupt(struct comedi_device *dev)
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* first uint16_t in the buffer because it contains junk data
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* from the final ADC of the previous poll list scan.
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*/
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int32_t *readaddr = (int32_t *)devpriv->ANABuf.logical_base + 1;
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int32_t *readaddr = (int32_t *)devpriv->ana_buf.logical_base + 1;
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bool finished = false;
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int i;
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@ -964,13 +964,13 @@ static void ResetADC(struct comedi_device *dev, uint8_t *ppl)
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s626_mc_disable(dev, MC1_ERPS1, P_MC1);
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/* Set starting logical address to write RPS commands. */
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pRPS = (uint32_t *)devpriv->RPSBuf.logical_base;
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pRPS = (uint32_t *)devpriv->rps_buf.logical_base;
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/* Initialize RPS instruction pointer */
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writel((uint32_t)devpriv->RPSBuf.physical_base,
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writel((uint32_t)devpriv->rps_buf.physical_base,
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devpriv->mmio + P_RPSADDR1);
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/* Construct RPS program in RPSBuf DMA buffer */
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/* Construct RPS program in rps_buf DMA buffer */
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if (cmd != NULL && cmd->scan_begin_src != TRIG_FOLLOW) {
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/* Wait for Start trigger. */
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*pRPS++ = RPS_PAUSE | RPS_SIGADC;
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@ -1001,8 +1001,8 @@ static void ResetADC(struct comedi_device *dev, uint8_t *ppl)
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* for loop to limit the slot count to 16 in case the application
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* forgot to set the EOPL flag in the final slot.
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*/
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for (devpriv->AdcItems = 0; devpriv->AdcItems < 16;
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devpriv->AdcItems++) {
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for (devpriv->adc_items = 0; devpriv->adc_items < 16;
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devpriv->adc_items++) {
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/*
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* Convert application's poll list item to private board class
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* format. Each app poll list item is an uint8_t with form
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@ -1047,9 +1047,10 @@ static void ResetADC(struct comedi_device *dev, uint8_t *ppl)
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* instruction prefetch pipeline.
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*/
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JmpAdrs =
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(uint32_t)devpriv->RPSBuf.physical_base +
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(uint32_t)devpriv->rps_buf.physical_base +
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(uint32_t)((unsigned long)pRPS -
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(unsigned long)devpriv->RPSBuf.logical_base);
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(unsigned long)devpriv->
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rps_buf.logical_base);
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for (i = 0; i < (10 * RPSCLK_PER_US / 2); i++) {
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JmpAdrs += 8; /* Repeat to implement time delay: */
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*pRPS++ = RPS_JUMP; /* Jump to next RPS instruction. */
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@ -1079,15 +1080,15 @@ static void ResetADC(struct comedi_device *dev, uint8_t *ppl)
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/* Transfer ADC data from FB BUFFER 1 register to DMA buffer. */
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*pRPS++ = RPS_STREG | (BUGFIX_STREG(P_FB_BUFFER1) >> 2);
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*pRPS++ = (uint32_t)devpriv->ANABuf.physical_base +
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(devpriv->AdcItems << 2);
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*pRPS++ = (uint32_t)devpriv->ana_buf.physical_base +
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(devpriv->adc_items << 2);
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/*
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* If this slot's EndOfPollList flag is set, all channels have
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* now been processed.
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*/
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if (*ppl++ & EOPL) {
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devpriv->AdcItems++; /* Adjust poll list item count. */
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devpriv->adc_items++; /* Adjust poll list item count. */
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break; /* Exit poll list processing loop. */
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}
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}
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@ -1122,8 +1123,8 @@ static void ResetADC(struct comedi_device *dev, uint8_t *ppl)
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/* Transfer final ADC data from FB BUFFER 1 register to DMA buffer. */
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*pRPS++ = RPS_STREG | (BUGFIX_STREG(P_FB_BUFFER1) >> 2);
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*pRPS++ = (uint32_t)devpriv->ANABuf.physical_base +
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(devpriv->AdcItems << 2);
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*pRPS++ = (uint32_t)devpriv->ana_buf.physical_base +
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(devpriv->adc_items << 2);
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/* Indicate ADC scan loop is finished. */
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/* Signal ReadADC() that scan is done. */
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@ -1135,7 +1136,7 @@ static void ResetADC(struct comedi_device *dev, uint8_t *ppl)
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/* Restart RPS program at its beginning. */
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*pRPS++ = RPS_JUMP; /* Branch to start of RPS program. */
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*pRPS++ = (uint32_t)devpriv->RPSBuf.physical_base;
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*pRPS++ = (uint32_t)devpriv->rps_buf.physical_base;
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/* End of RPS program build */
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}
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@ -1162,13 +1163,13 @@ static int s626_ai_rinsn(struct comedi_device *dev,
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* first uint16_t in the buffer because it contains junk data from
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* the final ADC of the previous poll list scan.
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*/
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readaddr = (uint32_t *)devpriv->ANABuf.logical_base + 1;
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readaddr = (uint32_t *)devpriv->ana_buf.logical_base + 1;
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/*
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* Convert ADC data to 16-bit integer values and
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* copy to application buffer.
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*/
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for (i = 0; i < devpriv->AdcItems; i++) {
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for (i = 0; i < devpriv->adc_items; i++) {
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*data = s626_ai_reg_to_uint(*readaddr++);
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data++;
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}
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@ -2022,7 +2023,7 @@ static void SetMode_A(struct comedi_device *dev, struct enc_private *k,
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* enable mask to indicate the counter interrupt is disabled.
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*/
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if (DisableIntSrc)
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devpriv->CounterIntEnabs &= ~k->MyEventBits[3];
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devpriv->counter_int_enabs &= ~k->MyEventBits[3];
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/*
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* While retaining CounterB and LatchSrc configurations, program the
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@ -2109,7 +2110,7 @@ static void SetMode_B(struct comedi_device *dev, struct enc_private *k,
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* enable mask to indicate the counter interrupt is disabled.
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*/
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if (DisableIntSrc)
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devpriv->CounterIntEnabs &= ~k->MyEventBits[3];
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devpriv->counter_int_enabs &= ~k->MyEventBits[3];
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/*
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* While retaining CounterA and LatchSrc configurations, program the
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@ -2202,8 +2203,8 @@ static void SetIntSrc_A(struct comedi_device *dev, struct enc_private *k,
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IntSource << CRABIT_INTSRC_A);
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/* Update MISC2 interrupt enable mask. */
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devpriv->CounterIntEnabs =
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(devpriv->CounterIntEnabs & ~k->
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devpriv->counter_int_enabs =
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(devpriv->counter_int_enabs & ~k->
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MyEventBits[3]) | k->MyEventBits[IntSource];
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}
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@ -2226,8 +2227,8 @@ static void SetIntSrc_B(struct comedi_device *dev, struct enc_private *k,
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(IntSource << CRBBIT_INTSRC_B)));
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/* Update MISC2 interrupt enable mask. */
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devpriv->CounterIntEnabs =
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(devpriv->CounterIntEnabs & ~k->MyEventBits[3]) |
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devpriv->counter_int_enabs =
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(devpriv->counter_int_enabs & ~k->MyEventBits[3]) |
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k->MyEventBits[IntSource];
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}
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@ -2470,14 +2471,14 @@ static int s626_allocate_dma_buffers(struct comedi_device *dev)
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addr = pci_alloc_consistent(pcidev, DMABUF_SIZE, &appdma);
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if (!addr)
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return -ENOMEM;
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devpriv->ANABuf.logical_base = addr;
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devpriv->ANABuf.physical_base = appdma;
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devpriv->ana_buf.logical_base = addr;
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devpriv->ana_buf.physical_base = appdma;
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addr = pci_alloc_consistent(pcidev, DMABUF_SIZE, &appdma);
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if (!addr)
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return -ENOMEM;
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devpriv->RPSBuf.logical_base = addr;
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devpriv->RPSBuf.physical_base = appdma;
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devpriv->rps_buf.logical_base = addr;
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devpriv->rps_buf.physical_base = appdma;
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return 0;
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}
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@ -2510,7 +2511,7 @@ static void s626_initialize(struct comedi_device *dev)
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writel(GPIO_BASE | GPIO1_HI, devpriv->mmio + P_GPIO);
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/* I2C device address for onboard eeprom (revb) */
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devpriv->I2CAdrs = 0xA0;
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devpriv->i2c_adrs = 0xA0;
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/*
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* Issue an I2C ABORT command to halt any I2C
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@ -2557,7 +2558,7 @@ static void s626_initialize(struct comedi_device *dev)
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*/
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/* Physical start of RPS program */
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writel((uint32_t)devpriv->RPSBuf.physical_base,
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writel((uint32_t)devpriv->rps_buf.physical_base,
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devpriv->mmio + P_RPSADDR1);
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/* RPS program performs no explicit mem writes */
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writel(0, devpriv->mmio + P_RPSPAGE1);
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@ -2625,7 +2626,7 @@ static void s626_initialize(struct comedi_device *dev)
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* single DWORD will be transferred each time a DMA transfer is
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* enabled.
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*/
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pPhysBuf = devpriv->ANABuf.physical_base +
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pPhysBuf = devpriv->ana_buf.physical_base +
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(DAC_WDMABUF_OS * sizeof(uint32_t));
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writel((uint32_t)pPhysBuf, devpriv->mmio + P_BASEA2_OUT);
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writel((uint32_t)(pPhysBuf + sizeof(uint32_t)),
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@ -2635,7 +2636,7 @@ static void s626_initialize(struct comedi_device *dev)
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* Cache Audio2's output DMA buffer logical address. This is
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* where DAC data is buffered for A2 output DMA transfers.
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*/
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devpriv->pDacWBuf = (uint32_t *)devpriv->ANABuf.logical_base +
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devpriv->dac_wbuf = (uint32_t *)devpriv->ana_buf.logical_base +
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DAC_WDMABUF_OS;
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/*
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@ -2863,8 +2864,8 @@ static void s626_detach(struct comedi_device *dev)
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writel(MC1_SHUTDOWN, devpriv->mmio + P_MC1);
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writel(ACON1_BASE, devpriv->mmio + P_ACON1);
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CloseDMAB(dev, &devpriv->RPSBuf, DMABUF_SIZE);
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CloseDMAB(dev, &devpriv->ANABuf, DMABUF_SIZE);
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CloseDMAB(dev, &devpriv->rps_buf, DMABUF_SIZE);
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CloseDMAB(dev, &devpriv->ana_buf, DMABUF_SIZE);
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}
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if (dev->irq)
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