mirror of https://gitee.com/openkylin/linux.git
PCI/AER: Use "aer" variable for capability offset
Previously we used "pos" or "aer_pos" for the offset of the AER Capability. Use "aer" consistently and initialize it the same way everywhere. No functional change intended. Link: https://lore.kernel.org/r/20200529230915.GA479883@bjorn-Precision-5520 Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
This commit is contained in:
Bjorn Helgaas
parent
af10cce7ad
commit
07b2fbb565
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@ -136,19 +136,18 @@ static const char * const ecrc_policy_str[] = {
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*/
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static int enable_ecrc_checking(struct pci_dev *dev)
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{
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int pos;
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int aer = dev->aer_cap;
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u32 reg32;
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pos = dev->aer_cap;
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if (!pos)
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if (!aer)
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return -ENODEV;
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pci_read_config_dword(dev, pos + PCI_ERR_CAP, ®32);
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pci_read_config_dword(dev, aer + PCI_ERR_CAP, ®32);
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if (reg32 & PCI_ERR_CAP_ECRC_GENC)
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reg32 |= PCI_ERR_CAP_ECRC_GENE;
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if (reg32 & PCI_ERR_CAP_ECRC_CHKC)
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reg32 |= PCI_ERR_CAP_ECRC_CHKE;
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pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32);
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pci_write_config_dword(dev, aer + PCI_ERR_CAP, reg32);
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return 0;
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}
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@ -161,16 +160,15 @@ static int enable_ecrc_checking(struct pci_dev *dev)
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*/
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static int disable_ecrc_checking(struct pci_dev *dev)
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{
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int pos;
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int aer = dev->aer_cap;
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u32 reg32;
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pos = dev->aer_cap;
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if (!pos)
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if (!aer)
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return -ENODEV;
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pci_read_config_dword(dev, pos + PCI_ERR_CAP, ®32);
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pci_read_config_dword(dev, aer + PCI_ERR_CAP, ®32);
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reg32 &= ~(PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE);
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pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32);
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pci_write_config_dword(dev, aer + PCI_ERR_CAP, reg32);
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return 0;
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}
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@ -253,18 +251,18 @@ void pci_aer_clear_device_status(struct pci_dev *dev)
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int pci_aer_clear_nonfatal_status(struct pci_dev *dev)
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{
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int pos = dev->aer_cap;
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int aer = dev->aer_cap;
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u32 status, sev;
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if (!pcie_aer_is_native(dev))
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return -EIO;
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/* Clear status bits for ERR_NONFATAL errors only */
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pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, &status);
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pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &sev);
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pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);
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pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, &sev);
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status &= ~sev;
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if (status)
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pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, status);
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pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, status);
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return 0;
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}
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@ -272,18 +270,18 @@ EXPORT_SYMBOL_GPL(pci_aer_clear_nonfatal_status);
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void pci_aer_clear_fatal_status(struct pci_dev *dev)
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{
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int pos = dev->aer_cap;
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int aer = dev->aer_cap;
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u32 status, sev;
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if (!pcie_aer_is_native(dev))
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return;
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/* Clear status bits for ERR_FATAL errors only */
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pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, &status);
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pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &sev);
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pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);
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pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, &sev);
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status &= sev;
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if (status)
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pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, status);
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pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, status);
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}
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/**
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@ -297,25 +295,24 @@ void pci_aer_clear_fatal_status(struct pci_dev *dev)
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*/
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int pci_aer_raw_clear_status(struct pci_dev *dev)
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{
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int pos;
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int aer = dev->aer_cap;
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u32 status;
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int port_type;
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pos = dev->aer_cap;
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if (!pos)
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if (!aer)
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return -EIO;
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port_type = pci_pcie_type(dev);
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if (port_type == PCI_EXP_TYPE_ROOT_PORT) {
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pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &status);
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pci_write_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, status);
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pci_read_config_dword(dev, aer + PCI_ERR_ROOT_STATUS, &status);
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pci_write_config_dword(dev, aer + PCI_ERR_ROOT_STATUS, status);
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}
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pci_read_config_dword(dev, pos + PCI_ERR_COR_STATUS, &status);
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pci_write_config_dword(dev, pos + PCI_ERR_COR_STATUS, status);
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pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS, &status);
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pci_write_config_dword(dev, aer + PCI_ERR_COR_STATUS, status);
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pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, &status);
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pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, status);
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pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);
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pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, status);
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return 0;
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}
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@ -330,12 +327,11 @@ int pci_aer_clear_status(struct pci_dev *dev)
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void pci_save_aer_state(struct pci_dev *dev)
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{
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int aer = dev->aer_cap;
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struct pci_cap_saved_state *save_state;
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u32 *cap;
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int pos;
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pos = dev->aer_cap;
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if (!pos)
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if (!aer)
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return;
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save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_ERR);
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@ -343,22 +339,21 @@ void pci_save_aer_state(struct pci_dev *dev)
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return;
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cap = &save_state->cap.data[0];
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pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, cap++);
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pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, cap++);
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pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, cap++);
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pci_read_config_dword(dev, pos + PCI_ERR_CAP, cap++);
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pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, cap++);
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pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, cap++);
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pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, cap++);
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pci_read_config_dword(dev, aer + PCI_ERR_CAP, cap++);
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if (pcie_cap_has_rtctl(dev))
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pci_read_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, cap++);
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pci_read_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, cap++);
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}
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void pci_restore_aer_state(struct pci_dev *dev)
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{
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int aer = dev->aer_cap;
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struct pci_cap_saved_state *save_state;
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u32 *cap;
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int pos;
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pos = dev->aer_cap;
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if (!pos)
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if (!aer)
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return;
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save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_ERR);
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@ -366,12 +361,12 @@ void pci_restore_aer_state(struct pci_dev *dev)
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return;
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cap = &save_state->cap.data[0];
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pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, *cap++);
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pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, *cap++);
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pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, *cap++);
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pci_write_config_dword(dev, pos + PCI_ERR_CAP, *cap++);
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pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, *cap++);
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pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, *cap++);
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pci_write_config_dword(dev, aer + PCI_ERR_COR_MASK, *cap++);
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pci_write_config_dword(dev, aer + PCI_ERR_CAP, *cap++);
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if (pcie_cap_has_rtctl(dev))
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pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, *cap++);
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pci_write_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, *cap++);
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}
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void pci_aer_init(struct pci_dev *dev)
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@ -802,7 +797,7 @@ static int add_error_device(struct aer_err_info *e_info, struct pci_dev *dev)
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*/
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static bool is_error_source(struct pci_dev *dev, struct aer_err_info *e_info)
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{
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int pos;
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int aer = dev->aer_cap;
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u32 status, mask;
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u16 reg16;
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@ -837,17 +832,16 @@ static bool is_error_source(struct pci_dev *dev, struct aer_err_info *e_info)
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if (!(reg16 & PCI_EXP_AER_FLAGS))
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return false;
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pos = dev->aer_cap;
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if (!pos)
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if (!aer)
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return false;
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/* Check if error is recorded */
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if (e_info->severity == AER_CORRECTABLE) {
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pci_read_config_dword(dev, pos + PCI_ERR_COR_STATUS, &status);
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pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, &mask);
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pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS, &status);
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pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, &mask);
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} else {
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pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, &status);
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pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, &mask);
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pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);
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pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &mask);
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}
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if (status & ~mask)
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return true;
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@ -918,16 +912,15 @@ static bool find_source_device(struct pci_dev *parent,
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*/
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static void handle_error_source(struct pci_dev *dev, struct aer_err_info *info)
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{
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int pos;
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int aer = dev->aer_cap;
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if (info->severity == AER_CORRECTABLE) {
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/*
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* Correctable error does not need software intervention.
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* No need to go through error recovery process.
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*/
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pos = dev->aer_cap;
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if (pos)
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pci_write_config_dword(dev, pos + PCI_ERR_COR_STATUS,
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if (aer)
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pci_write_config_dword(dev, aer + PCI_ERR_COR_STATUS,
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info->status);
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pci_aer_clear_device_status(dev);
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} else if (info->severity == AER_NONFATAL)
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@ -1018,22 +1011,21 @@ EXPORT_SYMBOL_GPL(aer_recover_queue);
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*/
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int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info)
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{
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int pos, temp;
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int aer = dev->aer_cap;
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int temp;
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/* Must reset in this function */
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info->status = 0;
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info->tlp_header_valid = 0;
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pos = dev->aer_cap;
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/* The device might not support AER */
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if (!pos)
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if (!aer)
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return 0;
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if (info->severity == AER_CORRECTABLE) {
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pci_read_config_dword(dev, pos + PCI_ERR_COR_STATUS,
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pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS,
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&info->status);
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pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK,
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pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK,
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&info->mask);
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if (!(info->status & ~info->mask))
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return 0;
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@ -1042,27 +1034,27 @@ int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info)
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info->severity == AER_NONFATAL) {
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/* Link is still healthy for IO reads */
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pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS,
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pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS,
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&info->status);
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pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK,
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pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK,
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&info->mask);
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if (!(info->status & ~info->mask))
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return 0;
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/* Get First Error Pointer */
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pci_read_config_dword(dev, pos + PCI_ERR_CAP, &temp);
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pci_read_config_dword(dev, aer + PCI_ERR_CAP, &temp);
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info->first_error = PCI_ERR_CAP_FEP(temp);
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if (info->status & AER_LOG_TLP_MASKS) {
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info->tlp_header_valid = 1;
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pci_read_config_dword(dev,
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pos + PCI_ERR_HEADER_LOG, &info->tlp.dw0);
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aer + PCI_ERR_HEADER_LOG, &info->tlp.dw0);
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pci_read_config_dword(dev,
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pos + PCI_ERR_HEADER_LOG + 4, &info->tlp.dw1);
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aer + PCI_ERR_HEADER_LOG + 4, &info->tlp.dw1);
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pci_read_config_dword(dev,
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pos + PCI_ERR_HEADER_LOG + 8, &info->tlp.dw2);
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aer + PCI_ERR_HEADER_LOG + 8, &info->tlp.dw2);
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pci_read_config_dword(dev,
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pos + PCI_ERR_HEADER_LOG + 12, &info->tlp.dw3);
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aer + PCI_ERR_HEADER_LOG + 12, &info->tlp.dw3);
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}
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}
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@ -1168,15 +1160,15 @@ static irqreturn_t aer_irq(int irq, void *context)
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struct pcie_device *pdev = (struct pcie_device *)context;
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struct aer_rpc *rpc = get_service_data(pdev);
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struct pci_dev *rp = rpc->rpd;
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int aer = rp->aer_cap;
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struct aer_err_source e_src = {};
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int pos = rp->aer_cap;
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pci_read_config_dword(rp, pos + PCI_ERR_ROOT_STATUS, &e_src.status);
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pci_read_config_dword(rp, aer + PCI_ERR_ROOT_STATUS, &e_src.status);
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if (!(e_src.status & (PCI_ERR_ROOT_UNCOR_RCV|PCI_ERR_ROOT_COR_RCV)))
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return IRQ_NONE;
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pci_read_config_dword(rp, pos + PCI_ERR_ROOT_ERR_SRC, &e_src.id);
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pci_write_config_dword(rp, pos + PCI_ERR_ROOT_STATUS, e_src.status);
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pci_read_config_dword(rp, aer + PCI_ERR_ROOT_ERR_SRC, &e_src.id);
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pci_write_config_dword(rp, aer + PCI_ERR_ROOT_STATUS, e_src.status);
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if (!kfifo_put(&rpc->aer_fifo, e_src))
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return IRQ_HANDLED;
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@ -1228,7 +1220,7 @@ static void set_downstream_devices_error_reporting(struct pci_dev *dev,
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static void aer_enable_rootport(struct aer_rpc *rpc)
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{
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struct pci_dev *pdev = rpc->rpd;
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int aer_pos;
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int aer = pdev->aer_cap;
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u16 reg16;
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u32 reg32;
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@ -1240,14 +1232,13 @@ static void aer_enable_rootport(struct aer_rpc *rpc)
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pcie_capability_clear_word(pdev, PCI_EXP_RTCTL,
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SYSTEM_ERROR_INTR_ON_MESG_MASK);
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aer_pos = pdev->aer_cap;
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/* Clear error status */
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pci_read_config_dword(pdev, aer_pos + PCI_ERR_ROOT_STATUS, ®32);
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pci_write_config_dword(pdev, aer_pos + PCI_ERR_ROOT_STATUS, reg32);
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pci_read_config_dword(pdev, aer_pos + PCI_ERR_COR_STATUS, ®32);
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pci_write_config_dword(pdev, aer_pos + PCI_ERR_COR_STATUS, reg32);
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pci_read_config_dword(pdev, aer_pos + PCI_ERR_UNCOR_STATUS, ®32);
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pci_write_config_dword(pdev, aer_pos + PCI_ERR_UNCOR_STATUS, reg32);
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pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, ®32);
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pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, reg32);
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pci_read_config_dword(pdev, aer + PCI_ERR_COR_STATUS, ®32);
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pci_write_config_dword(pdev, aer + PCI_ERR_COR_STATUS, reg32);
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pci_read_config_dword(pdev, aer + PCI_ERR_UNCOR_STATUS, ®32);
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pci_write_config_dword(pdev, aer + PCI_ERR_UNCOR_STATUS, reg32);
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/*
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* Enable error reporting for the root port device and downstream port
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@ -1256,9 +1247,9 @@ static void aer_enable_rootport(struct aer_rpc *rpc)
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set_downstream_devices_error_reporting(pdev, true);
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/* Enable Root Port's interrupt in response to error messages */
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pci_read_config_dword(pdev, aer_pos + PCI_ERR_ROOT_COMMAND, ®32);
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pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, ®32);
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reg32 |= ROOT_PORT_INTR_ON_MESG_MASK;
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pci_write_config_dword(pdev, aer_pos + PCI_ERR_ROOT_COMMAND, reg32);
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pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, reg32);
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}
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/**
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@ -1270,8 +1261,8 @@ static void aer_enable_rootport(struct aer_rpc *rpc)
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static void aer_disable_rootport(struct aer_rpc *rpc)
|
||||
{
|
||||
struct pci_dev *pdev = rpc->rpd;
|
||||
int aer = pdev->aer_cap;
|
||||
u32 reg32;
|
||||
int pos;
|
||||
|
||||
/*
|
||||
* Disable error reporting for the root port device and downstream port
|
||||
|
|
@ -1279,15 +1270,14 @@ static void aer_disable_rootport(struct aer_rpc *rpc)
|
|||
*/
|
||||
set_downstream_devices_error_reporting(pdev, false);
|
||||
|
||||
pos = pdev->aer_cap;
|
||||
/* Disable Root's interrupt in response to error messages */
|
||||
pci_read_config_dword(pdev, pos + PCI_ERR_ROOT_COMMAND, ®32);
|
||||
pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, ®32);
|
||||
reg32 &= ~ROOT_PORT_INTR_ON_MESG_MASK;
|
||||
pci_write_config_dword(pdev, pos + PCI_ERR_ROOT_COMMAND, reg32);
|
||||
pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, reg32);
|
||||
|
||||
/* Clear Root's error status reg */
|
||||
pci_read_config_dword(pdev, pos + PCI_ERR_ROOT_STATUS, ®32);
|
||||
pci_write_config_dword(pdev, pos + PCI_ERR_ROOT_STATUS, reg32);
|
||||
pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, ®32);
|
||||
pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, reg32);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -1344,28 +1334,27 @@ static int aer_probe(struct pcie_device *dev)
|
|||
*/
|
||||
static pci_ers_result_t aer_root_reset(struct pci_dev *dev)
|
||||
{
|
||||
int aer = dev->aer_cap;
|
||||
u32 reg32;
|
||||
int pos;
|
||||
int rc;
|
||||
|
||||
pos = dev->aer_cap;
|
||||
|
||||
/* Disable Root's interrupt in response to error messages */
|
||||
pci_read_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, ®32);
|
||||
pci_read_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, ®32);
|
||||
reg32 &= ~ROOT_PORT_INTR_ON_MESG_MASK;
|
||||
pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, reg32);
|
||||
pci_write_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, reg32);
|
||||
|
||||
rc = pci_bus_error_reset(dev);
|
||||
pci_info(dev, "Root Port link has been reset\n");
|
||||
|
||||
/* Clear Root Error Status */
|
||||
pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, ®32);
|
||||
pci_write_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, reg32);
|
||||
pci_read_config_dword(dev, aer + PCI_ERR_ROOT_STATUS, ®32);
|
||||
pci_write_config_dword(dev, aer + PCI_ERR_ROOT_STATUS, reg32);
|
||||
|
||||
/* Enable Root Port's interrupt in response to error messages */
|
||||
pci_read_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, ®32);
|
||||
pci_read_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, ®32);
|
||||
reg32 |= ROOT_PORT_INTR_ON_MESG_MASK;
|
||||
pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, reg32);
|
||||
pci_write_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, reg32);
|
||||
|
||||
return rc ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue