mirror of https://gitee.com/openkylin/linux.git
ASoC: Fix BCLK calculation of WM8994
This fixes BCLK calculation and removes unnecessary check code. Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> Acked-by: Liam Girdwood <lrg@slimlogic.co.uk> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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@ -3267,15 +3267,12 @@ static int wm8994_hw_params(struct snd_pcm_substream *substream,
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*/
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best = 0;
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for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
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if (bclk_divs[i] < 0)
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continue;
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cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i])
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- bclk_rate * 10;
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cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
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if (cur_val < 0) /* BCLK table is sorted */
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break;
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best = i;
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}
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bclk_rate = wm8994->aifclk[id] / bclk_divs[best];
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bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
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dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
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bclk_divs[best], bclk_rate);
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bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
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