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drm/amd/powerplay: Update CKS on/ CKS off voltage offset calculation 

CKS on/off voltage offset calculation algorithm takes in a few coefficients.
We need to update them for polaris to latest coefficients to align with BB.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Rex Zhu 2016-06-22 21:00:09 +08:00 committed by Alex Deucher
parent 83a7af6dcf
commit 0812a945fb
1 changed files with 17 additions and 9 deletions
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26
drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
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@ -98,6 +98,7 @@
#define PCIE_BUS_CLK 10000
#define TCLK (PCIE_BUS_CLK / 10)
#define CEILING_UCHAR(double) ((double-(uint8_t)(double)) > 0 ? (uint8_t)(double+1) : (uint8_t)(double))
static const uint16_t polaris10_clock_stretcher_lookup_table[2][4] =
{ {600, 1050, 3, 0}, {600, 1050, 6, 1} };
@ -1787,20 +1788,27 @@ static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
ro = efuse * (max -min)/255 + min;
/* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
/* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset
* there is a little difference in calculating
* volt_with_cks with windows */
for (i = 0; i < sclk_table->count; i++) {
data->smc_state_table.Sclk_CKS_masterEn0_7 |=
sclk_table->entries[i].cks_enable << i;
volt_without_cks = (uint32_t)(((ro - 40) * 1000 - 2753594 - sclk_table->entries[i].clk/100 * 136418 /1000) / \
(sclk_table->entries[i].clk/100 * 1132925 /10000 - 242418)/100);
volt_with_cks = (uint32_t)((ro * 1000 -2396351 - sclk_table->entries[i].clk/100 * 329021/1000) / \
(sclk_table->entries[i].clk/10000 * 649434 /1000 - 18005)/10);
if (hwmgr->chip_id == CHIP_POLARIS10) {
volt_without_cks = (uint32_t)((2753594000 + (sclk_table->entries[i].clk/100) * 136418 -(ro - 70) * 1000000) / \
(2424180 - (sclk_table->entries[i].clk/100) * 1132925/1000));
volt_with_cks = (uint32_t)((279720200 + sclk_table->entries[i].clk * 3232 - (ro - 65) * 100000000) / \
(252248000 - sclk_table->entries[i].clk/100 * 115764));
} else {
volt_without_cks = (uint32_t)((2416794800 + (sclk_table->entries[i].clk/100) * 1476925/10 -(ro - 50) * 1000000) / \
(2625416 - (sclk_table->entries[i].clk/100) * 12586807/10000));
volt_with_cks = (uint32_t)((2999656000 + sclk_table->entries[i].clk * 392803/100 - (ro - 44) * 1000000) / \
(3422454 - sclk_table->entries[i].clk/100 * 18886376/10000));
}
if (volt_without_cks >= volt_with_cks)
volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
sclk_table->entries[i].cks_voffset) * 100 / 625) + 1);
volt_offset = (uint8_t)CEILING_UCHAR((volt_without_cks - volt_with_cks +
sclk_table->entries[i].cks_voffset) * 100 / 625);
data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
}