mirror of https://gitee.com/openkylin/linux.git
ARM: S5P64X0: Add lookup of sdhci-s3c clocks using generic names
Add support for lookup of sdhci-s3c controller clocks using generic names for S5P64X0 SoCs. Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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ebc433c289
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0818c52756
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@ -378,36 +378,6 @@ static struct clksrc_sources clkset_audio = {
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static struct clksrc_clk clksrcs[] = {
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{
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.clk = {
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.name = "sclk_mmc",
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.devname = "s3c-sdhci.0",
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.ctrlbit = (1 << 24),
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.enable = s5p64x0_sclk_ctrl,
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},
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.sources = &clkset_group1,
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.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
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.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
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}, {
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.clk = {
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.name = "sclk_mmc",
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.devname = "s3c-sdhci.1",
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.ctrlbit = (1 << 25),
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.enable = s5p64x0_sclk_ctrl,
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},
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.sources = &clkset_group1,
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.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
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.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
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}, {
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.clk = {
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.name = "sclk_mmc",
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.devname = "s3c-sdhci.2",
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.ctrlbit = (1 << 26),
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.enable = s5p64x0_sclk_ctrl,
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},
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.sources = &clkset_group1,
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.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
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.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
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}, {
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.clk = {
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.name = "sclk_post",
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.ctrlbit = (1 << 10),
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@ -446,6 +416,42 @@ static struct clksrc_clk clksrcs[] = {
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},
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};
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static struct clksrc_clk clk_sclk_mmc0 = {
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.clk = {
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.name = "sclk_mmc",
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.devname = "s3c-sdhci.0",
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.ctrlbit = (1 << 24),
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.enable = s5p64x0_sclk_ctrl,
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},
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.sources = &clkset_group1,
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.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
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.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
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};
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static struct clksrc_clk clk_sclk_mmc1 = {
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.clk = {
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.name = "sclk_mmc",
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.devname = "s3c-sdhci.1",
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.ctrlbit = (1 << 25),
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.enable = s5p64x0_sclk_ctrl,
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},
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.sources = &clkset_group1,
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.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
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.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
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};
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static struct clksrc_clk clk_sclk_mmc2 = {
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.clk = {
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.name = "sclk_mmc",
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.devname = "s3c-sdhci.2",
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.ctrlbit = (1 << 26),
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.enable = s5p64x0_sclk_ctrl,
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},
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.sources = &clkset_group1,
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.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
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.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
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};
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static struct clksrc_clk clk_sclk_uclk = {
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.clk = {
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.name = "uclk1",
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@ -503,6 +509,9 @@ static struct clksrc_clk *clksrc_cdev[] = {
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&clk_sclk_uclk,
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&clk_sclk_spi0,
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&clk_sclk_spi1,
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&clk_sclk_mmc0,
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&clk_sclk_mmc1,
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&clk_sclk_mmc2
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};
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static struct clk_lookup s5p6440_clk_lookup[] = {
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@ -511,6 +520,9 @@ static struct clk_lookup s5p6440_clk_lookup[] = {
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CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
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CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
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CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
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CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
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CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
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CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
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};
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void __init_or_cpufreq s5p6440_setup_clocks(void)
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@ -412,36 +412,6 @@ static struct clksrc_clk clk_sclk_audio0 = {
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static struct clksrc_clk clksrcs[] = {
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{
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.clk = {
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.name = "sclk_mmc",
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.devname = "s3c-sdhci.0",
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.ctrlbit = (1 << 24),
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.enable = s5p64x0_sclk_ctrl,
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},
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.sources = &clkset_group2,
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.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
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.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
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}, {
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.clk = {
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.name = "sclk_mmc",
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.devname = "s3c-sdhci.1",
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.ctrlbit = (1 << 25),
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.enable = s5p64x0_sclk_ctrl,
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},
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.sources = &clkset_group2,
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.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
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.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
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}, {
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.clk = {
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.name = "sclk_mmc",
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.devname = "s3c-sdhci.2",
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.ctrlbit = (1 << 26),
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.enable = s5p64x0_sclk_ctrl,
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},
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.sources = &clkset_group2,
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.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
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.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
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}, {
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.clk = {
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.name = "sclk_fimc",
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.ctrlbit = (1 << 10),
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@ -507,6 +477,42 @@ static struct clksrc_clk clksrcs[] = {
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},
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};
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static struct clksrc_clk clk_sclk_mmc0 = {
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.clk = {
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.name = "sclk_mmc",
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.devname = "s3c-sdhci.0",
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.ctrlbit = (1 << 24),
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.enable = s5p64x0_sclk_ctrl,
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},
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.sources = &clkset_group2,
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.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
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.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
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};
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static struct clksrc_clk clk_sclk_mmc1 = {
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.clk = {
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.name = "sclk_mmc",
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.devname = "s3c-sdhci.1",
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.ctrlbit = (1 << 25),
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.enable = s5p64x0_sclk_ctrl,
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},
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.sources = &clkset_group2,
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.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
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.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
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};
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static struct clksrc_clk clk_sclk_mmc2 = {
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.clk = {
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.name = "sclk_mmc",
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.devname = "s3c-sdhci.2",
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.ctrlbit = (1 << 26),
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.enable = s5p64x0_sclk_ctrl,
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},
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.sources = &clkset_group2,
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.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
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.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
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};
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static struct clksrc_clk clk_sclk_uclk = {
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.clk = {
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.name = "uclk1",
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@ -546,6 +552,9 @@ static struct clksrc_clk *clksrc_cdev[] = {
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&clk_sclk_uclk,
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&clk_sclk_spi0,
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&clk_sclk_spi1,
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&clk_sclk_mmc0,
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&clk_sclk_mmc1,
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&clk_sclk_mmc2,
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};
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static struct clk_lookup s5p6450_clk_lookup[] = {
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@ -554,6 +563,9 @@ static struct clk_lookup s5p6450_clk_lookup[] = {
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CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
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CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
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CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
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CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
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CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
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CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
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};
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/* Clock initialization code */
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