mirror of https://gitee.com/openkylin/linux.git
drm/i2c: tda998x: fix sync generation and calculation
This fixes the wrong sync generation and sync calculation of TDA998x for HS/VS-based sync detection. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Darren Etheridge <detheridge@ti.com> Tested-by: Russell King <rmk_kernel@arm.linux.org.uk> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Sebastian Hesselbarth
Dave Airlie
parent
c4c11dd160
commit
088d61d1fd
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@ -140,8 +140,12 @@ struct tda998x_priv {
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#define REG_VS_LINE_END_1_LSB REG(0x00, 0xae) /* write */
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#define REG_VS_PIX_END_1_MSB REG(0x00, 0xaf) /* write */
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#define REG_VS_PIX_END_1_LSB REG(0x00, 0xb0) /* write */
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#define REG_VS_LINE_STRT_2_MSB REG(0x00, 0xb1) /* write */
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#define REG_VS_LINE_STRT_2_LSB REG(0x00, 0xb2) /* write */
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#define REG_VS_PIX_STRT_2_MSB REG(0x00, 0xb3) /* write */
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#define REG_VS_PIX_STRT_2_LSB REG(0x00, 0xb4) /* write */
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#define REG_VS_LINE_END_2_MSB REG(0x00, 0xb5) /* write */
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#define REG_VS_LINE_END_2_LSB REG(0x00, 0xb6) /* write */
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#define REG_VS_PIX_END_2_MSB REG(0x00, 0xb7) /* write */
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#define REG_VS_PIX_END_2_LSB REG(0x00, 0xb8) /* write */
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#define REG_HS_PIX_START_MSB REG(0x00, 0xb9) /* write */
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@ -152,21 +156,29 @@ struct tda998x_priv {
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#define REG_VWIN_START_1_LSB REG(0x00, 0xbe) /* write */
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#define REG_VWIN_END_1_MSB REG(0x00, 0xbf) /* write */
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#define REG_VWIN_END_1_LSB REG(0x00, 0xc0) /* write */
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#define REG_VWIN_START_2_MSB REG(0x00, 0xc1) /* write */
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#define REG_VWIN_START_2_LSB REG(0x00, 0xc2) /* write */
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#define REG_VWIN_END_2_MSB REG(0x00, 0xc3) /* write */
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#define REG_VWIN_END_2_LSB REG(0x00, 0xc4) /* write */
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#define REG_DE_START_MSB REG(0x00, 0xc5) /* write */
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#define REG_DE_START_LSB REG(0x00, 0xc6) /* write */
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#define REG_DE_STOP_MSB REG(0x00, 0xc7) /* write */
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#define REG_DE_STOP_LSB REG(0x00, 0xc8) /* write */
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#define REG_TBG_CNTRL_0 REG(0x00, 0xca) /* write */
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# define TBG_CNTRL_0_TOP_TGL (1 << 0)
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# define TBG_CNTRL_0_TOP_SEL (1 << 1)
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# define TBG_CNTRL_0_DE_EXT (1 << 2)
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# define TBG_CNTRL_0_TOP_EXT (1 << 3)
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# define TBG_CNTRL_0_FRAME_DIS (1 << 5)
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# define TBG_CNTRL_0_SYNC_MTHD (1 << 6)
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# define TBG_CNTRL_0_SYNC_ONCE (1 << 7)
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#define REG_TBG_CNTRL_1 REG(0x00, 0xcb) /* write */
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# define TBG_CNTRL_1_VH_TGL_0 (1 << 0)
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# define TBG_CNTRL_1_VH_TGL_1 (1 << 1)
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# define TBG_CNTRL_1_VH_TGL_2 (1 << 2)
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# define TBG_CNTRL_1_VHX_EXT_DE (1 << 3)
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# define TBG_CNTRL_1_VHX_EXT_HS (1 << 4)
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# define TBG_CNTRL_1_VHX_EXT_VS (1 << 5)
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# define TBG_CNTRL_1_H_TGL (1 << 0)
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# define TBG_CNTRL_1_V_TGL (1 << 1)
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# define TBG_CNTRL_1_TGL_EN (1 << 2)
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# define TBG_CNTRL_1_X_EXT (1 << 3)
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# define TBG_CNTRL_1_H_EXT (1 << 4)
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# define TBG_CNTRL_1_V_EXT (1 << 5)
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# define TBG_CNTRL_1_DWIN_DIS (1 << 6)
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#define REG_ENABLE_SPACE REG(0x00, 0xd6) /* write */
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#define REG_HVF_CNTRL_0 REG(0x00, 0xe4) /* write */
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@ -735,43 +747,70 @@ tda998x_encoder_mode_set(struct drm_encoder *encoder,
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struct drm_display_mode *adjusted_mode)
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{
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struct tda998x_priv *priv = to_tda998x_priv(encoder);
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uint16_t hs_start, hs_end, line_start, line_end;
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uint16_t vwin_start, vwin_end, de_start, de_end;
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uint16_t ref_pix, ref_line, pix_start2;
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uint16_t ref_pix, ref_line, n_pix, n_line;
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uint16_t hs_pix_s, hs_pix_e;
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uint16_t vs1_pix_s, vs1_pix_e, vs1_line_s, vs1_line_e;
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uint16_t vs2_pix_s, vs2_pix_e, vs2_line_s, vs2_line_e;
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uint16_t vwin1_line_s, vwin1_line_e;
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uint16_t vwin2_line_s, vwin2_line_e;
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uint16_t de_pix_s, de_pix_e;
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uint8_t reg, div, rep;
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hs_start = mode->hsync_start - mode->hdisplay;
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hs_end = mode->hsync_end - mode->hdisplay;
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line_start = 1;
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line_end = 1 + mode->vsync_end - mode->vsync_start;
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vwin_start = mode->vtotal - mode->vsync_start;
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vwin_end = vwin_start + mode->vdisplay;
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de_start = mode->htotal - mode->hdisplay;
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de_end = mode->htotal;
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pix_start2 = 0;
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if (mode->flags & DRM_MODE_FLAG_INTERLACE)
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pix_start2 = (mode->htotal / 2) + hs_start;
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/* TODO how is this value calculated? It is 2 for all common
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* formats in the tables in out of tree nxp driver (assuming
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* I've properly deciphered their byzantine table system)
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/*
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* Internally TDA998x is using ITU-R BT.656 style sync but
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* we get VESA style sync. TDA998x is using a reference pixel
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* relative to ITU to sync to the input frame and for output
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* sync generation. Currently, we are using reference detection
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* from HS/VS, i.e. REFPIX/REFLINE denote frame start sync point
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* which is position of rising VS with coincident rising HS.
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*
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* Now there is some issues to take care of:
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* - HDMI data islands require sync-before-active
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* - TDA998x register values must be > 0 to be enabled
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* - REFLINE needs an additional offset of +1
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* - REFPIX needs an addtional offset of +1 for UYUV and +3 for RGB
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*
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* So we add +1 to all horizontal and vertical register values,
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* plus an additional +3 for REFPIX as we are using RGB input only.
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*/
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ref_line = 2;
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n_pix = mode->htotal;
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n_line = mode->vtotal;
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/* this might changes for other color formats from the CRTC: */
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ref_pix = 3 + hs_start;
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hs_pix_e = mode->hsync_end - mode->hdisplay;
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hs_pix_s = mode->hsync_start - mode->hdisplay;
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de_pix_e = mode->htotal;
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de_pix_s = mode->htotal - mode->hdisplay;
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ref_pix = 3 + hs_pix_s;
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if ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0) {
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ref_line = 1 + mode->vsync_start - mode->vdisplay;
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vwin1_line_s = mode->vtotal - mode->vdisplay - 1;
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vwin1_line_e = vwin1_line_s + mode->vdisplay;
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vs1_pix_s = vs1_pix_e = hs_pix_s;
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vs1_line_s = mode->vsync_start - mode->vdisplay;
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vs1_line_e = vs1_line_s +
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mode->vsync_end - mode->vsync_start;
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vwin2_line_s = vwin2_line_e = 0;
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vs2_pix_s = vs2_pix_e = 0;
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vs2_line_s = vs2_line_e = 0;
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} else {
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ref_line = 1 + (mode->vsync_start - mode->vdisplay)/2;
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vwin1_line_s = (mode->vtotal - mode->vdisplay)/2;
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vwin1_line_e = vwin1_line_s + mode->vdisplay/2;
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vs1_pix_s = vs1_pix_e = hs_pix_s;
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vs1_line_s = (mode->vsync_start - mode->vdisplay)/2;
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vs1_line_e = vs1_line_s +
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(mode->vsync_end - mode->vsync_start)/2;
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vwin2_line_s = vwin1_line_s + mode->vtotal/2;
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vwin2_line_e = vwin2_line_s + mode->vdisplay/2;
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vs2_pix_s = vs2_pix_e = hs_pix_s + mode->htotal/2;
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vs2_line_s = vs1_line_s + mode->vtotal/2 ;
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vs2_line_e = vs2_line_s +
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(mode->vsync_end - mode->vsync_start)/2;
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}
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div = 148500 / mode->clock;
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DBG("clock=%d, div=%u", mode->clock, div);
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DBG("hs_start=%u, hs_end=%u, line_start=%u, line_end=%u",
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hs_start, hs_end, line_start, line_end);
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DBG("vwin_start=%u, vwin_end=%u, de_start=%u, de_end=%u",
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vwin_start, vwin_end, de_start, de_end);
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DBG("ref_line=%u, ref_pix=%u, pix_start2=%u",
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ref_line, ref_pix, pix_start2);
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/* mute the audio FIFO: */
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reg_set(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
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@ -802,9 +841,6 @@ tda998x_encoder_mode_set(struct drm_encoder *encoder,
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reg_write(encoder, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) |
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PLL_SERIAL_2_SRL_PR(rep));
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reg_write16(encoder, REG_VS_PIX_STRT_2_MSB, pix_start2);
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reg_write16(encoder, REG_VS_PIX_END_2_MSB, pix_start2);
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/* set color matrix bypass flag: */
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reg_set(encoder, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP);
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@ -813,46 +849,59 @@ tda998x_encoder_mode_set(struct drm_encoder *encoder,
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reg_clear(encoder, REG_TBG_CNTRL_0, TBG_CNTRL_0_SYNC_MTHD);
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/*
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* Sync on rising HSYNC/VSYNC
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*/
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reg_write(encoder, REG_VIP_CNTRL_3, 0);
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reg_set(encoder, REG_VIP_CNTRL_3, VIP_CNTRL_3_SYNC_HS);
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/*
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* TDA19988 requires high-active sync at input stage,
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* so invert low-active sync provided by master encoder here
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*/
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if (mode->flags & DRM_MODE_FLAG_NHSYNC)
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reg_set(encoder, REG_VIP_CNTRL_3, VIP_CNTRL_3_H_TGL);
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if (mode->flags & DRM_MODE_FLAG_NVSYNC)
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reg_set(encoder, REG_VIP_CNTRL_3, VIP_CNTRL_3_V_TGL);
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/*
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* Always generate sync polarity relative to input sync and
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* revert input stage toggled sync at output stage
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*/
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reg = TBG_CNTRL_1_TGL_EN;
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if (mode->flags & DRM_MODE_FLAG_NHSYNC)
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reg_set(encoder, REG_VIP_CNTRL_3, VIP_CNTRL_3_H_TGL);
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reg |= TBG_CNTRL_1_H_TGL;
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if (mode->flags & DRM_MODE_FLAG_NVSYNC)
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reg |= TBG_CNTRL_1_V_TGL;
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reg_write(encoder, REG_TBG_CNTRL_1, reg);
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reg_write(encoder, REG_VIDFORMAT, 0x00);
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reg_write16(encoder, REG_NPIX_MSB, mode->htotal);
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reg_write16(encoder, REG_NLINE_MSB, mode->vtotal);
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reg_write16(encoder, REG_VS_LINE_STRT_1_MSB, line_start);
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reg_write16(encoder, REG_VS_LINE_END_1_MSB, line_end);
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reg_write16(encoder, REG_VS_PIX_STRT_1_MSB, hs_start);
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reg_write16(encoder, REG_VS_PIX_END_1_MSB, hs_start);
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reg_write16(encoder, REG_HS_PIX_START_MSB, hs_start);
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reg_write16(encoder, REG_HS_PIX_STOP_MSB, hs_end);
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reg_write16(encoder, REG_VWIN_START_1_MSB, vwin_start);
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reg_write16(encoder, REG_VWIN_END_1_MSB, vwin_end);
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reg_write16(encoder, REG_DE_START_MSB, de_start);
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reg_write16(encoder, REG_DE_STOP_MSB, de_end);
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reg_write16(encoder, REG_REFPIX_MSB, ref_pix);
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reg_write16(encoder, REG_REFLINE_MSB, ref_line);
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reg_write16(encoder, REG_NPIX_MSB, n_pix);
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reg_write16(encoder, REG_NLINE_MSB, n_line);
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reg_write16(encoder, REG_VS_LINE_STRT_1_MSB, vs1_line_s);
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reg_write16(encoder, REG_VS_PIX_STRT_1_MSB, vs1_pix_s);
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reg_write16(encoder, REG_VS_LINE_END_1_MSB, vs1_line_e);
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reg_write16(encoder, REG_VS_PIX_END_1_MSB, vs1_pix_e);
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reg_write16(encoder, REG_VS_LINE_STRT_2_MSB, vs2_line_s);
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reg_write16(encoder, REG_VS_PIX_STRT_2_MSB, vs2_pix_s);
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reg_write16(encoder, REG_VS_LINE_END_2_MSB, vs2_line_e);
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reg_write16(encoder, REG_VS_PIX_END_2_MSB, vs2_pix_e);
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reg_write16(encoder, REG_HS_PIX_START_MSB, hs_pix_s);
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reg_write16(encoder, REG_HS_PIX_STOP_MSB, hs_pix_e);
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reg_write16(encoder, REG_VWIN_START_1_MSB, vwin1_line_s);
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reg_write16(encoder, REG_VWIN_END_1_MSB, vwin1_line_e);
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reg_write16(encoder, REG_VWIN_START_2_MSB, vwin2_line_s);
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reg_write16(encoder, REG_VWIN_END_2_MSB, vwin2_line_e);
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reg_write16(encoder, REG_DE_START_MSB, de_pix_s);
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reg_write16(encoder, REG_DE_STOP_MSB, de_pix_e);
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if (priv->rev == TDA19988) {
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/* let incoming pixels fill the active space (if any) */
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reg_write(encoder, REG_ENABLE_SPACE, 0x01);
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}
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reg_write16(encoder, REG_REFPIX_MSB, ref_pix);
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reg_write16(encoder, REG_REFLINE_MSB, ref_line);
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reg = TBG_CNTRL_1_DWIN_DIS | /* HDCP off */
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TBG_CNTRL_1_VH_TGL_2;
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/*
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* It is questionable whether this is correct - the nxp driver
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* does not set VH_TGL_2 and the below for all display modes.
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*/
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if (mode->flags & (DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC))
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reg |= TBG_CNTRL_1_VH_TGL_0;
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reg_set(encoder, REG_TBG_CNTRL_1, reg);
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/* must be last register set: */
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reg_clear(encoder, REG_TBG_CNTRL_0, TBG_CNTRL_0_SYNC_ONCE);
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