mirror of https://gitee.com/openkylin/linux.git
media: atomisp: get rid of version-specific system_local.h
After removing the unused 32-bits data, the isp2401_system_local.h now contains everything that it is needed, either by isp2401 or by isp2400. So, remove code duplication. Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
This commit is contained in:
Mauro Carvalho Chehab
parent
4b28ded763
commit
08b2bcc665
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@ -1,149 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Support for Intel Camera Imaging ISP subsystem.
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* Copyright (c) 2010-2015, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef __SYSTEM_LOCAL_H_INCLUDED__
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#define __SYSTEM_LOCAL_H_INCLUDED__
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#ifdef HRT_ISP_CSS_CUSTOM_HOST
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#ifndef HRT_USE_VIR_ADDRS
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#define HRT_USE_VIR_ADDRS
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#endif
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#endif
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#include "system_global.h"
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/*
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* Cell specific address maps
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*/
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#define GP_FIFO_BASE ((hrt_address)0x0000000000090104) /* This is NOT a base address */
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/* ISP */
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static const hrt_address ISP_CTRL_BASE[N_ISP_ID] = {
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(hrt_address)0x0000000000020000ULL
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};
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static const hrt_address ISP_DMEM_BASE[N_ISP_ID] = {
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(hrt_address)0x0000000000200000ULL
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};
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static const hrt_address ISP_BAMEM_BASE[N_BAMEM_ID] = {
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(hrt_address)0x0000000000100000ULL
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};
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/* SP */
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static const hrt_address SP_CTRL_BASE[N_SP_ID] = {
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(hrt_address)0x0000000000010000ULL
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};
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static const hrt_address SP_DMEM_BASE[N_SP_ID] = {
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(hrt_address)0x0000000000300000ULL
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};
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/* MMU */
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/*
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* MMU0_ID: The data MMU
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* MMU1_ID: The icache MMU
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*/
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static const hrt_address MMU_BASE[N_MMU_ID] = {
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(hrt_address)0x0000000000070000ULL,
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(hrt_address)0x00000000000A0000ULL
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};
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/* DMA */
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static const hrt_address DMA_BASE[N_DMA_ID] = {
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(hrt_address)0x0000000000040000ULL
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};
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/* IRQ */
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static const hrt_address IRQ_BASE[N_IRQ_ID] = {
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(hrt_address)0x0000000000000500ULL,
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(hrt_address)0x0000000000030A00ULL,
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(hrt_address)0x000000000008C000ULL,
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(hrt_address)0x0000000000090200ULL
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};
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/*
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(hrt_address)0x0000000000000500ULL};
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*/
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/* GDC */
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static const hrt_address GDC_BASE[N_GDC_ID] = {
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(hrt_address)0x0000000000050000ULL,
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(hrt_address)0x0000000000060000ULL
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};
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/* FIFO_MONITOR (not a subset of GP_DEVICE) */
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static const hrt_address FIFO_MONITOR_BASE[N_FIFO_MONITOR_ID] = {
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(hrt_address)0x0000000000000000ULL
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};
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/*
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static const hrt_address GP_REGS_BASE[N_GP_REGS_ID] = {
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(hrt_address)0x0000000000000000ULL};
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static const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID] = {
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(hrt_address)0x0000000000090000ULL};
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*/
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/* GP_DEVICE (single base for all separate GP_REG instances) */
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static const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID] = {
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(hrt_address)0x0000000000000000ULL
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};
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/*GP TIMER , all timer registers are inter-twined,
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* so, having multiple base addresses for
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* different timers does not help*/
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static const hrt_address GP_TIMER_BASE =
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(hrt_address)0x0000000000000600ULL;
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/* GPIO */
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static const hrt_address GPIO_BASE[N_GPIO_ID] = {
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(hrt_address)0x0000000000000400ULL
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};
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/* TIMED_CTRL */
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static const hrt_address TIMED_CTRL_BASE[N_TIMED_CTRL_ID] = {
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(hrt_address)0x0000000000000100ULL
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};
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/* INPUT_FORMATTER */
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static const hrt_address INPUT_FORMATTER_BASE[N_INPUT_FORMATTER_ID] = {
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(hrt_address)0x0000000000030000ULL,
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(hrt_address)0x0000000000030200ULL,
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(hrt_address)0x0000000000030400ULL,
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(hrt_address)0x0000000000030600ULL
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}; /* memcpy() */
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/* INPUT_SYSTEM */
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static const hrt_address INPUT_SYSTEM_BASE[N_INPUT_SYSTEM_ID] = {
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(hrt_address)0x0000000000080000ULL
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};
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/* (hrt_address)0x0000000000081000ULL, */ /* capture A */
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/* (hrt_address)0x0000000000082000ULL, */ /* capture B */
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/* (hrt_address)0x0000000000083000ULL, */ /* capture C */
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/* (hrt_address)0x0000000000084000ULL, */ /* Acquisition */
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/* (hrt_address)0x0000000000085000ULL, */ /* DMA */
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/* (hrt_address)0x0000000000089000ULL, */ /* ctrl */
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/* (hrt_address)0x000000000008A000ULL, */ /* GP regs */
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/* (hrt_address)0x000000000008B000ULL, */ /* FIFO */
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/* (hrt_address)0x000000000008C000ULL, */ /* IRQ */
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/* RX, the MIPI lane control regs start at offset 0 */
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static const hrt_address RX_BASE[N_RX_ID] = {
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(hrt_address)0x0000000000080100ULL
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};
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#endif /* __SYSTEM_LOCAL_H_INCLUDED__ */
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@ -1,196 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Support for Intel Camera Imaging ISP subsystem.
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* Copyright (c) 2015, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef __SYSTEM_LOCAL_H_INCLUDED__
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#define __SYSTEM_LOCAL_H_INCLUDED__
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#ifdef HRT_ISP_CSS_CUSTOM_HOST
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#ifndef HRT_USE_VIR_ADDRS
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#define HRT_USE_VIR_ADDRS
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#endif
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#endif
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#include "system_global.h"
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/*
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* Cell specific address maps
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*/
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#define GP_FIFO_BASE ((hrt_address)0x0000000000090104) /* This is NOT a base address */
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/* ISP */
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static const hrt_address ISP_CTRL_BASE[N_ISP_ID] = {
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0x0000000000020000ULL
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};
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static const hrt_address ISP_DMEM_BASE[N_ISP_ID] = {
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0x0000000000200000ULL
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};
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static const hrt_address ISP_BAMEM_BASE[N_BAMEM_ID] = {
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0x0000000000100000ULL
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};
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/* SP */
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static const hrt_address SP_CTRL_BASE[N_SP_ID] = {
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0x0000000000010000ULL
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};
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static const hrt_address SP_DMEM_BASE[N_SP_ID] = {
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0x0000000000300000ULL
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};
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/* MMU */
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/*
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* MMU0_ID: The data MMU
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* MMU1_ID: The icache MMU
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*/
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static const hrt_address MMU_BASE[N_MMU_ID] = {
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0x0000000000070000ULL,
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0x00000000000A0000ULL
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};
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/* DMA */
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static const hrt_address DMA_BASE[N_DMA_ID] = {
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0x0000000000040000ULL
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};
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static const hrt_address ISYS2401_DMA_BASE[N_ISYS2401_DMA_ID] = {
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0x00000000000CA000ULL
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};
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/* IRQ */
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static const hrt_address IRQ_BASE[N_IRQ_ID] = {
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0x0000000000000500ULL,
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0x0000000000030A00ULL,
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0x000000000008C000ULL,
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0x0000000000090200ULL
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};
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/*
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0x0000000000000500ULL};
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*/
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/* GDC */
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static const hrt_address GDC_BASE[N_GDC_ID] = {
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0x0000000000050000ULL,
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0x0000000000060000ULL
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};
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/* FIFO_MONITOR (not a subset of GP_DEVICE) */
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static const hrt_address FIFO_MONITOR_BASE[N_FIFO_MONITOR_ID] = {
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0x0000000000000000ULL
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};
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/*
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static const hrt_address GP_REGS_BASE[N_GP_REGS_ID] = {
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0x0000000000000000ULL};
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static const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID] = {
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0x0000000000090000ULL};
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*/
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/* GP_DEVICE (single base for all separate GP_REG instances) */
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static const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID] = {
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0x0000000000000000ULL
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};
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/*GP TIMER , all timer registers are inter-twined,
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* so, having multiple base addresses for
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* different timers does not help*/
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static const hrt_address GP_TIMER_BASE =
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(hrt_address)0x0000000000000600ULL;
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/* GPIO */
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static const hrt_address GPIO_BASE[N_GPIO_ID] = {
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0x0000000000000400ULL
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};
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/* TIMED_CTRL */
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static const hrt_address TIMED_CTRL_BASE[N_TIMED_CTRL_ID] = {
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0x0000000000000100ULL
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};
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/* INPUT_FORMATTER */
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static const hrt_address INPUT_FORMATTER_BASE[N_INPUT_FORMATTER_ID] = {
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0x0000000000030000ULL,
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0x0000000000030200ULL,
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0x0000000000030400ULL,
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0x0000000000030600ULL
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}; /* memcpy() */
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/* INPUT_SYSTEM */
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static const hrt_address INPUT_SYSTEM_BASE[N_INPUT_SYSTEM_ID] = {
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0x0000000000080000ULL
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};
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/* 0x0000000000081000ULL, */ /* capture A */
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/* 0x0000000000082000ULL, */ /* capture B */
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/* 0x0000000000083000ULL, */ /* capture C */
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/* 0x0000000000084000ULL, */ /* Acquisition */
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/* 0x0000000000085000ULL, */ /* DMA */
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/* 0x0000000000089000ULL, */ /* ctrl */
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/* 0x000000000008A000ULL, */ /* GP regs */
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/* 0x000000000008B000ULL, */ /* FIFO */
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/* 0x000000000008C000ULL, */ /* IRQ */
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/* RX, the MIPI lane control regs start at offset 0 */
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static const hrt_address RX_BASE[N_RX_ID] = {
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0x0000000000080100ULL
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};
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/* IBUF_CTRL, part of the Input System 2401 */
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static const hrt_address IBUF_CTRL_BASE[N_IBUF_CTRL_ID] = {
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0x00000000000C1800ULL, /* ibuf controller A */
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0x00000000000C3800ULL, /* ibuf controller B */
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0x00000000000C5800ULL /* ibuf controller C */
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};
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/* ISYS IRQ Controllers, part of the Input System 2401 */
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static const hrt_address ISYS_IRQ_BASE[N_ISYS_IRQ_ID] = {
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0x00000000000C1400ULL, /* port a */
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0x00000000000C3400ULL, /* port b */
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0x00000000000C5400ULL /* port c */
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};
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/* CSI FE, part of the Input System 2401 */
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static const hrt_address CSI_RX_FE_CTRL_BASE[N_CSI_RX_FRONTEND_ID] = {
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0x00000000000C0400ULL, /* csi fe controller A */
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0x00000000000C2400ULL, /* csi fe controller B */
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0x00000000000C4400ULL /* csi fe controller C */
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};
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/* CSI BE, part of the Input System 2401 */
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static const hrt_address CSI_RX_BE_CTRL_BASE[N_CSI_RX_BACKEND_ID] = {
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0x00000000000C0800ULL, /* csi be controller A */
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0x00000000000C2800ULL, /* csi be controller B */
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0x00000000000C4800ULL /* csi be controller C */
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};
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/* PIXEL Generator, part of the Input System 2401 */
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static const hrt_address PIXELGEN_CTRL_BASE[N_PIXELGEN_ID] = {
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0x00000000000C1000ULL, /* pixel gen controller A */
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0x00000000000C3000ULL, /* pixel gen controller B */
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0x00000000000C5000ULL /* pixel gen controller C */
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};
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/* Stream2MMIO, part of the Input System 2401 */
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static const hrt_address STREAM2MMIO_CTRL_BASE[N_STREAM2MMIO_ID] = {
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0x00000000000C0C00ULL, /* stream2mmio controller A */
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0x00000000000C2C00ULL, /* stream2mmio controller B */
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0x00000000000C4C00ULL /* stream2mmio controller C */
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};
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#endif /* __SYSTEM_LOCAL_H_INCLUDED__ */
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@ -1,10 +1,199 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* (c) 2020 Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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* Support for Intel Camera Imaging ISP subsystem.
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* Copyright (c) 2015, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
|
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* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*/
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#ifdef ISP2401
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# include "isp2401_system_local.h"
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#else
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# include "isp2400_system_local.h"
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#ifndef __SYSTEM_LOCAL_H_INCLUDED__
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#define __SYSTEM_LOCAL_H_INCLUDED__
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#ifdef HRT_ISP_CSS_CUSTOM_HOST
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#ifndef HRT_USE_VIR_ADDRS
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#define HRT_USE_VIR_ADDRS
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#endif
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#endif
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#include "system_global.h"
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/* This interface is deprecated */
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#include "hive_types.h"
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/*
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* Cell specific address maps
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*/
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|
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#define GP_FIFO_BASE ((hrt_address)0x0000000000090104) /* This is NOT a base address */
|
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|
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/* ISP */
|
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static const hrt_address ISP_CTRL_BASE[N_ISP_ID] = {
|
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0x0000000000020000ULL
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};
|
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|
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static const hrt_address ISP_DMEM_BASE[N_ISP_ID] = {
|
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0x0000000000200000ULL
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};
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|
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static const hrt_address ISP_BAMEM_BASE[N_BAMEM_ID] = {
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0x0000000000100000ULL
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};
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/* SP */
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static const hrt_address SP_CTRL_BASE[N_SP_ID] = {
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0x0000000000010000ULL
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};
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static const hrt_address SP_DMEM_BASE[N_SP_ID] = {
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0x0000000000300000ULL
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};
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|
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/* MMU */
|
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/*
|
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* MMU0_ID: The data MMU
|
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* MMU1_ID: The icache MMU
|
||||
*/
|
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static const hrt_address MMU_BASE[N_MMU_ID] = {
|
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0x0000000000070000ULL,
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0x00000000000A0000ULL
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};
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/* DMA */
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static const hrt_address DMA_BASE[N_DMA_ID] = {
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0x0000000000040000ULL
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};
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static const hrt_address ISYS2401_DMA_BASE[N_ISYS2401_DMA_ID] = {
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0x00000000000CA000ULL
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};
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/* IRQ */
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static const hrt_address IRQ_BASE[N_IRQ_ID] = {
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0x0000000000000500ULL,
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0x0000000000030A00ULL,
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0x000000000008C000ULL,
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0x0000000000090200ULL
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};
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/*
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0x0000000000000500ULL};
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*/
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/* GDC */
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static const hrt_address GDC_BASE[N_GDC_ID] = {
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0x0000000000050000ULL,
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0x0000000000060000ULL
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};
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|
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/* FIFO_MONITOR (not a subset of GP_DEVICE) */
|
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static const hrt_address FIFO_MONITOR_BASE[N_FIFO_MONITOR_ID] = {
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0x0000000000000000ULL
|
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};
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|
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/*
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static const hrt_address GP_REGS_BASE[N_GP_REGS_ID] = {
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0x0000000000000000ULL};
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static const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID] = {
|
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0x0000000000090000ULL};
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||||
*/
|
||||
|
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/* GP_DEVICE (single base for all separate GP_REG instances) */
|
||||
static const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID] = {
|
||||
0x0000000000000000ULL
|
||||
};
|
||||
|
||||
/*GP TIMER , all timer registers are inter-twined,
|
||||
* so, having multiple base addresses for
|
||||
* different timers does not help*/
|
||||
static const hrt_address GP_TIMER_BASE =
|
||||
(hrt_address)0x0000000000000600ULL;
|
||||
|
||||
/* GPIO */
|
||||
static const hrt_address GPIO_BASE[N_GPIO_ID] = {
|
||||
0x0000000000000400ULL
|
||||
};
|
||||
|
||||
/* TIMED_CTRL */
|
||||
static const hrt_address TIMED_CTRL_BASE[N_TIMED_CTRL_ID] = {
|
||||
0x0000000000000100ULL
|
||||
};
|
||||
|
||||
/* INPUT_FORMATTER */
|
||||
static const hrt_address INPUT_FORMATTER_BASE[N_INPUT_FORMATTER_ID] = {
|
||||
0x0000000000030000ULL,
|
||||
0x0000000000030200ULL,
|
||||
0x0000000000030400ULL,
|
||||
0x0000000000030600ULL
|
||||
}; /* memcpy() */
|
||||
|
||||
/* INPUT_SYSTEM */
|
||||
static const hrt_address INPUT_SYSTEM_BASE[N_INPUT_SYSTEM_ID] = {
|
||||
0x0000000000080000ULL
|
||||
};
|
||||
|
||||
/* 0x0000000000081000ULL, */ /* capture A */
|
||||
/* 0x0000000000082000ULL, */ /* capture B */
|
||||
/* 0x0000000000083000ULL, */ /* capture C */
|
||||
/* 0x0000000000084000ULL, */ /* Acquisition */
|
||||
/* 0x0000000000085000ULL, */ /* DMA */
|
||||
/* 0x0000000000089000ULL, */ /* ctrl */
|
||||
/* 0x000000000008A000ULL, */ /* GP regs */
|
||||
/* 0x000000000008B000ULL, */ /* FIFO */
|
||||
/* 0x000000000008C000ULL, */ /* IRQ */
|
||||
|
||||
/* RX, the MIPI lane control regs start at offset 0 */
|
||||
static const hrt_address RX_BASE[N_RX_ID] = {
|
||||
0x0000000000080100ULL
|
||||
};
|
||||
|
||||
/* IBUF_CTRL, part of the Input System 2401 */
|
||||
static const hrt_address IBUF_CTRL_BASE[N_IBUF_CTRL_ID] = {
|
||||
0x00000000000C1800ULL, /* ibuf controller A */
|
||||
0x00000000000C3800ULL, /* ibuf controller B */
|
||||
0x00000000000C5800ULL /* ibuf controller C */
|
||||
};
|
||||
|
||||
/* ISYS IRQ Controllers, part of the Input System 2401 */
|
||||
static const hrt_address ISYS_IRQ_BASE[N_ISYS_IRQ_ID] = {
|
||||
0x00000000000C1400ULL, /* port a */
|
||||
0x00000000000C3400ULL, /* port b */
|
||||
0x00000000000C5400ULL /* port c */
|
||||
};
|
||||
|
||||
/* CSI FE, part of the Input System 2401 */
|
||||
static const hrt_address CSI_RX_FE_CTRL_BASE[N_CSI_RX_FRONTEND_ID] = {
|
||||
0x00000000000C0400ULL, /* csi fe controller A */
|
||||
0x00000000000C2400ULL, /* csi fe controller B */
|
||||
0x00000000000C4400ULL /* csi fe controller C */
|
||||
};
|
||||
|
||||
/* CSI BE, part of the Input System 2401 */
|
||||
static const hrt_address CSI_RX_BE_CTRL_BASE[N_CSI_RX_BACKEND_ID] = {
|
||||
0x00000000000C0800ULL, /* csi be controller A */
|
||||
0x00000000000C2800ULL, /* csi be controller B */
|
||||
0x00000000000C4800ULL /* csi be controller C */
|
||||
};
|
||||
|
||||
/* PIXEL Generator, part of the Input System 2401 */
|
||||
static const hrt_address PIXELGEN_CTRL_BASE[N_PIXELGEN_ID] = {
|
||||
0x00000000000C1000ULL, /* pixel gen controller A */
|
||||
0x00000000000C3000ULL, /* pixel gen controller B */
|
||||
0x00000000000C5000ULL /* pixel gen controller C */
|
||||
};
|
||||
|
||||
/* Stream2MMIO, part of the Input System 2401 */
|
||||
static const hrt_address STREAM2MMIO_CTRL_BASE[N_STREAM2MMIO_ID] = {
|
||||
0x00000000000C0C00ULL, /* stream2mmio controller A */
|
||||
0x00000000000C2C00ULL, /* stream2mmio controller B */
|
||||
0x00000000000C4C00ULL /* stream2mmio controller C */
|
||||
};
|
||||
|
||||
#endif /* __SYSTEM_LOCAL_H_INCLUDED__ */
|
||||
|
|
|
|||
Loading…
Reference in New Issue