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clk: vt8500: fix sign of possible PLL values 

With unsigned values underflow in loops can occur resulting in
theoretically infinite loops.

The problem has been detected using proposed semantic patch
scripts/coccinelle/tests/unsigned_lesser_than_zero.cocci [1].

[1]: http://permalink.gmane.org/gmane.linux.kernel/2038576

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit is contained in:
Andrzej Hajda 2015-10-02 06:49:53 +02:00 committed by Stephen Boyd
parent 0b225e41e3
commit 090341b0a9
1 changed files with 6 additions and 3 deletions
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9
drivers/clk/clk-vt8500.c
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@ -384,7 +384,8 @@ static void vt8500_find_pll_bits(unsigned long rate, unsigned long parent_rate,
static void wm8650_find_pll_bits(unsigned long rate, unsigned long parent_rate, static void wm8650_find_pll_bits(unsigned long rate, unsigned long parent_rate,
u32 *multiplier, u32 *divisor1, u32 *divisor2) u32 *multiplier, u32 *divisor1, u32 *divisor2)
{ {
u32 mul, div1, div2; u32 mul, div1;
int div2;
u32 best_mul, best_div1, best_div2; u32 best_mul, best_div1, best_div2;
unsigned long tclk, rate_err, best_err; unsigned long tclk, rate_err, best_err;
@ -452,7 +453,8 @@ static u32 wm8750_get_filter(u32 parent_rate, u32 divisor1)
static void wm8750_find_pll_bits(unsigned long rate, unsigned long parent_rate, static void wm8750_find_pll_bits(unsigned long rate, unsigned long parent_rate,
u32 *filter, u32 *multiplier, u32 *divisor1, u32 *divisor2) u32 *filter, u32 *multiplier, u32 *divisor1, u32 *divisor2)
{ {
u32 mul, div1, div2; u32 mul;
int div1, div2;
u32 best_mul, best_div1, best_div2; u32 best_mul, best_div1, best_div2;
unsigned long tclk, rate_err, best_err; unsigned long tclk, rate_err, best_err;
@ -496,7 +498,8 @@ static void wm8750_find_pll_bits(unsigned long rate, unsigned long parent_rate,
static void wm8850_find_pll_bits(unsigned long rate, unsigned long parent_rate, static void wm8850_find_pll_bits(unsigned long rate, unsigned long parent_rate,
u32 *multiplier, u32 *divisor1, u32 *divisor2) u32 *multiplier, u32 *divisor1, u32 *divisor2)
{ {
u32 mul, div1, div2; u32 mul;
int div1, div2;
u32 best_mul, best_div1, best_div2; u32 best_mul, best_div1, best_div2;
unsigned long tclk, rate_err, best_err; unsigned long tclk, rate_err, best_err;