mirror of https://gitee.com/openkylin/linux.git
sh: oprofile: Kill off bitrotted SH7750 driver.
This kills off the old SH7750 oprofile driver, preferring perf instead. As this driver has a number of bugs that no one seems to have noticed, it's safe to kill this off now rather than providing an extended transition period. The old oprofile framework is still kept in place for now, primarily to give out-of-tree drivers a chance to transition off. But this too will be killed off in short order. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Paul Mundt
parent
1d823323f2
commit
093aed1937
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@ -7,7 +7,3 @@ DRIVER_OBJS = $(addprefix ../../../drivers/oprofile/, \
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timer_int.o )
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oprofile-y := $(DRIVER_OBJS) common.o backtrace.o
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oprofile-$(CONFIG_CPU_SUBTYPE_SH7750S) += op_model_sh7750.o
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oprofile-$(CONFIG_CPU_SUBTYPE_SH7750) += op_model_sh7750.o
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oprofile-$(CONFIG_CPU_SUBTYPE_SH7091) += op_model_sh7750.o
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@ -20,9 +20,6 @@
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#include <asm/processor.h>
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#include "op_impl.h"
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extern struct op_sh_model op_model_sh7750_ops __weak;
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extern struct op_sh_model op_model_sh4a_ops __weak;
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static struct op_sh_model *model;
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static struct op_counter_config ctr[20];
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@ -94,33 +91,14 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
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*/
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ops->backtrace = sh_backtrace;
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switch (current_cpu_data.type) {
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/* SH-4 types */
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case CPU_SH7750:
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case CPU_SH7750S:
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lmodel = &op_model_sh7750_ops;
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break;
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/* SH-4A types */
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case CPU_SH7763:
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case CPU_SH7770:
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case CPU_SH7780:
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case CPU_SH7781:
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case CPU_SH7785:
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case CPU_SH7786:
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case CPU_SH7723:
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case CPU_SH7724:
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case CPU_SHX3:
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lmodel = &op_model_sh4a_ops;
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break;
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/* SH4AL-DSP types */
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case CPU_SH7343:
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case CPU_SH7722:
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case CPU_SH7366:
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lmodel = &op_model_sh4a_ops;
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break;
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}
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/*
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* XXX
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*
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* All of the SH7750/SH-4A counters have been converted to perf,
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* this infrastructure hook is left for other users until they've
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* had a chance to convert over, at which point all of this
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* will be deleted.
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*/
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if (!lmodel)
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return -ENODEV;
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@ -1,255 +0,0 @@
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/*
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* arch/sh/oprofile/op_model_sh7750.c
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*
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* OProfile support for SH7750/SH7750S Performance Counters
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*
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* Copyright (C) 2003 - 2008 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/oprofile.h>
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#include <linux/profile.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/fs.h>
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#include "op_impl.h"
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#define PM_CR_BASE 0xff000084 /* 16-bit */
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#define PM_CTR_BASE 0xff100004 /* 32-bit */
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#define PMCR(n) (PM_CR_BASE + ((n) * 0x04))
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#define PMCTRH(n) (PM_CTR_BASE + 0x00 + ((n) * 0x08))
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#define PMCTRL(n) (PM_CTR_BASE + 0x04 + ((n) * 0x08))
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#define PMCR_PMM_MASK 0x0000003f
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#define PMCR_CLKF 0x00000100
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#define PMCR_PMCLR 0x00002000
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#define PMCR_PMST 0x00004000
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#define PMCR_PMEN 0x00008000
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struct op_sh_model op_model_sh7750_ops;
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#define NR_CNTRS 2
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static struct sh7750_ppc_register_config {
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unsigned int ctrl;
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unsigned long cnt_hi;
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unsigned long cnt_lo;
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} regcache[NR_CNTRS];
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/*
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* There are a number of events supported by each counter (33 in total).
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* Since we have 2 counters, each counter will take the event code as it
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* corresponds to the PMCR PMM setting. Each counter can be configured
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* independently.
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*
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* Event Code Description
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* ---------- -----------
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*
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* 0x01 Operand read access
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* 0x02 Operand write access
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* 0x03 UTLB miss
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* 0x04 Operand cache read miss
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* 0x05 Operand cache write miss
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* 0x06 Instruction fetch (w/ cache)
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* 0x07 Instruction TLB miss
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* 0x08 Instruction cache miss
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* 0x09 All operand accesses
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* 0x0a All instruction accesses
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* 0x0b OC RAM operand access
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* 0x0d On-chip I/O space access
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* 0x0e Operand access (r/w)
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* 0x0f Operand cache miss (r/w)
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* 0x10 Branch instruction
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* 0x11 Branch taken
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* 0x12 BSR/BSRF/JSR
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* 0x13 Instruction execution
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* 0x14 Instruction execution in parallel
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* 0x15 FPU Instruction execution
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* 0x16 Interrupt
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* 0x17 NMI
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* 0x18 trapa instruction execution
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* 0x19 UBCA match
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* 0x1a UBCB match
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* 0x21 Instruction cache fill
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* 0x22 Operand cache fill
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* 0x23 Elapsed time
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* 0x24 Pipeline freeze by I-cache miss
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* 0x25 Pipeline freeze by D-cache miss
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* 0x27 Pipeline freeze by branch instruction
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* 0x28 Pipeline freeze by CPU register
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* 0x29 Pipeline freeze by FPU
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*
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* Unfortunately we don't have a native exception or interrupt for counter
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* overflow (although since these counters can run for 16.3 days without
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* overflowing, it's not really necessary).
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*
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* OProfile on the other hand likes to have samples taken periodically, so
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* for now we just piggyback the timer interrupt to get the expected
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* behavior.
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*/
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static int sh7750_timer_notify(struct pt_regs *regs)
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{
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oprofile_add_sample(regs, 0);
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return 0;
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}
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static u64 sh7750_read_counter(int counter)
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{
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return (u64)((u64)(__raw_readl(PMCTRH(counter)) & 0xffff) << 32) |
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__raw_readl(PMCTRL(counter));
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}
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/*
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* Files will be in a path like:
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*
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* /<oprofilefs mount point>/<counter number>/<file>
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*
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* So when dealing with <file>, we look to the parent dentry for the counter
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* number.
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*/
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static inline int to_counter(struct file *file)
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{
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const unsigned char *name = file->f_path.dentry->d_parent->d_name.name;
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return (int)simple_strtol(name, NULL, 10);
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}
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/*
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* XXX: We have 48-bit counters, so we're probably going to want something
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* more along the lines of oprofilefs_ullong_to_user().. Truncating to
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* unsigned long works fine for now though, as long as we don't attempt to
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* profile for too horribly long.
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*/
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static ssize_t sh7750_read_count(struct file *file, char __user *buf,
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size_t count, loff_t *ppos)
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{
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int counter = to_counter(file);
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u64 val = sh7750_read_counter(counter);
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return oprofilefs_ulong_to_user((unsigned long)val, buf, count, ppos);
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}
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static ssize_t sh7750_write_count(struct file *file, const char __user *buf,
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size_t count, loff_t *ppos)
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{
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int counter = to_counter(file);
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unsigned long val;
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if (oprofilefs_ulong_from_user(&val, buf, count))
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return -EFAULT;
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/*
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* Any write will clear the counter, although only 0 should be
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* written for this purpose, as we do not support setting the
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* counter to an arbitrary value.
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*/
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WARN_ON(val != 0);
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__raw_writew(__raw_readw(PMCR(counter)) | PMCR_PMCLR, PMCR(counter));
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return count;
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}
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static const struct file_operations count_fops = {
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.read = sh7750_read_count,
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.write = sh7750_write_count,
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};
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static int sh7750_ppc_create_files(struct super_block *sb, struct dentry *dir)
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{
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return oprofilefs_create_file(sb, dir, "count", &count_fops);
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}
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static void sh7750_ppc_reg_setup(struct op_counter_config *ctr)
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{
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unsigned int counters = op_model_sh7750_ops.num_counters;
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int i;
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for (i = 0; i < counters; i++) {
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regcache[i].ctrl = 0;
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regcache[i].cnt_hi = 0;
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regcache[i].cnt_lo = 0;
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if (!ctr[i].enabled)
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continue;
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regcache[i].ctrl |= ctr[i].event | PMCR_PMEN | PMCR_PMST;
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regcache[i].cnt_hi = (unsigned long)((ctr->count >> 32) & 0xffff);
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regcache[i].cnt_lo = (unsigned long)(ctr->count & 0xffffffff);
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}
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}
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static void sh7750_ppc_cpu_setup(void *args)
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{
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unsigned int counters = op_model_sh7750_ops.num_counters;
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int i;
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for (i = 0; i < counters; i++) {
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__raw_writew(0, PMCR(i));
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__raw_writel(regcache[i].cnt_hi, PMCTRH(i));
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__raw_writel(regcache[i].cnt_lo, PMCTRL(i));
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}
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}
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static void sh7750_ppc_cpu_start(void *args)
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{
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unsigned int counters = op_model_sh7750_ops.num_counters;
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int i;
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for (i = 0; i < counters; i++)
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__raw_writew(regcache[i].ctrl, PMCR(i));
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}
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static void sh7750_ppc_cpu_stop(void *args)
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{
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unsigned int counters = op_model_sh7750_ops.num_counters;
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int i;
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/* Disable the counters */
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for (i = 0; i < counters; i++)
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__raw_writew(__raw_readw(PMCR(i)) & ~PMCR_PMEN, PMCR(i));
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}
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static inline void sh7750_ppc_reset(void)
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{
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unsigned int counters = op_model_sh7750_ops.num_counters;
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int i;
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/* Clear the counters */
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for (i = 0; i < counters; i++)
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__raw_writew(__raw_readw(PMCR(i)) | PMCR_PMCLR, PMCR(i));
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}
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static int sh7750_ppc_init(void)
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{
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sh7750_ppc_reset();
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return register_timer_hook(sh7750_timer_notify);
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}
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static void sh7750_ppc_exit(void)
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{
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unregister_timer_hook(sh7750_timer_notify);
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sh7750_ppc_reset();
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}
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struct op_sh_model op_model_sh7750_ops = {
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.cpu_type = "sh/sh7750",
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.num_counters = NR_CNTRS,
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.reg_setup = sh7750_ppc_reg_setup,
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.cpu_setup = sh7750_ppc_cpu_setup,
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.cpu_start = sh7750_ppc_cpu_start,
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.cpu_stop = sh7750_ppc_cpu_stop,
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.init = sh7750_ppc_init,
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.exit = sh7750_ppc_exit,
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.create_files = sh7750_ppc_create_files,
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};
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