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drm/i915: vlv: fix RPS interrupt mask setting 

This typo may lead to missed RPS interrupts and as a result a too
low or too high frequency for the current workload. The interrupt mask
will be set properly at a subsequent GPU idle event, but can get
corrupted again at the next RPS up/down event.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Imre Deak 2014-04-03 20:02:42 +03:00 committed by Daniel Vetter
parent f6d519481b
commit 09c87db8b4
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/i915/intel_pm.c
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@ -3159,7 +3159,7 @@ void valleyview_set_rps(struct drm_device *dev, u8 val)
if (val != dev_priv->rps.cur_freq) if (val != dev_priv->rps.cur_freq)
vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val); vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
I915_WRITE(GEN6_PMINTRMSK, val); I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
dev_priv->rps.cur_freq = val; dev_priv->rps.cur_freq = val;
trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val)); trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));