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arm64: dts: rockchip: fix rk3328 sdmmc0 write errors 

Various rk3328 based boards experience occasional sdmmc0 write errors.
This is due to the rk3328.dtsi tx drive levels being set to 4ma, vs
8ma per the rk3328 datasheet default settings.

Fix this by setting the tx signal pins to 8ma.
Inspiration from tonymac32's patch,
dc1212b347

Fixes issues on the rk3328-roc-cc and the rk3328-rock64 (as per the
above commit message).

Tested on the rk3328-roc-cc board.

Fixes: 52e02d377a ("arm64: dts: rockchip: add core dtsi file for RK3328 SoCs")
Cc: stable@vger.kernel.org
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
Peter Geis 2019-03-13 19:02:30 +00:00 committed by Heiko Stuebner
parent 6fd8b9780e
commit 09f91381fa
1 changed files with 7 additions and 7 deletions
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14
arch/arm64/boot/dts/rockchip/rk3328.dtsi
View File

@ -1445,11 +1445,11 @@ sdmmc0m1_gpio: sdmmc0m1-gpio {
sdmmc0 {
sdmmc0_clk: sdmmc0-clk {
rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_4ma>;
rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_8ma>;
};
sdmmc0_cmd: sdmmc0-cmd {
rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_4ma>;
rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_8ma>;
};
sdmmc0_dectn: sdmmc0-dectn {
@ -1461,14 +1461,14 @@ sdmmc0_wrprt: sdmmc0-wrprt {
};
sdmmc0_bus1: sdmmc0-bus1 {
rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_4ma>;
rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>;
};
sdmmc0_bus4: sdmmc0-bus4 {
rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_4ma>,
<1 RK_PA1 1 &pcfg_pull_up_4ma>,
<1 RK_PA2 1 &pcfg_pull_up_4ma>,
<1 RK_PA3 1 &pcfg_pull_up_4ma>;
rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>,
<1 RK_PA1 1 &pcfg_pull_up_8ma>,
<1 RK_PA2 1 &pcfg_pull_up_8ma>,
<1 RK_PA3 1 &pcfg_pull_up_8ma>;
};
sdmmc0_gpio: sdmmc0-gpio {