mirror of https://gitee.com/openkylin/linux.git
This pull request contains Broadcom ARM64-based SoC Device Tree changes:
- Anup enables a bunch of standard peripherals in the Northstar 2 DTS: PL330 DMA, GIC maintenance interrupt, PL022 SPI controller - Anup also re-orgnanizes the clock Device Tree fragments into a separate file for consistency with how other Broadcom SoCs are doing this - Luke switches the SMP enable-method and reboot from a spin-table + syscon to the standard PSCI 1.0 firmware interface -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJXG8r9AAoJEIfQlpxEBwcEVIYP/0Q5uRJ7zysbVOBo0dm4CPwK 2dxmt1ANc6fB/LSuedIzCkAOXPBX1x4goF59pb5UHBBpV2/Y79HT6BMG2SVvjtNh 4FF3mqVLZ5B6KlJDkZb6JN29SG82OjGZrZLpSC8/89TXMadTLdbSq41hVjJ9sY9l 9feg1qmhO1pKfZIRWPxJnNzCyiJOtKBZSSZaUyejolZBMIIdf8uPUtiRqu/sNWvd mz37YDdXFJomaoBdgUSKlwvChs+6LkzczSLRlcTHa9Wr7luXwftU1uXRHbzHDMHS BUxvIbJe8ivwDjYdCB6l0PxIiigYm2mVIZt06BVYLbQMih5zmlOdrSW6c3e/CrIe i9IBRHwR+l7uqs/u2b6dX7/wziH9jtZ2Hv0dK7+k/A8nktw4wWr5VZsYiMWZ/j0Q ikfSRz26+p0LJ05PNTtmqSFhZ5sAcUQ599+guyNDl+8EbpVKHvTlHtmWxktO/w0v 3K0QwaIvxac0xR90XVBvhmY6b+/8uJoKqp6jqTymEZGOqinOvA9kcnNW6PDZHyxh 6LdEGg1APNou0/t1Uq7khlOfkRhhifUAV8dJVFqFsc/ZFOB1zZiLIiEmV5ckdZlR iUFKArRzki4G6CG1JQ2bGIjun+JGVPCuQsdlVERJdeBC4WJn4JtT/SGlc0DlowK2 r/4BBv44ZLmRcLcm10+L =6mn8 -----END PGP SIGNATURE----- Merge tag 'arm-soc/for-4.7/devicetree-arm64' of http://github.com/Broadcom/stblinux into next/dt64 Pull "Broadcom ARM64-based SoC Device Tree changes" from Florian Fainelli: - Anup enables a bunch of standard peripherals in the Northstar 2 DTS: PL330 DMA, GIC maintenance interrupt, PL022 SPI controller - Anup also re-orgnanizes the clock Device Tree fragments into a separate file for consistency with how other Broadcom SoCs are doing this - Luke switches the SMP enable-method and reboot from a spin-table + syscon to the standard PSCI 1.0 firmware interface * tag 'arm-soc/for-4.7/devicetree-arm64' of http://github.com/Broadcom/stblinux: arm64: dts: NS2 secondary core enablement via PSCI arm64: dts: Add ARM PL022 SPI DT nodes for NS2 arm64: dts: Move NS2 clock DT nodes to separate DT file arm64: dts: Add maintenance interrupt for GIC in NS2 DT arm64: dts: Add ARM PL330 DMA DT node for NS2
This commit is contained in:
Arnd Bergmann
commit
0a45e16a54
|
|
@ -0,0 +1,105 @@
|
|||
/*
|
||||
* BSD LICENSE
|
||||
*
|
||||
* Copyright (c) 2016 Broadcom. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* * Neither the name of Broadcom Corporation nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/bcm-ns2.h>
|
||||
|
||||
osc: oscillator {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
lcpll_ddr: lcpll_ddr@6501d058 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "brcm,ns2-lcpll-ddr";
|
||||
reg = <0x6501d058 0x20>,
|
||||
<0x6501c020 0x4>,
|
||||
<0x6501d04c 0x4>;
|
||||
clocks = <&osc>;
|
||||
clock-output-names = "lcpll_ddr", "pcie_sata_usb",
|
||||
"ddr", "ddr_ch2_unused",
|
||||
"ddr_ch3_unused", "ddr_ch4_unused",
|
||||
"ddr_ch5_unused";
|
||||
};
|
||||
|
||||
lcpll_ports: lcpll_ports@6501d078 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "brcm,ns2-lcpll-ports";
|
||||
reg = <0x6501d078 0x20>,
|
||||
<0x6501c020 0x4>,
|
||||
<0x6501d054 0x4>;
|
||||
clocks = <&osc>;
|
||||
clock-output-names = "lcpll_ports", "wan", "rgmii",
|
||||
"ports_ch2_unused",
|
||||
"ports_ch3_unused",
|
||||
"ports_ch4_unused",
|
||||
"ports_ch5_unused";
|
||||
};
|
||||
|
||||
genpll_scr: genpll_scr@6501d098 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "brcm,ns2-genpll-scr";
|
||||
reg = <0x6501d098 0x32>,
|
||||
<0x6501c020 0x4>,
|
||||
<0x6501d044 0x4>;
|
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clocks = <&osc>;
|
||||
clock-output-names = "genpll_scr", "scr", "fs",
|
||||
"audio_ref", "scr_ch3_unused",
|
||||
"scr_ch4_unused", "scr_ch5_unused";
|
||||
};
|
||||
|
||||
iprocmed: iprocmed {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>;
|
||||
clock-div = <2>;
|
||||
clock-mult = <1>;
|
||||
};
|
||||
|
||||
iprocslow: iprocslow {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>;
|
||||
clock-div = <4>;
|
||||
clock-mult = <1>;
|
||||
};
|
||||
|
||||
genpll_sw: genpll_sw@6501d0c4 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "brcm,ns2-genpll-sw";
|
||||
reg = <0x6501d0c4 0x32>,
|
||||
<0x6501c020 0x4>,
|
||||
<0x6501d044 0x4>;
|
||||
clocks = <&osc>;
|
||||
clock-output-names = "genpll_sw", "rpe", "250", "nic",
|
||||
"chimp", "port", "sdio";
|
||||
};
|
||||
|
|
@ -72,6 +72,51 @@ &uart3 {
|
|||
status = "ok";
|
||||
};
|
||||
|
||||
&ssp0 {
|
||||
status = "ok";
|
||||
|
||||
slic@0 {
|
||||
compatible = "silabs,si3226x";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <5000000>;
|
||||
spi-cpha = <1>;
|
||||
spi-cpol = <1>;
|
||||
pl022,hierarchy = <0>;
|
||||
pl022,interface = <0>;
|
||||
pl022,slave-tx-disable = <0>;
|
||||
pl022,com-mode = <0>;
|
||||
pl022,rx-level-trig = <1>;
|
||||
pl022,tx-level-trig = <1>;
|
||||
pl022,ctrl-len = <11>;
|
||||
pl022,wait-state = <0>;
|
||||
pl022,duplex = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&ssp1 {
|
||||
status = "ok";
|
||||
|
||||
at25@0 {
|
||||
compatible = "atmel,at25";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <5000000>;
|
||||
at25,byte-len = <0x8000>;
|
||||
at25,addr-mode = <2>;
|
||||
at25,page-size = <64>;
|
||||
spi-cpha = <1>;
|
||||
spi-cpol = <1>;
|
||||
pl022,hierarchy = <0>;
|
||||
pl022,interface = <0>;
|
||||
pl022,slave-tx-disable = <0>;
|
||||
pl022,com-mode = <0>;
|
||||
pl022,rx-level-trig = <1>;
|
||||
pl022,tx-level-trig = <1>;
|
||||
pl022,ctrl-len = <11>;
|
||||
pl022,wait-state = <0>;
|
||||
pl022,duplex = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&sdio0 {
|
||||
status = "ok";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* BSD LICENSE
|
||||
*
|
||||
* Copyright(c) 2015 Broadcom Corporation. All rights reserved.
|
||||
* Copyright (c) 2015 Broadcom. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
|
|
@ -33,8 +33,6 @@
|
|||
#include <dt-bindings/interrupt-controller/arm-gic.h>
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||||
#include <dt-bindings/clock/bcm-ns2.h>
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||||
|
||||
/memreserve/ 0x84b00000 0x00000008;
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||||
|
||||
/ {
|
||||
compatible = "brcm,ns2";
|
||||
interrupt-parent = <&gic>;
|
||||
|
|
@ -49,8 +47,7 @@ A57_0: cpu@0 {
|
|||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57", "arm,armv8";
|
||||
reg = <0 0>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x84b00000>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&CLUSTER0_L2>;
|
||||
};
|
||||
|
||||
|
|
@ -58,8 +55,7 @@ A57_1: cpu@1 {
|
|||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57", "arm,armv8";
|
||||
reg = <0 1>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x84b00000>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&CLUSTER0_L2>;
|
||||
};
|
||||
|
||||
|
|
@ -67,8 +63,7 @@ A57_2: cpu@2 {
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|||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57", "arm,armv8";
|
||||
reg = <0 2>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x84b00000>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&CLUSTER0_L2>;
|
||||
};
|
||||
|
||||
|
|
@ -76,8 +71,7 @@ A57_3: cpu@3 {
|
|||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0 3>;
|
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enable-method = "spin-table";
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cpu-release-addr = <0 0x84b00000>;
|
||||
enable-method = "psci";
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next-level-cache = <&CLUSTER0_L2>;
|
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};
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|
|
@ -86,6 +80,11 @@ CLUSTER0_L2: l2-cache@000 {
|
|||
};
|
||||
};
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||||
|
||||
psci {
|
||||
compatible = "arm,psci-1.0";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) |
|
||||
|
|
@ -110,33 +109,6 @@ pmu {
|
|||
<&A57_3>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
osc: oscillator {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
iprocmed: iprocmed {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>;
|
||||
clock-div = <2>;
|
||||
clock-mult = <1>;
|
||||
};
|
||||
|
||||
iprocslow: iprocslow {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>;
|
||||
clock-div = <4>;
|
||||
clock-mult = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie0: pcie@20020000 {
|
||||
compatible = "brcm,iproc-pcie";
|
||||
reg = <0 0x20020000 0 0x1000>;
|
||||
|
|
@ -217,6 +189,27 @@ soc: soc {
|
|||
#size-cells = <1>;
|
||||
ranges = <0 0 0 0xffffffff>;
|
||||
|
||||
#include "ns2-clock.dtsi"
|
||||
|
||||
dma0: dma@61360000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x61360000 0x1000>;
|
||||
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
#dma-requests = <32>;
|
||||
clocks = <&iprocslow>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
smmu: mmu@64000000 {
|
||||
compatible = "arm,mmu-500";
|
||||
reg = <0x64000000 0x40000>;
|
||||
|
|
@ -258,68 +251,6 @@ smmu: mmu@64000000 {
|
|||
mmu-masters;
|
||||
};
|
||||
|
||||
lcpll_ddr: lcpll_ddr@6501d058 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "brcm,ns2-lcpll-ddr";
|
||||
reg = <0x6501d058 0x20>,
|
||||
<0x6501c020 0x4>,
|
||||
<0x6501d04c 0x4>;
|
||||
clocks = <&osc>;
|
||||
clock-output-names = "lcpll_ddr", "pcie_sata_usb",
|
||||
"ddr", "ddr_ch2_unused",
|
||||
"ddr_ch3_unused", "ddr_ch4_unused",
|
||||
"ddr_ch5_unused";
|
||||
};
|
||||
|
||||
lcpll_ports: lcpll_ports@6501d078 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "brcm,ns2-lcpll-ports";
|
||||
reg = <0x6501d078 0x20>,
|
||||
<0x6501c020 0x4>,
|
||||
<0x6501d054 0x4>;
|
||||
clocks = <&osc>;
|
||||
clock-output-names = "lcpll_ports", "wan", "rgmii",
|
||||
"ports_ch2_unused",
|
||||
"ports_ch3_unused",
|
||||
"ports_ch4_unused",
|
||||
"ports_ch5_unused";
|
||||
};
|
||||
|
||||
genpll_scr: genpll_scr@6501d098 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "brcm,ns2-genpll-scr";
|
||||
reg = <0x6501d098 0x32>,
|
||||
<0x6501c020 0x4>,
|
||||
<0x6501d044 0x4>;
|
||||
clocks = <&osc>;
|
||||
clock-output-names = "genpll_scr", "scr", "fs",
|
||||
"audio_ref", "scr_ch3_unused",
|
||||
"scr_ch4_unused", "scr_ch5_unused";
|
||||
};
|
||||
|
||||
genpll_sw: genpll_sw@6501d0c4 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "brcm,ns2-genpll-sw";
|
||||
reg = <0x6501d0c4 0x32>,
|
||||
<0x6501c020 0x4>,
|
||||
<0x6501d044 0x4>;
|
||||
clocks = <&osc>;
|
||||
clock-output-names = "genpll_sw", "rpe", "250", "nic",
|
||||
"chimp", "port", "sdio";
|
||||
};
|
||||
|
||||
crmu: crmu@65024000 {
|
||||
compatible = "syscon";
|
||||
reg = <0x65024000 0x100>;
|
||||
};
|
||||
|
||||
reboot@65024000 {
|
||||
compatible ="syscon-reboot";
|
||||
regmap = <&crmu>;
|
||||
offset = <0x90>;
|
||||
mask = <0xfffffffd>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@65210000 {
|
||||
compatible = "arm,gic-400";
|
||||
#interrupt-cells = <3>;
|
||||
|
|
@ -328,6 +259,8 @@ gic: interrupt-controller@65210000 {
|
|||
<0x65220000 0x1000>,
|
||||
<0x65240000 0x2000>,
|
||||
<0x65260000 0x1000>;
|
||||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
|
||||
IRQ_TYPE_LEVEL_HIGH)>;
|
||||
};
|
||||
|
||||
timer0: timer@66030000 {
|
||||
|
|
@ -408,6 +341,28 @@ uart3: serial@66130000 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
ssp0: ssp@66180000 {
|
||||
compatible = "arm,pl022", "arm,primecell";
|
||||
reg = <0x66180000 0x1000>;
|
||||
interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&iprocslow>, <&iprocslow>;
|
||||
clock-names = "spiclk", "apb_pclk";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ssp1: ssp@66190000 {
|
||||
compatible = "arm,pl022", "arm,primecell";
|
||||
reg = <0x66190000 0x1000>;
|
||||
interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&iprocslow>, <&iprocslow>;
|
||||
clock-names = "spiclk", "apb_pclk";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hwrng: hwrng@66220000 {
|
||||
compatible = "brcm,iproc-rng200";
|
||||
reg = <0x66220000 0x28>;
|
||||
|
|
|
|||
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Reference in New Issue