mirror of https://gitee.com/openkylin/linux.git
ath9k_hw: Tx IQ cal changes for AR9003
Add multiple Tx IQ cal support to improve EVM accross different power levels. Signed-off-by: Vasanthakumar Thiagarajan <vasanth@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Vasanthakumar Thiagarajan
John W. Linville
parent
895ad7eb21
commit
0b2084bc57
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@ -608,107 +608,6 @@ static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah,
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return true;
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}
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static void ar9003_hw_tx_iq_cal(struct ath_hw *ah)
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{
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struct ath_common *common = ath9k_hw_common(ah);
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static const u32 txiqcal_status[AR9300_MAX_CHAINS] = {
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AR_PHY_TX_IQCAL_STATUS_B0,
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AR_PHY_TX_IQCAL_STATUS_B1,
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AR_PHY_TX_IQCAL_STATUS_B2,
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};
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static const u_int32_t chan_info_tab[] = {
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AR_PHY_CHAN_INFO_TAB_0,
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AR_PHY_CHAN_INFO_TAB_1,
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AR_PHY_CHAN_INFO_TAB_2,
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};
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u32 tx_corr_coeff[AR9300_MAX_CHAINS];
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s32 iq_res[6];
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s32 iqc_coeff[2];
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s32 i, j;
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u32 num_chains = 0;
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tx_corr_coeff[0] = AR_PHY_TX_IQCAL_CORR_COEFF_B0(0);
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tx_corr_coeff[1] = AR_PHY_TX_IQCAL_CORR_COEFF_B1(0);
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tx_corr_coeff[2] = AR_PHY_TX_IQCAL_CORR_COEFF_B2(0);
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for (i = 0; i < AR9300_MAX_CHAINS; i++) {
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if (ah->txchainmask & (1 << i))
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num_chains++;
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}
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REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_1,
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AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT,
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DELPT);
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REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_START,
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AR_PHY_TX_IQCAL_START_DO_CAL,
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AR_PHY_TX_IQCAL_START_DO_CAL);
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if (!ath9k_hw_wait(ah, AR_PHY_TX_IQCAL_START,
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AR_PHY_TX_IQCAL_START_DO_CAL,
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0, AH_WAIT_TIMEOUT)) {
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ath_dbg(common, ATH_DBG_CALIBRATE,
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"Tx IQ Cal not complete.\n");
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goto TX_IQ_CAL_FAILED;
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}
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for (i = 0; i < num_chains; i++) {
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ath_dbg(common, ATH_DBG_CALIBRATE,
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"Doing Tx IQ Cal for chain %d.\n", i);
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if (REG_READ(ah, txiqcal_status[i]) &
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AR_PHY_TX_IQCAL_STATUS_FAILED) {
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ath_dbg(common, ATH_DBG_CALIBRATE,
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"Tx IQ Cal failed for chain %d.\n", i);
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goto TX_IQ_CAL_FAILED;
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}
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for (j = 0; j < 3; j++) {
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u_int8_t idx = 2 * j,
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offset = 4 * j;
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REG_RMW_FIELD(ah, AR_PHY_CHAN_INFO_MEMORY,
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AR_PHY_CHAN_INFO_TAB_S2_READ, 0);
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/* 32 bits */
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iq_res[idx] = REG_READ(ah, chan_info_tab[i] + offset);
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REG_RMW_FIELD(ah, AR_PHY_CHAN_INFO_MEMORY,
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AR_PHY_CHAN_INFO_TAB_S2_READ, 1);
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/* 16 bits */
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iq_res[idx+1] = 0xffff & REG_READ(ah,
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chan_info_tab[i] +
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offset);
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ath_dbg(common, ATH_DBG_CALIBRATE,
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"IQ RES[%d]=0x%x IQ_RES[%d]=0x%x\n",
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idx, iq_res[idx], idx+1, iq_res[idx+1]);
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}
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if (!ar9003_hw_calc_iq_corr(ah, i, iq_res, iqc_coeff)) {
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ath_dbg(common, ATH_DBG_CALIBRATE,
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"Failed in calculation of IQ correction.\n");
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goto TX_IQ_CAL_FAILED;
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}
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ath_dbg(common, ATH_DBG_CALIBRATE,
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"IQ_COEFF[0] = 0x%x IQ_COEFF[1] = 0x%x\n",
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iqc_coeff[0], iqc_coeff[1]);
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REG_RMW_FIELD(ah, tx_corr_coeff[i],
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AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE,
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iqc_coeff[0]);
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}
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REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_3,
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AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN, 0x1);
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return;
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TX_IQ_CAL_FAILED:
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ath_dbg(common, ATH_DBG_CALIBRATE, "Tx IQ Cal failed\n");
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}
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static bool ar9003_hw_compute_closest_pass_and_avg(int *mp_coeff, int *mp_avg)
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{
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int diff[MPASS];
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@ -717,9 +616,9 @@ static bool ar9003_hw_compute_closest_pass_and_avg(int *mp_coeff, int *mp_avg)
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diff[1] = abs(mp_coeff[1] - mp_coeff[2]);
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diff[2] = abs(mp_coeff[2] - mp_coeff[0]);
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if (diff[0] > MAX_MEASUREMENT &&
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diff[1] > MAX_MEASUREMENT &&
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diff[2] > MAX_MEASUREMENT)
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if (diff[0] > MAX_DIFFERENCE &&
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diff[1] > MAX_DIFFERENCE &&
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diff[2] > MAX_DIFFERENCE)
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return false;
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if (diff[0] <= diff[1] && diff[0] <= diff[2])
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@ -817,6 +716,111 @@ static void ar9003_hw_tx_iqcal_load_avg_2_passes(struct ath_hw *ah,
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ath_dbg(common, ATH_DBG_CALIBRATE, "TX IQ Cal disabled\n");
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}
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static void ar9003_hw_tx_iq_cal(struct ath_hw *ah)
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{
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struct ath_common *common = ath9k_hw_common(ah);
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static const u32 txiqcal_status[AR9300_MAX_CHAINS] = {
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AR_PHY_TX_IQCAL_STATUS_B0,
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AR_PHY_TX_IQCAL_STATUS_B1,
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AR_PHY_TX_IQCAL_STATUS_B2,
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};
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static const u32 chan_info_tab[] = {
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AR_PHY_CHAN_INFO_TAB_0,
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AR_PHY_CHAN_INFO_TAB_1,
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AR_PHY_CHAN_INFO_TAB_2,
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};
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struct coeff coeff;
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s32 iq_res[6];
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s32 i, j, ip, im, nmeasurement;
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u8 nchains = get_streams(common->tx_chainmask);
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for (ip = 0; ip < MPASS; ip++) {
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REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_1,
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AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT,
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DELPT);
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REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_START,
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AR_PHY_TX_IQCAL_START_DO_CAL,
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AR_PHY_TX_IQCAL_START_DO_CAL);
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if (!ath9k_hw_wait(ah, AR_PHY_TX_IQCAL_START,
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AR_PHY_TX_IQCAL_START_DO_CAL,
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0, AH_WAIT_TIMEOUT)) {
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ath_dbg(common, ATH_DBG_CALIBRATE,
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"Tx IQ Cal not complete.\n");
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goto TX_IQ_CAL_FAILED;
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}
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nmeasurement = REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_STATUS_B0,
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AR_PHY_CALIBRATED_GAINS_0);
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if (nmeasurement > MAX_MEASUREMENT)
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nmeasurement = MAX_MEASUREMENT;
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for (i = 0; i < nchains; i++) {
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ath_dbg(common, ATH_DBG_CALIBRATE,
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"Doing Tx IQ Cal for chain %d.\n", i);
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for (im = 0; im < nmeasurement; im++) {
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if (REG_READ(ah, txiqcal_status[i]) &
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AR_PHY_TX_IQCAL_STATUS_FAILED) {
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ath_dbg(common, ATH_DBG_CALIBRATE,
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"Tx IQ Cal failed for chain %d.\n", i);
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goto TX_IQ_CAL_FAILED;
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}
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for (j = 0; j < 3; j++) {
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u8 idx = 2 * j,
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offset = 4 * (3 * im + j);
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REG_RMW_FIELD(ah, AR_PHY_CHAN_INFO_MEMORY,
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AR_PHY_CHAN_INFO_TAB_S2_READ,
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0);
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/* 32 bits */
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iq_res[idx] = REG_READ(ah,
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chan_info_tab[i] +
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offset);
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REG_RMW_FIELD(ah, AR_PHY_CHAN_INFO_MEMORY,
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AR_PHY_CHAN_INFO_TAB_S2_READ,
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1);
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/* 16 bits */
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iq_res[idx+1] = 0xffff & REG_READ(ah,
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chan_info_tab[i] +
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offset);
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ath_dbg(common, ATH_DBG_CALIBRATE,
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"IQ RES[%d]=0x%x IQ_RES[%d]=0x%x\n",
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idx, iq_res[idx], idx+1, iq_res[idx+1]);
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}
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if (!ar9003_hw_calc_iq_corr(ah, i, iq_res,
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coeff.iqc_coeff)) {
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ath_dbg(common, ATH_DBG_CALIBRATE,
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"Failed in calculation of IQ correction.\n");
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goto TX_IQ_CAL_FAILED;
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}
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coeff.mag_coeff[i][im][ip] =
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coeff.iqc_coeff[0] & 0x7f;
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coeff.phs_coeff[i][im][ip] =
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(coeff.iqc_coeff[0] >> 7) & 0x7f;
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if (coeff.mag_coeff[i][im][ip] > 63)
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coeff.mag_coeff[i][im][ip] -= 128;
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if (coeff.phs_coeff[i][im][ip] > 63)
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coeff.phs_coeff[i][im][ip] -= 128;
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}
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}
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}
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ar9003_hw_tx_iqcal_load_avg_2_passes(ah, nchains, &coeff);
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return;
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TX_IQ_CAL_FAILED:
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ath_dbg(common, ATH_DBG_CALIBRATE, "Tx IQ Cal failed\n");
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}
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static void ar9003_hw_tx_iq_cal_run(struct ath_hw *ah)
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{
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u8 tx_gain_forced;
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