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drm/amdkfd: Fix sparse errors 

Signed-off-by: Oded Gabbay <oded.gabbay@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Oded Gabbay 2015-01-22 13:42:28 +02:00
parent 7113cd6529
commit 0b3674ae1c
3 changed files with 27 additions and 37 deletions
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16
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
View File

@ -141,8 +141,6 @@ static int kfd_ioctl_get_version(struct file *filep, struct kfd_process *p,
static int set_queue_properties_from_user(struct queue_properties *q_properties, static int set_queue_properties_from_user(struct queue_properties *q_properties,
struct kfd_ioctl_create_queue_args *args) struct kfd_ioctl_create_queue_args *args)
{ {
void *tmp;
if (args->queue_percentage > KFD_MAX_QUEUE_PERCENTAGE) { if (args->queue_percentage > KFD_MAX_QUEUE_PERCENTAGE) {
pr_err("kfd: queue percentage must be between 0 to KFD_MAX_QUEUE_PERCENTAGE\n"); pr_err("kfd: queue percentage must be between 0 to KFD_MAX_QUEUE_PERCENTAGE\n");
return -EINVAL; return -EINVAL;
@ -180,16 +178,18 @@ static int set_queue_properties_from_user(struct queue_properties *q_properties,
return -EFAULT; return -EFAULT;
} }
tmp = (void *)(uintptr_t)args->eop_buffer_address; if (args->eop_buffer_address &&
if (tmp != NULL && !access_ok(VERIFY_WRITE,
!access_ok(VERIFY_WRITE, tmp, sizeof(uint32_t))) { (const void __user *) args->eop_buffer_address,
sizeof(uint32_t))) {
pr_debug("kfd: can't access eop buffer"); pr_debug("kfd: can't access eop buffer");
return -EFAULT; return -EFAULT;
} }
tmp = (void *)(uintptr_t)args->ctx_save_restore_address; if (args->ctx_save_restore_address &&
if (tmp != NULL && !access_ok(VERIFY_WRITE,
!access_ok(VERIFY_WRITE, tmp, sizeof(uint32_t))) { (const void __user *) args->ctx_save_restore_address,
sizeof(uint32_t))) {
pr_debug("kfd: can't access ctx save restore buffer"); pr_debug("kfd: can't access ctx save restore buffer");
return -EFAULT; return -EFAULT;
} }

28
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
View File

@ -62,12 +62,6 @@ enum KFD_MQD_TYPE get_mqd_type_from_queue_type(enum kfd_queue_type type)
return KFD_MQD_TYPE_CP; return KFD_MQD_TYPE_CP;
} }
inline unsigned int get_pipes_num(struct device_queue_manager *dqm)
{
BUG_ON(!dqm || !dqm->dev);
return dqm->dev->shared_resources.compute_pipe_count;
}
static inline unsigned int get_first_pipe(struct device_queue_manager *dqm) static inline unsigned int get_first_pipe(struct device_queue_manager *dqm)
{ {
BUG_ON(!dqm); BUG_ON(!dqm);
@ -79,25 +73,6 @@ static inline unsigned int get_pipes_num_cpsch(void)
return PIPE_PER_ME_CP_SCHEDULING; return PIPE_PER_ME_CP_SCHEDULING;
} }
inline unsigned int
get_sh_mem_bases_nybble_64(struct kfd_process_device *pdd)
{
uint32_t nybble;
nybble = (pdd->lds_base >> 60) & 0x0E;
return nybble;
}
inline unsigned int get_sh_mem_bases_32(struct kfd_process_device *pdd)
{
unsigned int shared_base;
shared_base = (pdd->lds_base >> 16) & 0xFF;
return shared_base;
}
void program_sh_mem_settings(struct device_queue_manager *dqm, void program_sh_mem_settings(struct device_queue_manager *dqm,
struct qcm_process_device *qpd) struct qcm_process_device *qpd)
{ {
@ -336,7 +311,8 @@ static int update_queue(struct device_queue_manager *dqm, struct queue *q)
BUG_ON(!dqm || !q || !q->mqd); BUG_ON(!dqm || !q || !q->mqd);
mutex_lock(&dqm->lock); mutex_lock(&dqm->lock);
mqd = dqm->ops.get_mqd_manager(dqm, q->properties.type); mqd = dqm->ops.get_mqd_manager(dqm,
get_mqd_type_from_queue_type(q->properties.type));
if (mqd == NULL) { if (mqd == NULL) {
mutex_unlock(&dqm->lock); mutex_unlock(&dqm->lock);
return -ENOMEM; return -ENOMEM;

20
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
View File

@ -160,10 +160,24 @@ void device_queue_manager_init_cik(struct device_queue_manager_ops *ops);
void device_queue_manager_init_vi(struct device_queue_manager_ops *ops); void device_queue_manager_init_vi(struct device_queue_manager_ops *ops);
void program_sh_mem_settings(struct device_queue_manager *dqm, void program_sh_mem_settings(struct device_queue_manager *dqm,
struct qcm_process_device *qpd); struct qcm_process_device *qpd);
inline unsigned int get_sh_mem_bases_32(struct kfd_process_device *qpd);
inline unsigned int get_sh_mem_bases_nybble_64(struct kfd_process_device *pdd);
int init_pipelines(struct device_queue_manager *dqm, int init_pipelines(struct device_queue_manager *dqm,
unsigned int pipes_num, unsigned int first_pipe); unsigned int pipes_num, unsigned int first_pipe);
inline unsigned int get_pipes_num(struct device_queue_manager *dqm);
extern inline unsigned int get_sh_mem_bases_32(struct kfd_process_device *pdd)
{
return (pdd->lds_base >> 16) & 0xFF;
}
extern inline unsigned int
get_sh_mem_bases_nybble_64(struct kfd_process_device *pdd)
{
return (pdd->lds_base >> 60) & 0x0E;
}
extern inline unsigned int get_pipes_num(struct device_queue_manager *dqm)
{
BUG_ON(!dqm || !dqm->dev);
return dqm->dev->shared_resources.compute_pipe_count;
}
#endif /* KFD_DEVICE_QUEUE_MANAGER_H_ */ #endif /* KFD_DEVICE_QUEUE_MANAGER_H_ */