mirror of https://gitee.com/openkylin/linux.git
arm64: dts: hi6220: add coresight dt nodes
For detailed coresight topology, Hi6220 has 8xCA53 CPUs and each CPU has one Embedded Trace Macrocell (ETM); the CPU trace data is output to the cluster funnel. Due system has another CPU and one MCU, all of them transfer the trace data through trace bus (ATB) to SoC funnel; the SoC funnel is connected to Embedded Trace FIFO (ETF) with 8KB buffer; an non-configurable replicator is used to output trace data for two sinks, one is Embedded Trace Route (ETR) so trace data can be saved into DRAM, another is Trace Port Interface Unit (TPIU) for capturing trace data by external debugger. According to the Hi6220 coresight topology, this patch is to add coresight dt nodes. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Mike Leach <mike.leach@linaro.org> Cc: Guodong Xu <guodong.xu@linaro.org> Cc: Zhangfei Gao <zhangfei.gao@linaro.org> Cc: Haojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: Li Pengcheng <lipengcheng8@huawei.com> Signed-off-by: Li Zhong <lizhong11@hisilicon.com> Signed-off-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
This commit is contained in:
Li Pengcheng
Wei Xu
parent
2bd6bf03f4
commit
0b79842775
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@ -0,0 +1,381 @@
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/*
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* dtsi file for Hisilicon Hi6220 coresight
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*
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* Copyright (C) 2017 Hisilicon Ltd.
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*
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* Author: Pengcheng Li <lipengcheng8@huawei.com>
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* Leo Yan <leo.yan@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* publishhed by the Free Software Foundation.
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*
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*/
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/ {
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soc {
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funnel@f6401000 {
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compatible = "arm,coresight-funnel", "arm,primecell";
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reg = <0 0xf6401000 0 0x1000>;
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clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
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clock-names = "apb_pclk";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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soc_funnel_out: endpoint {
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remote-endpoint =
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<&etf_in>;
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};
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};
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port@1 {
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reg = <0>;
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soc_funnel_in: endpoint {
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slave-mode;
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remote-endpoint =
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<&acpu_funnel_out>;
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};
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};
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};
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};
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etf@f6402000 {
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compatible = "arm,coresight-tmc", "arm,primecell";
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reg = <0 0xf6402000 0 0x1000>;
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clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
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clock-names = "apb_pclk";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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etf_in: endpoint {
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slave-mode;
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remote-endpoint =
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<&soc_funnel_out>;
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};
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};
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port@1 {
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reg = <0>;
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etf_out: endpoint {
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remote-endpoint =
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<&replicator_in>;
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};
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};
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};
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};
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replicator {
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compatible = "arm,coresight-replicator";
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clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
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clock-names = "apb_pclk";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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replicator_in: endpoint {
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slave-mode;
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remote-endpoint =
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<&etf_out>;
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};
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};
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port@1 {
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reg = <0>;
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replicator_out0: endpoint {
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remote-endpoint =
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<&etr_in>;
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};
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};
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port@2 {
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reg = <1>;
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replicator_out1: endpoint {
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remote-endpoint =
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<&tpiu_in>;
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};
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};
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};
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};
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etr@f6404000 {
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compatible = "arm,coresight-tmc", "arm,primecell";
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reg = <0 0xf6404000 0 0x1000>;
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clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
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clock-names = "apb_pclk";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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etr_in: endpoint {
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slave-mode;
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remote-endpoint =
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<&replicator_out0>;
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};
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};
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};
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};
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tpiu@f6405000 {
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compatible = "arm,coresight-tpiu", "arm,primecell";
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reg = <0 0xf6405000 0 0x1000>;
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clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
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clock-names = "apb_pclk";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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tpiu_in: endpoint {
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slave-mode;
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remote-endpoint =
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<&replicator_out1>;
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};
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};
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};
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};
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funnel@f6501000 {
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compatible = "arm,coresight-funnel", "arm,primecell";
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reg = <0 0xf6501000 0 0x1000>;
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clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
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clock-names = "apb_pclk";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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acpu_funnel_out: endpoint {
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remote-endpoint =
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<&soc_funnel_in>;
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};
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};
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port@1 {
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reg = <0>;
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acpu_funnel_in0: endpoint {
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slave-mode;
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remote-endpoint =
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<&etm0_out>;
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};
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};
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port@2 {
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reg = <1>;
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acpu_funnel_in1: endpoint {
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slave-mode;
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remote-endpoint =
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<&etm1_out>;
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};
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};
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port@3 {
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reg = <2>;
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acpu_funnel_in2: endpoint {
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slave-mode;
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remote-endpoint =
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<&etm2_out>;
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};
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};
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port@4 {
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reg = <3>;
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acpu_funnel_in3: endpoint {
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slave-mode;
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remote-endpoint =
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<&etm3_out>;
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};
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};
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port@5 {
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reg = <4>;
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acpu_funnel_in4: endpoint {
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slave-mode;
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remote-endpoint =
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<&etm4_out>;
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};
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};
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port@6 {
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reg = <5>;
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acpu_funnel_in5: endpoint {
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slave-mode;
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remote-endpoint =
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<&etm5_out>;
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};
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};
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port@7 {
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reg = <6>;
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acpu_funnel_in6: endpoint {
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slave-mode;
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remote-endpoint =
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<&etm6_out>;
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};
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};
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port@8 {
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reg = <7>;
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acpu_funnel_in7: endpoint {
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slave-mode;
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remote-endpoint =
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<&etm7_out>;
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};
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};
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};
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};
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etm@f659c000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0 0xf659c000 0 0x1000>;
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clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
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clock-names = "apb_pclk";
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cpu = <&cpu0>;
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port {
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etm0_out: endpoint {
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remote-endpoint =
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<&acpu_funnel_in0>;
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};
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};
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};
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etm@f659d000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0 0xf659d000 0 0x1000>;
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clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
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clock-names = "apb_pclk";
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cpu = <&cpu1>;
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port {
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etm1_out: endpoint {
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remote-endpoint =
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<&acpu_funnel_in1>;
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};
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};
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};
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etm@f659e000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0 0xf659e000 0 0x1000>;
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clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
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clock-names = "apb_pclk";
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cpu = <&cpu2>;
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port {
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etm2_out: endpoint {
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remote-endpoint =
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<&acpu_funnel_in2>;
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};
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};
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};
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etm@f659f000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0 0xf659f000 0 0x1000>;
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clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
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clock-names = "apb_pclk";
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cpu = <&cpu3>;
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port {
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etm3_out: endpoint {
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remote-endpoint =
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<&acpu_funnel_in3>;
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};
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};
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};
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etm@f65dc000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0 0xf65dc000 0 0x1000>;
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clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
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clock-names = "apb_pclk";
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cpu = <&cpu4>;
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port {
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etm4_out: endpoint {
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remote-endpoint =
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<&acpu_funnel_in4>;
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};
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};
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};
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etm@f65dd000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0 0xf65dd000 0 0x1000>;
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clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
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clock-names = "apb_pclk";
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cpu = <&cpu5>;
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port {
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etm5_out: endpoint {
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remote-endpoint =
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<&acpu_funnel_in5>;
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};
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};
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};
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etm@f65de000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0 0xf65de000 0 0x1000>;
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clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
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clock-names = "apb_pclk";
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cpu = <&cpu6>;
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port {
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etm6_out: endpoint {
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remote-endpoint =
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<&acpu_funnel_in6>;
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};
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};
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};
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etm@f65df000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0 0xf65df000 0 0x1000>;
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clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
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clock-names = "apb_pclk";
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cpu = <&cpu7>;
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port {
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etm7_out: endpoint {
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remote-endpoint =
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<&acpu_funnel_in7>;
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};
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};
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};
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};
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};
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@ -986,3 +986,5 @@ debug@f65d6000 {
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};
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};
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};
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#include "hi6220-coresight.dtsi"
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