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drm/amdgpu: add amdgpu_gart_map function v2 

This allows us to write the mapped PTEs into
an IB instead of the table directly.

v2: fix build with debugfs enabled, remove unused assignment

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Christian König 2017-06-29 17:24:26 +02:00 committed by Alex Deucher
parent cc25188afd
commit 0c2c421e26
2 changed files with 51 additions and 14 deletions
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3
drivers/gpu/drm/amd/amdgpu/amdgpu.h
View File

@ -570,6 +570,9 @@ int amdgpu_gart_init(struct amdgpu_device *adev);
void amdgpu_gart_fini(struct amdgpu_device *adev); void amdgpu_gart_fini(struct amdgpu_device *adev);
int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset, int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
int pages); int pages);
int amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset,
int pages, dma_addr_t *dma_addr, uint64_t flags,
void *dst);
int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset, int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
int pages, struct page **pagelist, int pages, struct page **pagelist,
dma_addr_t *dma_addr, uint64_t flags); dma_addr_t *dma_addr, uint64_t flags);

60
drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
View File

@ -282,6 +282,41 @@ int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
return 0; return 0;
} }
/**
* amdgpu_gart_map - map dma_addresses into GART entries
*
* @adev: amdgpu_device pointer
* @offset: offset into the GPU's gart aperture
* @pages: number of pages to bind
* @dma_addr: DMA addresses of pages
*
* Map the dma_addresses into GART entries (all asics).
* Returns 0 for success, -EINVAL for failure.
*/
int amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset,
int pages, dma_addr_t *dma_addr, uint64_t flags,
void *dst)
{
uint64_t page_base;
unsigned i, j, t;
if (!adev->gart.ready) {
WARN(1, "trying to bind memory to uninitialized GART !\n");
return -EINVAL;
}
t = offset / AMDGPU_GPU_PAGE_SIZE;
for (i = 0; i < pages; i++) {
page_base = dma_addr[i];
for (j = 0; j < (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); j++, t++) {
amdgpu_gart_set_pte_pde(adev, dst, t, page_base, flags);
page_base += AMDGPU_GPU_PAGE_SIZE;
}
}
return 0;
}
/** /**
* amdgpu_gart_bind - bind pages into the gart page table * amdgpu_gart_bind - bind pages into the gart page table
* *
@ -299,31 +334,30 @@ int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
int pages, struct page **pagelist, dma_addr_t *dma_addr, int pages, struct page **pagelist, dma_addr_t *dma_addr,
uint64_t flags) uint64_t flags)
{ {
unsigned t; #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
unsigned p; unsigned i,t,p;
uint64_t page_base; #endif
int i, j; int r;
if (!adev->gart.ready) { if (!adev->gart.ready) {
WARN(1, "trying to bind memory to uninitialized GART !\n"); WARN(1, "trying to bind memory to uninitialized GART !\n");
return -EINVAL; return -EINVAL;
} }
#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
t = offset / AMDGPU_GPU_PAGE_SIZE; t = offset / AMDGPU_GPU_PAGE_SIZE;
p = t / (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); p = t / (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE);
for (i = 0; i < pages; i++, p++)
for (i = 0; i < pages; i++, p++) {
#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
adev->gart.pages[p] = pagelist[i]; adev->gart.pages[p] = pagelist[i];
#endif #endif
if (adev->gart.ptr) { if (adev->gart.ptr) {
page_base = dma_addr[i]; r = amdgpu_gart_map(adev, offset, pages, dma_addr, flags,
for (j = 0; j < (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); j++, t++) { adev->gart.ptr);
amdgpu_gart_set_pte_pde(adev, adev->gart.ptr, t, page_base, flags); if (r)
page_base += AMDGPU_GPU_PAGE_SIZE; return r;
}
}
} }
mb(); mb();
amdgpu_gart_flush_gpu_tlb(adev, 0); amdgpu_gart_flush_gpu_tlb(adev, 0);
return 0; return 0;