mirror of https://gitee.com/openkylin/linux.git
MIPS: Octeon: Rewrite interrupt handling code.
This includes conversion to new style irq_chip functions, and
correctly enabling/disabling per-CPU interrupts.
The hardware interrupt bit to irq number mapping is now done with a
flexible map, instead of by bit twiddling the irq number.
[ tglx: Adjusted to new irq_cpu_on/offline callbacks and
__irq_set_affinity_lock ]
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Cc: linux-mips@linux-mips.org
Cc: ralf@linux-mips.org
LKML-Reference: <1301081931-11240-5-git-send-email-ddaney@caviumnetworks.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This commit is contained in:
David Daney
Thomas Gleixner
parent
a458465641
commit
0c3263870f
File diff suppressed because it is too large
Load Diff
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@ -420,7 +420,6 @@ void octeon_user_io_init(void)
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void __init prom_init(void)
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{
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struct cvmx_sysinfo *sysinfo;
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const int coreid = cvmx_get_core_num();
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int i;
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int argc;
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#ifdef CONFIG_CAVIUM_RESERVE32
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@ -537,17 +536,6 @@ void __init prom_init(void)
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octeon_uart = octeon_get_boot_uart();
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/*
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* Disable All CIU Interrupts. The ones we need will be
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* enabled later. Read the SUM register so we know the write
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* completed.
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*/
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cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2)), 0);
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cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2 + 1)), 0);
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cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2)), 0);
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cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2 + 1)), 0);
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cvmx_read_csr(CVMX_CIU_INTX_SUM0((coreid * 2)));
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#ifdef CONFIG_SMP
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octeon_write_lcd("LinuxSMP");
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#else
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@ -171,12 +171,27 @@ static void octeon_boot_secondary(int cpu, struct task_struct *idle)
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* After we've done initial boot, this function is called to allow the
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* board code to clean up state, if needed
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*/
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static void octeon_init_secondary(void)
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static void __cpuinit octeon_init_secondary(void)
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{
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const int coreid = cvmx_get_core_num();
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union cvmx_ciu_intx_sum0 interrupt_enable;
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unsigned int sr;
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sr = set_c0_status(ST0_BEV);
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write_c0_ebase((u32)ebase);
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write_c0_status(sr);
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octeon_check_cpu_bist();
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octeon_init_cvmcount();
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octeon_irq_setup_secondary();
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raw_local_irq_enable();
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}
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/**
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* Callout to firmware before smp_init
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*
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*/
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void octeon_prepare_cpus(unsigned int max_cpus)
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{
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#ifdef CONFIG_HOTPLUG_CPU
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struct linux_app_boot_info *labi;
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@ -186,34 +201,6 @@ static void octeon_init_secondary(void)
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panic("The bootloader version on this board is incorrect.");
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#endif
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sr = set_c0_status(ST0_BEV);
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write_c0_ebase((u32)ebase);
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write_c0_status(sr);
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octeon_check_cpu_bist();
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octeon_init_cvmcount();
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/*
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pr_info("SMP: CPU%d (CoreId %lu) started\n", cpu, coreid);
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*/
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/* Enable Mailbox interrupts to this core. These are the only
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interrupts allowed on line 3 */
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cvmx_write_csr(CVMX_CIU_MBOX_CLRX(coreid), 0xffffffff);
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interrupt_enable.u64 = 0;
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interrupt_enable.s.mbox = 0x3;
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cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2)), interrupt_enable.u64);
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cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2 + 1)), 0);
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cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2)), 0);
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cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2 + 1)), 0);
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/* Enable core interrupt processing for 2,3 and 7 */
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set_c0_status(0x8c01);
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}
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/**
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* Callout to firmware before smp_init
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*
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*/
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void octeon_prepare_cpus(unsigned int max_cpus)
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{
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cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffffffff);
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if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt, IRQF_DISABLED,
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"mailbox0", mailbox_interrupt)) {
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@ -11,172 +11,91 @@
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#define NR_IRQS OCTEON_IRQ_LAST
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#define MIPS_CPU_IRQ_BASE OCTEON_IRQ_SW0
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/* 0 - 7 represent the i8259 master */
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#define OCTEON_IRQ_I8259M0 0
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#define OCTEON_IRQ_I8259M1 1
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#define OCTEON_IRQ_I8259M2 2
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#define OCTEON_IRQ_I8259M3 3
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#define OCTEON_IRQ_I8259M4 4
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#define OCTEON_IRQ_I8259M5 5
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#define OCTEON_IRQ_I8259M6 6
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#define OCTEON_IRQ_I8259M7 7
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/* 8 - 15 represent the i8259 slave */
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#define OCTEON_IRQ_I8259S0 8
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#define OCTEON_IRQ_I8259S1 9
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#define OCTEON_IRQ_I8259S2 10
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#define OCTEON_IRQ_I8259S3 11
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#define OCTEON_IRQ_I8259S4 12
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#define OCTEON_IRQ_I8259S5 13
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#define OCTEON_IRQ_I8259S6 14
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#define OCTEON_IRQ_I8259S7 15
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/* 16 - 23 represent the 8 MIPS standard interrupt sources */
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#define OCTEON_IRQ_SW0 16
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#define OCTEON_IRQ_SW1 17
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#define OCTEON_IRQ_CIU0 18
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#define OCTEON_IRQ_CIU1 19
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#define OCTEON_IRQ_CIU4 20
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#define OCTEON_IRQ_5 21
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#define OCTEON_IRQ_PERF 22
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#define OCTEON_IRQ_TIMER 23
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/* 24 - 87 represent the sources in CIU_INTX_EN0 */
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#define OCTEON_IRQ_WORKQ0 24
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#define OCTEON_IRQ_WORKQ1 25
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#define OCTEON_IRQ_WORKQ2 26
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#define OCTEON_IRQ_WORKQ3 27
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#define OCTEON_IRQ_WORKQ4 28
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#define OCTEON_IRQ_WORKQ5 29
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#define OCTEON_IRQ_WORKQ6 30
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#define OCTEON_IRQ_WORKQ7 31
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#define OCTEON_IRQ_WORKQ8 32
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#define OCTEON_IRQ_WORKQ9 33
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#define OCTEON_IRQ_WORKQ10 34
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#define OCTEON_IRQ_WORKQ11 35
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#define OCTEON_IRQ_WORKQ12 36
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#define OCTEON_IRQ_WORKQ13 37
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#define OCTEON_IRQ_WORKQ14 38
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#define OCTEON_IRQ_WORKQ15 39
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#define OCTEON_IRQ_GPIO0 40
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#define OCTEON_IRQ_GPIO1 41
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#define OCTEON_IRQ_GPIO2 42
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#define OCTEON_IRQ_GPIO3 43
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#define OCTEON_IRQ_GPIO4 44
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#define OCTEON_IRQ_GPIO5 45
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#define OCTEON_IRQ_GPIO6 46
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#define OCTEON_IRQ_GPIO7 47
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#define OCTEON_IRQ_GPIO8 48
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#define OCTEON_IRQ_GPIO9 49
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#define OCTEON_IRQ_GPIO10 50
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#define OCTEON_IRQ_GPIO11 51
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#define OCTEON_IRQ_GPIO12 52
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#define OCTEON_IRQ_GPIO13 53
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#define OCTEON_IRQ_GPIO14 54
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#define OCTEON_IRQ_GPIO15 55
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#define OCTEON_IRQ_MBOX0 56
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#define OCTEON_IRQ_MBOX1 57
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#define OCTEON_IRQ_UART0 58
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#define OCTEON_IRQ_UART1 59
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#define OCTEON_IRQ_PCI_INT0 60
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#define OCTEON_IRQ_PCI_INT1 61
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#define OCTEON_IRQ_PCI_INT2 62
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#define OCTEON_IRQ_PCI_INT3 63
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#define OCTEON_IRQ_PCI_MSI0 64
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#define OCTEON_IRQ_PCI_MSI1 65
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#define OCTEON_IRQ_PCI_MSI2 66
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#define OCTEON_IRQ_PCI_MSI3 67
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#define OCTEON_IRQ_RESERVED68 68 /* Summary of CIU_INT_SUM1 */
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#define OCTEON_IRQ_TWSI 69
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#define OCTEON_IRQ_RML 70
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#define OCTEON_IRQ_TRACE 71
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#define OCTEON_IRQ_GMX_DRP0 72
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#define OCTEON_IRQ_GMX_DRP1 73
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#define OCTEON_IRQ_IPD_DRP 74
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#define OCTEON_IRQ_KEY_ZERO 75
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#define OCTEON_IRQ_TIMER0 76
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#define OCTEON_IRQ_TIMER1 77
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#define OCTEON_IRQ_TIMER2 78
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#define OCTEON_IRQ_TIMER3 79
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#define OCTEON_IRQ_USB0 80
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#define OCTEON_IRQ_PCM 81
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#define OCTEON_IRQ_MPI 82
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#define OCTEON_IRQ_TWSI2 83
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#define OCTEON_IRQ_POWIQ 84
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#define OCTEON_IRQ_IPDPPTHR 85
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#define OCTEON_IRQ_MII0 86
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#define OCTEON_IRQ_BOOTDMA 87
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/* 88 - 151 represent the sources in CIU_INTX_EN1 */
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#define OCTEON_IRQ_WDOG0 88
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#define OCTEON_IRQ_WDOG1 89
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#define OCTEON_IRQ_WDOG2 90
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#define OCTEON_IRQ_WDOG3 91
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#define OCTEON_IRQ_WDOG4 92
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#define OCTEON_IRQ_WDOG5 93
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#define OCTEON_IRQ_WDOG6 94
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#define OCTEON_IRQ_WDOG7 95
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#define OCTEON_IRQ_WDOG8 96
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#define OCTEON_IRQ_WDOG9 97
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#define OCTEON_IRQ_WDOG10 98
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#define OCTEON_IRQ_WDOG11 99
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#define OCTEON_IRQ_WDOG12 100
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#define OCTEON_IRQ_WDOG13 101
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#define OCTEON_IRQ_WDOG14 102
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#define OCTEON_IRQ_WDOG15 103
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#define OCTEON_IRQ_UART2 104
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#define OCTEON_IRQ_USB1 105
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#define OCTEON_IRQ_MII1 106
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#define OCTEON_IRQ_RESERVED107 107
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#define OCTEON_IRQ_RESERVED108 108
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#define OCTEON_IRQ_RESERVED109 109
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#define OCTEON_IRQ_RESERVED110 110
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#define OCTEON_IRQ_RESERVED111 111
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#define OCTEON_IRQ_RESERVED112 112
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#define OCTEON_IRQ_RESERVED113 113
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#define OCTEON_IRQ_RESERVED114 114
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#define OCTEON_IRQ_RESERVED115 115
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#define OCTEON_IRQ_RESERVED116 116
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#define OCTEON_IRQ_RESERVED117 117
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#define OCTEON_IRQ_RESERVED118 118
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#define OCTEON_IRQ_RESERVED119 119
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#define OCTEON_IRQ_RESERVED120 120
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#define OCTEON_IRQ_RESERVED121 121
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#define OCTEON_IRQ_RESERVED122 122
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#define OCTEON_IRQ_RESERVED123 123
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#define OCTEON_IRQ_RESERVED124 124
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#define OCTEON_IRQ_RESERVED125 125
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#define OCTEON_IRQ_RESERVED126 126
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#define OCTEON_IRQ_RESERVED127 127
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#define OCTEON_IRQ_RESERVED128 128
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#define OCTEON_IRQ_RESERVED129 129
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#define OCTEON_IRQ_RESERVED130 130
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#define OCTEON_IRQ_RESERVED131 131
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#define OCTEON_IRQ_RESERVED132 132
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#define OCTEON_IRQ_RESERVED133 133
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#define OCTEON_IRQ_RESERVED134 134
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#define OCTEON_IRQ_RESERVED135 135
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#define OCTEON_IRQ_RESERVED136 136
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#define OCTEON_IRQ_RESERVED137 137
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#define OCTEON_IRQ_RESERVED138 138
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#define OCTEON_IRQ_RESERVED139 139
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#define OCTEON_IRQ_RESERVED140 140
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#define OCTEON_IRQ_RESERVED141 141
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#define OCTEON_IRQ_RESERVED142 142
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#define OCTEON_IRQ_RESERVED143 143
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#define OCTEON_IRQ_RESERVED144 144
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#define OCTEON_IRQ_RESERVED145 145
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#define OCTEON_IRQ_RESERVED146 146
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#define OCTEON_IRQ_RESERVED147 147
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#define OCTEON_IRQ_RESERVED148 148
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#define OCTEON_IRQ_RESERVED149 149
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#define OCTEON_IRQ_RESERVED150 150
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#define OCTEON_IRQ_RESERVED151 151
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enum octeon_irq {
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/* 1 - 8 represent the 8 MIPS standard interrupt sources */
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OCTEON_IRQ_SW0 = 1,
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OCTEON_IRQ_SW1,
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/* CIU0, CUI2, CIU4 are 3, 4, 5 */
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OCTEON_IRQ_5 = 6,
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OCTEON_IRQ_PERF,
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OCTEON_IRQ_TIMER,
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/* sources in CIU_INTX_EN0 */
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OCTEON_IRQ_WORKQ0,
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OCTEON_IRQ_GPIO0 = OCTEON_IRQ_WORKQ0 + 16,
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OCTEON_IRQ_WDOG0 = OCTEON_IRQ_GPIO0 + 16,
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OCTEON_IRQ_WDOG15 = OCTEON_IRQ_WDOG0 + 15,
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OCTEON_IRQ_MBOX0 = OCTEON_IRQ_WDOG0 + 16,
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OCTEON_IRQ_MBOX1,
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OCTEON_IRQ_UART0,
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OCTEON_IRQ_UART1,
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OCTEON_IRQ_UART2,
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OCTEON_IRQ_PCI_INT0,
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OCTEON_IRQ_PCI_INT1,
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OCTEON_IRQ_PCI_INT2,
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OCTEON_IRQ_PCI_INT3,
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OCTEON_IRQ_PCI_MSI0,
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OCTEON_IRQ_PCI_MSI1,
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OCTEON_IRQ_PCI_MSI2,
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OCTEON_IRQ_PCI_MSI3,
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OCTEON_IRQ_TWSI,
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OCTEON_IRQ_TWSI2,
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OCTEON_IRQ_RML,
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OCTEON_IRQ_TRACE0,
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OCTEON_IRQ_GMX_DRP0 = OCTEON_IRQ_TRACE0 + 4,
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OCTEON_IRQ_IPD_DRP = OCTEON_IRQ_GMX_DRP0 + 5,
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OCTEON_IRQ_KEY_ZERO,
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OCTEON_IRQ_TIMER0,
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OCTEON_IRQ_TIMER1,
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OCTEON_IRQ_TIMER2,
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OCTEON_IRQ_TIMER3,
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OCTEON_IRQ_USB0,
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OCTEON_IRQ_USB1,
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OCTEON_IRQ_PCM,
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OCTEON_IRQ_MPI,
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OCTEON_IRQ_POWIQ,
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OCTEON_IRQ_IPDPPTHR,
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OCTEON_IRQ_MII0,
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OCTEON_IRQ_MII1,
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OCTEON_IRQ_BOOTDMA,
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OCTEON_IRQ_NAND,
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OCTEON_IRQ_MIO, /* Summary of MIO_BOOT_ERR */
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OCTEON_IRQ_IOB, /* Summary of IOB_INT_SUM */
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OCTEON_IRQ_FPA, /* Summary of FPA_INT_SUM */
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OCTEON_IRQ_POW, /* Summary of POW_ECC_ERR */
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OCTEON_IRQ_L2C, /* Summary of L2C_INT_STAT */
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OCTEON_IRQ_IPD, /* Summary of IPD_INT_SUM */
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OCTEON_IRQ_PIP, /* Summary of PIP_INT_REG */
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OCTEON_IRQ_PKO, /* Summary of PKO_REG_ERROR */
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OCTEON_IRQ_ZIP, /* Summary of ZIP_ERROR */
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OCTEON_IRQ_TIM, /* Summary of TIM_REG_ERROR */
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OCTEON_IRQ_RAD, /* Summary of RAD_REG_ERROR */
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OCTEON_IRQ_KEY, /* Summary of KEY_INT_SUM */
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OCTEON_IRQ_DFA, /* Summary of DFA */
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OCTEON_IRQ_USBCTL, /* Summary of USBN0_INT_SUM */
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OCTEON_IRQ_SLI, /* Summary of SLI_INT_SUM */
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OCTEON_IRQ_DPI, /* Summary of DPI_INT_SUM */
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OCTEON_IRQ_AGX0, /* Summary of GMX0*+PCS0_INT*_REG */
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OCTEON_IRQ_AGL = OCTEON_IRQ_AGX0 + 5,
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OCTEON_IRQ_PTP,
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OCTEON_IRQ_PEM0,
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OCTEON_IRQ_PEM1,
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OCTEON_IRQ_SRIO0,
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OCTEON_IRQ_SRIO1,
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OCTEON_IRQ_LMC0,
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OCTEON_IRQ_DFM = OCTEON_IRQ_LMC0 + 4, /* Summary of DFM */
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OCTEON_IRQ_RST,
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};
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#ifdef CONFIG_PCI_MSI
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/* 152 - 215 represent the MSI interrupts 0-63 */
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#define OCTEON_IRQ_MSI_BIT0 152
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#define OCTEON_IRQ_MSI_LAST (OCTEON_IRQ_MSI_BIT0 + 255)
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/* 152 - 407 represent the MSI interrupts 0-255 */
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#define OCTEON_IRQ_MSI_BIT0 (OCTEON_IRQ_RST + 1)
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#define OCTEON_IRQ_LAST (OCTEON_IRQ_MSI_LAST + 1)
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#define OCTEON_IRQ_MSI_LAST (OCTEON_IRQ_MSI_BIT0 + 255)
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#define OCTEON_IRQ_LAST (OCTEON_IRQ_MSI_LAST + 1)
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#else
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#define OCTEON_IRQ_LAST 152
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#define OCTEON_IRQ_LAST (OCTEON_IRQ_RST + 1)
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#endif
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#endif
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@ -257,4 +257,6 @@ extern struct cvmx_bootinfo *octeon_bootinfo;
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extern uint64_t octeon_bootloader_entry_addr;
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extern void (*octeon_irq_setup_secondary)(void);
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#endif /* __ASM_OCTEON_OCTEON_H */
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@ -259,11 +259,11 @@ static DEFINE_RAW_SPINLOCK(octeon_irq_msi_lock);
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static u64 msi_rcv_reg[4];
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static u64 mis_ena_reg[4];
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static void octeon_irq_msi_enable_pcie(unsigned int irq)
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static void octeon_irq_msi_enable_pcie(struct irq_data *data)
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{
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u64 en;
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unsigned long flags;
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int msi_number = irq - OCTEON_IRQ_MSI_BIT0;
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int msi_number = data->irq - OCTEON_IRQ_MSI_BIT0;
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int irq_index = msi_number >> 6;
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int irq_bit = msi_number & 0x3f;
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@ -275,11 +275,11 @@ static void octeon_irq_msi_enable_pcie(unsigned int irq)
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raw_spin_unlock_irqrestore(&octeon_irq_msi_lock, flags);
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}
|
||||
|
||||
static void octeon_irq_msi_disable_pcie(unsigned int irq)
|
||||
static void octeon_irq_msi_disable_pcie(struct irq_data *data)
|
||||
{
|
||||
u64 en;
|
||||
unsigned long flags;
|
||||
int msi_number = irq - OCTEON_IRQ_MSI_BIT0;
|
||||
int msi_number = data->irq - OCTEON_IRQ_MSI_BIT0;
|
||||
int irq_index = msi_number >> 6;
|
||||
int irq_bit = msi_number & 0x3f;
|
||||
|
||||
|
|
@ -293,11 +293,11 @@ static void octeon_irq_msi_disable_pcie(unsigned int irq)
|
|||
|
||||
static struct irq_chip octeon_irq_chip_msi_pcie = {
|
||||
.name = "MSI",
|
||||
.enable = octeon_irq_msi_enable_pcie,
|
||||
.disable = octeon_irq_msi_disable_pcie,
|
||||
.irq_enable = octeon_irq_msi_enable_pcie,
|
||||
.irq_disable = octeon_irq_msi_disable_pcie,
|
||||
};
|
||||
|
||||
static void octeon_irq_msi_enable_pci(unsigned int irq)
|
||||
static void octeon_irq_msi_enable_pci(struct irq_data *data)
|
||||
{
|
||||
/*
|
||||
* Octeon PCI doesn't have the ability to mask/unmask MSI
|
||||
|
|
@ -308,15 +308,15 @@ static void octeon_irq_msi_enable_pci(unsigned int irq)
|
|||
*/
|
||||
}
|
||||
|
||||
static void octeon_irq_msi_disable_pci(unsigned int irq)
|
||||
static void octeon_irq_msi_disable_pci(struct irq_data *data)
|
||||
{
|
||||
/* See comment in enable */
|
||||
}
|
||||
|
||||
static struct irq_chip octeon_irq_chip_msi_pci = {
|
||||
.name = "MSI",
|
||||
.enable = octeon_irq_msi_enable_pci,
|
||||
.disable = octeon_irq_msi_disable_pci,
|
||||
.irq_enable = octeon_irq_msi_enable_pci,
|
||||
.irq_disable = octeon_irq_msi_disable_pci,
|
||||
};
|
||||
|
||||
/*
|
||||
|
|
|
|||
Loading…
Reference in New Issue