mirror of https://gitee.com/openkylin/linux.git
drm/amdgpu: add SI SMC support
Signed-off-by: Maruthi Bayyavarapu <maruthi.bayyavarapu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Maruthi Srinivas Bayyavarapu
Alex Deucher
parent
9139d731fd
commit
0c34f45368
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@ -0,0 +1,280 @@
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/*
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* Copyright 2011 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
|
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* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
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* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
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||||
*
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* The above copyright notice and this permission notice shall be included in
|
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Alex Deucher
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*/
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#include <linux/firmware.h>
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#include "drmP.h"
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#include "amdgpu.h"
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#include "si/sid.h"
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#include "ppsmc.h"
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#include "amdgpu_ucode.h"
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#include "sislands_smc.h"
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static int si_set_smc_sram_address(struct amdgpu_device *adev,
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u32 smc_address, u32 limit)
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{
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if (smc_address & 3)
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return -EINVAL;
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if ((smc_address + 3) > limit)
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return -EINVAL;
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WREG32(SMC_IND_INDEX_0, smc_address);
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WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0);
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return 0;
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}
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int si_copy_bytes_to_smc(struct amdgpu_device *adev,
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u32 smc_start_address,
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const u8 *src, u32 byte_count, u32 limit)
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{
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unsigned long flags;
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int ret = 0;
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u32 data, original_data, addr, extra_shift;
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if (smc_start_address & 3)
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return -EINVAL;
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if ((smc_start_address + byte_count) > limit)
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return -EINVAL;
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addr = smc_start_address;
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spin_lock_irqsave(&adev->smc_idx_lock, flags);
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while (byte_count >= 4) {
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/* SMC address space is BE */
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data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3];
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ret = si_set_smc_sram_address(adev, addr, limit);
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if (ret)
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goto done;
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WREG32(SMC_IND_DATA_0, data);
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src += 4;
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byte_count -= 4;
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addr += 4;
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}
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/* RMW for the final bytes */
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if (byte_count > 0) {
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data = 0;
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ret = si_set_smc_sram_address(adev, addr, limit);
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if (ret)
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goto done;
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original_data = RREG32(SMC_IND_DATA_0);
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extra_shift = 8 * (4 - byte_count);
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while (byte_count > 0) {
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/* SMC address space is BE */
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data = (data << 8) + *src++;
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byte_count--;
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}
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data <<= extra_shift;
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data |= (original_data & ~((~0UL) << extra_shift));
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ret = si_set_smc_sram_address(adev, addr, limit);
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if (ret)
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goto done;
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WREG32(SMC_IND_DATA_0, data);
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}
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done:
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spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
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return ret;
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}
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void si_start_smc(struct amdgpu_device *adev)
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{
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u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
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tmp &= ~RST_REG;
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WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
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}
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void si_reset_smc(struct amdgpu_device *adev)
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{
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u32 tmp;
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RREG32(CB_CGTT_SCLK_CTRL);
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RREG32(CB_CGTT_SCLK_CTRL);
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RREG32(CB_CGTT_SCLK_CTRL);
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RREG32(CB_CGTT_SCLK_CTRL);
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tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
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tmp |= RST_REG;
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WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
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}
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int si_program_jump_on_start(struct amdgpu_device *adev)
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{
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static const u8 data[] = { 0x0E, 0x00, 0x40, 0x40 };
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return si_copy_bytes_to_smc(adev, 0x0, data, 4, sizeof(data)+1);
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}
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void si_stop_smc_clock(struct amdgpu_device *adev)
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{
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u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
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tmp |= CK_DISABLE;
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WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp);
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}
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void si_start_smc_clock(struct amdgpu_device *adev)
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{
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u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
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tmp &= ~CK_DISABLE;
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WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp);
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}
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bool si_is_smc_running(struct amdgpu_device *adev)
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{
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u32 rst = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
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u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
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if (!(rst & RST_REG) && !(clk & CK_DISABLE))
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return true;
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return false;
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}
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PPSMC_Result si_send_msg_to_smc(struct amdgpu_device *adev, PPSMC_Msg msg)
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{
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u32 tmp;
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int i;
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if (!si_is_smc_running(adev))
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return PPSMC_Result_Failed;
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WREG32(SMC_MESSAGE_0, msg);
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for (i = 0; i < adev->usec_timeout; i++) {
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tmp = RREG32(SMC_RESP_0);
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if (tmp != 0)
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break;
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udelay(1);
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}
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tmp = RREG32(SMC_RESP_0);
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return (PPSMC_Result)tmp;
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}
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PPSMC_Result si_wait_for_smc_inactive(struct amdgpu_device *adev)
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{
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u32 tmp;
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int i;
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if (!si_is_smc_running(adev))
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return PPSMC_Result_OK;
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for (i = 0; i < adev->usec_timeout; i++) {
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tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
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if ((tmp & CKEN) == 0)
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break;
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udelay(1);
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}
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return PPSMC_Result_OK;
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}
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int si_load_smc_ucode(struct amdgpu_device *adev, u32 limit)
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{
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const struct smc_firmware_header_v1_0 *hdr;
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unsigned long flags;
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u32 ucode_start_address;
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u32 ucode_size;
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const u8 *src;
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u32 data;
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if (!adev->pm.fw)
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return -EINVAL;
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hdr = (const struct smc_firmware_header_v1_0 *)adev->pm.fw->data;
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amdgpu_ucode_print_smc_hdr(&hdr->header);
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ucode_start_address = le32_to_cpu(hdr->ucode_start_addr);
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ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes);
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src = (const u8 *)
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(adev->pm.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
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if (ucode_size & 3)
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return -EINVAL;
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spin_lock_irqsave(&adev->smc_idx_lock, flags);
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WREG32(SMC_IND_INDEX_0, ucode_start_address);
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WREG32_P(SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, ~AUTO_INCREMENT_IND_0);
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while (ucode_size >= 4) {
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/* SMC address space is BE */
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data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3];
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WREG32(SMC_IND_DATA_0, data);
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src += 4;
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ucode_size -= 4;
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}
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WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0);
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spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
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return 0;
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}
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int si_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,
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u32 *value, u32 limit)
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{
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unsigned long flags;
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int ret;
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spin_lock_irqsave(&adev->smc_idx_lock, flags);
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ret = si_set_smc_sram_address(adev, smc_address, limit);
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if (ret == 0)
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*value = RREG32(SMC_IND_DATA_0);
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spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
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return ret;
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}
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int si_write_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,
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u32 value, u32 limit)
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{
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unsigned long flags;
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int ret;
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spin_lock_irqsave(&adev->smc_idx_lock, flags);
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ret = si_set_smc_sram_address(adev, smc_address, limit);
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if (ret == 0)
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WREG32(SMC_IND_DATA_0, value);
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spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
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return ret;
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}
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@ -0,0 +1,423 @@
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/*
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* Copyright 2013 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
|
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* to deal in the Software without restriction, including without limitation
|
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
|
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef PP_SISLANDS_SMC_H
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#define PP_SISLANDS_SMC_H
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#include "ppsmc.h"
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#pragma pack(push, 1)
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#define SISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE 16
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struct PP_SIslands_Dpm2PerfLevel
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{
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uint8_t MaxPS;
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uint8_t TgtAct;
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uint8_t MaxPS_StepInc;
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uint8_t MaxPS_StepDec;
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uint8_t PSSamplingTime;
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uint8_t NearTDPDec;
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uint8_t AboveSafeInc;
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uint8_t BelowSafeInc;
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uint8_t PSDeltaLimit;
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uint8_t PSDeltaWin;
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uint16_t PwrEfficiencyRatio;
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uint8_t Reserved[4];
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};
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typedef struct PP_SIslands_Dpm2PerfLevel PP_SIslands_Dpm2PerfLevel;
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struct PP_SIslands_DPM2Status
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{
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uint32_t dpm2Flags;
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uint8_t CurrPSkip;
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uint8_t CurrPSkipPowerShift;
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uint8_t CurrPSkipTDP;
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uint8_t CurrPSkipOCP;
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uint8_t MaxSPLLIndex;
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uint8_t MinSPLLIndex;
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uint8_t CurrSPLLIndex;
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uint8_t InfSweepMode;
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uint8_t InfSweepDir;
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uint8_t TDPexceeded;
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uint8_t reserved;
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uint8_t SwitchDownThreshold;
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uint32_t SwitchDownCounter;
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uint32_t SysScalingFactor;
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};
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typedef struct PP_SIslands_DPM2Status PP_SIslands_DPM2Status;
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struct PP_SIslands_DPM2Parameters
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{
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uint32_t TDPLimit;
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uint32_t NearTDPLimit;
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uint32_t SafePowerLimit;
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uint32_t PowerBoostLimit;
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uint32_t MinLimitDelta;
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};
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typedef struct PP_SIslands_DPM2Parameters PP_SIslands_DPM2Parameters;
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struct PP_SIslands_PAPMStatus
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{
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uint32_t EstimatedDGPU_T;
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uint32_t EstimatedDGPU_P;
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uint32_t EstimatedAPU_T;
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uint32_t EstimatedAPU_P;
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uint8_t dGPU_T_Limit_Exceeded;
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uint8_t reserved[3];
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};
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typedef struct PP_SIslands_PAPMStatus PP_SIslands_PAPMStatus;
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struct PP_SIslands_PAPMParameters
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{
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uint32_t NearTDPLimitTherm;
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uint32_t NearTDPLimitPAPM;
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uint32_t PlatformPowerLimit;
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uint32_t dGPU_T_Limit;
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uint32_t dGPU_T_Warning;
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uint32_t dGPU_T_Hysteresis;
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};
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typedef struct PP_SIslands_PAPMParameters PP_SIslands_PAPMParameters;
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struct SISLANDS_SMC_SCLK_VALUE
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{
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uint32_t vCG_SPLL_FUNC_CNTL;
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uint32_t vCG_SPLL_FUNC_CNTL_2;
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uint32_t vCG_SPLL_FUNC_CNTL_3;
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uint32_t vCG_SPLL_FUNC_CNTL_4;
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uint32_t vCG_SPLL_SPREAD_SPECTRUM;
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uint32_t vCG_SPLL_SPREAD_SPECTRUM_2;
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uint32_t sclk_value;
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};
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typedef struct SISLANDS_SMC_SCLK_VALUE SISLANDS_SMC_SCLK_VALUE;
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struct SISLANDS_SMC_MCLK_VALUE
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{
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uint32_t vMPLL_FUNC_CNTL;
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uint32_t vMPLL_FUNC_CNTL_1;
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uint32_t vMPLL_FUNC_CNTL_2;
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uint32_t vMPLL_AD_FUNC_CNTL;
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uint32_t vMPLL_DQ_FUNC_CNTL;
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uint32_t vMCLK_PWRMGT_CNTL;
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uint32_t vDLL_CNTL;
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uint32_t vMPLL_SS;
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uint32_t vMPLL_SS2;
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uint32_t mclk_value;
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};
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typedef struct SISLANDS_SMC_MCLK_VALUE SISLANDS_SMC_MCLK_VALUE;
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struct SISLANDS_SMC_VOLTAGE_VALUE
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{
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uint16_t value;
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uint8_t index;
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uint8_t phase_settings;
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};
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typedef struct SISLANDS_SMC_VOLTAGE_VALUE SISLANDS_SMC_VOLTAGE_VALUE;
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struct SISLANDS_SMC_HW_PERFORMANCE_LEVEL
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{
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uint8_t ACIndex;
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uint8_t displayWatermark;
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uint8_t gen2PCIE;
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uint8_t UVDWatermark;
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uint8_t VCEWatermark;
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uint8_t strobeMode;
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uint8_t mcFlags;
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uint8_t padding;
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uint32_t aT;
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uint32_t bSP;
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SISLANDS_SMC_SCLK_VALUE sclk;
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SISLANDS_SMC_MCLK_VALUE mclk;
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SISLANDS_SMC_VOLTAGE_VALUE vddc;
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SISLANDS_SMC_VOLTAGE_VALUE mvdd;
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SISLANDS_SMC_VOLTAGE_VALUE vddci;
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SISLANDS_SMC_VOLTAGE_VALUE std_vddc;
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uint8_t hysteresisUp;
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uint8_t hysteresisDown;
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uint8_t stateFlags;
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uint8_t arbRefreshState;
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uint32_t SQPowerThrottle;
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uint32_t SQPowerThrottle_2;
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uint32_t MaxPoweredUpCU;
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SISLANDS_SMC_VOLTAGE_VALUE high_temp_vddc;
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SISLANDS_SMC_VOLTAGE_VALUE low_temp_vddc;
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uint32_t reserved[2];
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PP_SIslands_Dpm2PerfLevel dpm2;
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};
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#define SISLANDS_SMC_STROBE_RATIO 0x0F
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#define SISLANDS_SMC_STROBE_ENABLE 0x10
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||||
|
||||
#define SISLANDS_SMC_MC_EDC_RD_FLAG 0x01
|
||||
#define SISLANDS_SMC_MC_EDC_WR_FLAG 0x02
|
||||
#define SISLANDS_SMC_MC_RTT_ENABLE 0x04
|
||||
#define SISLANDS_SMC_MC_STUTTER_EN 0x08
|
||||
#define SISLANDS_SMC_MC_PG_EN 0x10
|
||||
|
||||
typedef struct SISLANDS_SMC_HW_PERFORMANCE_LEVEL SISLANDS_SMC_HW_PERFORMANCE_LEVEL;
|
||||
|
||||
struct SISLANDS_SMC_SWSTATE
|
||||
{
|
||||
uint8_t flags;
|
||||
uint8_t levelCount;
|
||||
uint8_t padding2;
|
||||
uint8_t padding3;
|
||||
SISLANDS_SMC_HW_PERFORMANCE_LEVEL levels[1];
|
||||
};
|
||||
|
||||
typedef struct SISLANDS_SMC_SWSTATE SISLANDS_SMC_SWSTATE;
|
||||
|
||||
#define SISLANDS_SMC_VOLTAGEMASK_VDDC 0
|
||||
#define SISLANDS_SMC_VOLTAGEMASK_MVDD 1
|
||||
#define SISLANDS_SMC_VOLTAGEMASK_VDDCI 2
|
||||
#define SISLANDS_SMC_VOLTAGEMASK_MAX 4
|
||||
|
||||
struct SISLANDS_SMC_VOLTAGEMASKTABLE
|
||||
{
|
||||
uint32_t lowMask[SISLANDS_SMC_VOLTAGEMASK_MAX];
|
||||
};
|
||||
|
||||
typedef struct SISLANDS_SMC_VOLTAGEMASKTABLE SISLANDS_SMC_VOLTAGEMASKTABLE;
|
||||
|
||||
#define SISLANDS_MAX_NO_VREG_STEPS 32
|
||||
|
||||
struct SISLANDS_SMC_STATETABLE
|
||||
{
|
||||
uint8_t thermalProtectType;
|
||||
uint8_t systemFlags;
|
||||
uint8_t maxVDDCIndexInPPTable;
|
||||
uint8_t extraFlags;
|
||||
uint32_t lowSMIO[SISLANDS_MAX_NO_VREG_STEPS];
|
||||
SISLANDS_SMC_VOLTAGEMASKTABLE voltageMaskTable;
|
||||
SISLANDS_SMC_VOLTAGEMASKTABLE phaseMaskTable;
|
||||
PP_SIslands_DPM2Parameters dpm2Params;
|
||||
SISLANDS_SMC_SWSTATE initialState;
|
||||
SISLANDS_SMC_SWSTATE ACPIState;
|
||||
SISLANDS_SMC_SWSTATE ULVState;
|
||||
SISLANDS_SMC_SWSTATE driverState;
|
||||
SISLANDS_SMC_HW_PERFORMANCE_LEVEL dpmLevels[SISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1];
|
||||
};
|
||||
|
||||
typedef struct SISLANDS_SMC_STATETABLE SISLANDS_SMC_STATETABLE;
|
||||
|
||||
#define SI_SMC_SOFT_REGISTER_mclk_chg_timeout 0x0
|
||||
#define SI_SMC_SOFT_REGISTER_delay_vreg 0xC
|
||||
#define SI_SMC_SOFT_REGISTER_delay_acpi 0x28
|
||||
#define SI_SMC_SOFT_REGISTER_seq_index 0x5C
|
||||
#define SI_SMC_SOFT_REGISTER_mvdd_chg_time 0x60
|
||||
#define SI_SMC_SOFT_REGISTER_mclk_switch_lim 0x70
|
||||
#define SI_SMC_SOFT_REGISTER_watermark_threshold 0x78
|
||||
#define SI_SMC_SOFT_REGISTER_phase_shedding_delay 0x88
|
||||
#define SI_SMC_SOFT_REGISTER_ulv_volt_change_delay 0x8C
|
||||
#define SI_SMC_SOFT_REGISTER_mc_block_delay 0x98
|
||||
#define SI_SMC_SOFT_REGISTER_ticks_per_us 0xA8
|
||||
#define SI_SMC_SOFT_REGISTER_crtc_index 0xC4
|
||||
#define SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min 0xC8
|
||||
#define SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max 0xCC
|
||||
#define SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width 0xF4
|
||||
#define SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen 0xFC
|
||||
#define SI_SMC_SOFT_REGISTER_vr_hot_gpio 0x100
|
||||
#define SI_SMC_SOFT_REGISTER_svi_rework_plat_type 0x118
|
||||
#define SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd 0x11c
|
||||
#define SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc 0x120
|
||||
|
||||
struct PP_SIslands_FanTable
|
||||
{
|
||||
uint8_t fdo_mode;
|
||||
uint8_t padding;
|
||||
int16_t temp_min;
|
||||
int16_t temp_med;
|
||||
int16_t temp_max;
|
||||
int16_t slope1;
|
||||
int16_t slope2;
|
||||
int16_t fdo_min;
|
||||
int16_t hys_up;
|
||||
int16_t hys_down;
|
||||
int16_t hys_slope;
|
||||
int16_t temp_resp_lim;
|
||||
int16_t temp_curr;
|
||||
int16_t slope_curr;
|
||||
int16_t pwm_curr;
|
||||
uint32_t refresh_period;
|
||||
int16_t fdo_max;
|
||||
uint8_t temp_src;
|
||||
int8_t padding2;
|
||||
};
|
||||
|
||||
typedef struct PP_SIslands_FanTable PP_SIslands_FanTable;
|
||||
|
||||
#define SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES 16
|
||||
#define SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES 32
|
||||
|
||||
#define SMC_SISLANDS_SCALE_I 7
|
||||
#define SMC_SISLANDS_SCALE_R 12
|
||||
|
||||
struct PP_SIslands_CacConfig
|
||||
{
|
||||
uint16_t cac_lkge_lut[SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES];
|
||||
uint32_t lkge_lut_V0;
|
||||
uint32_t lkge_lut_Vstep;
|
||||
uint32_t WinTime;
|
||||
uint32_t R_LL;
|
||||
uint32_t calculation_repeats;
|
||||
uint32_t l2numWin_TDP;
|
||||
uint32_t dc_cac;
|
||||
uint8_t lts_truncate_n;
|
||||
uint8_t SHIFT_N;
|
||||
uint8_t log2_PG_LKG_SCALE;
|
||||
uint8_t cac_temp;
|
||||
uint32_t lkge_lut_T0;
|
||||
uint32_t lkge_lut_Tstep;
|
||||
};
|
||||
|
||||
typedef struct PP_SIslands_CacConfig PP_SIslands_CacConfig;
|
||||
|
||||
#define SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE 16
|
||||
#define SMC_SISLANDS_MC_REGISTER_ARRAY_SET_COUNT 20
|
||||
|
||||
struct SMC_SIslands_MCRegisterAddress
|
||||
{
|
||||
uint16_t s0;
|
||||
uint16_t s1;
|
||||
};
|
||||
|
||||
typedef struct SMC_SIslands_MCRegisterAddress SMC_SIslands_MCRegisterAddress;
|
||||
|
||||
struct SMC_SIslands_MCRegisterSet
|
||||
{
|
||||
uint32_t value[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE];
|
||||
};
|
||||
|
||||
typedef struct SMC_SIslands_MCRegisterSet SMC_SIslands_MCRegisterSet;
|
||||
|
||||
struct SMC_SIslands_MCRegisters
|
||||
{
|
||||
uint8_t last;
|
||||
uint8_t reserved[3];
|
||||
SMC_SIslands_MCRegisterAddress address[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE];
|
||||
SMC_SIslands_MCRegisterSet data[SMC_SISLANDS_MC_REGISTER_ARRAY_SET_COUNT];
|
||||
};
|
||||
|
||||
typedef struct SMC_SIslands_MCRegisters SMC_SIslands_MCRegisters;
|
||||
|
||||
struct SMC_SIslands_MCArbDramTimingRegisterSet
|
||||
{
|
||||
uint32_t mc_arb_dram_timing;
|
||||
uint32_t mc_arb_dram_timing2;
|
||||
uint8_t mc_arb_rfsh_rate;
|
||||
uint8_t mc_arb_burst_time;
|
||||
uint8_t padding[2];
|
||||
};
|
||||
|
||||
typedef struct SMC_SIslands_MCArbDramTimingRegisterSet SMC_SIslands_MCArbDramTimingRegisterSet;
|
||||
|
||||
struct SMC_SIslands_MCArbDramTimingRegisters
|
||||
{
|
||||
uint8_t arb_current;
|
||||
uint8_t reserved[3];
|
||||
SMC_SIslands_MCArbDramTimingRegisterSet data[16];
|
||||
};
|
||||
|
||||
typedef struct SMC_SIslands_MCArbDramTimingRegisters SMC_SIslands_MCArbDramTimingRegisters;
|
||||
|
||||
struct SMC_SISLANDS_SPLL_DIV_TABLE
|
||||
{
|
||||
uint32_t freq[256];
|
||||
uint32_t ss[256];
|
||||
};
|
||||
|
||||
#define SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK 0x01ffffff
|
||||
#define SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT 0
|
||||
#define SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK 0xfe000000
|
||||
#define SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT 25
|
||||
#define SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK 0x000fffff
|
||||
#define SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT 0
|
||||
#define SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK 0xfff00000
|
||||
#define SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT 20
|
||||
|
||||
typedef struct SMC_SISLANDS_SPLL_DIV_TABLE SMC_SISLANDS_SPLL_DIV_TABLE;
|
||||
|
||||
#define SMC_SISLANDS_DTE_MAX_FILTER_STAGES 5
|
||||
|
||||
#define SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE 16
|
||||
|
||||
struct Smc_SIslands_DTE_Configuration
|
||||
{
|
||||
uint32_t tau[SMC_SISLANDS_DTE_MAX_FILTER_STAGES];
|
||||
uint32_t R[SMC_SISLANDS_DTE_MAX_FILTER_STAGES];
|
||||
uint32_t K;
|
||||
uint32_t T0;
|
||||
uint32_t MaxT;
|
||||
uint8_t WindowSize;
|
||||
uint8_t Tdep_count;
|
||||
uint8_t temp_select;
|
||||
uint8_t DTE_mode;
|
||||
uint8_t T_limits[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];
|
||||
uint32_t Tdep_tau[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];
|
||||
uint32_t Tdep_R[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];
|
||||
uint32_t Tthreshold;
|
||||
};
|
||||
|
||||
typedef struct Smc_SIslands_DTE_Configuration Smc_SIslands_DTE_Configuration;
|
||||
|
||||
#define SMC_SISLANDS_DTE_STATUS_FLAG_DTE_ON 1
|
||||
|
||||
#define SISLANDS_SMC_FIRMWARE_HEADER_LOCATION 0x10000
|
||||
|
||||
#define SISLANDS_SMC_FIRMWARE_HEADER_version 0x0
|
||||
#define SISLANDS_SMC_FIRMWARE_HEADER_flags 0x4
|
||||
#define SISLANDS_SMC_FIRMWARE_HEADER_softRegisters 0xC
|
||||
#define SISLANDS_SMC_FIRMWARE_HEADER_stateTable 0x10
|
||||
#define SISLANDS_SMC_FIRMWARE_HEADER_fanTable 0x14
|
||||
#define SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable 0x18
|
||||
#define SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable 0x24
|
||||
#define SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable 0x30
|
||||
#define SISLANDS_SMC_FIRMWARE_HEADER_spllTable 0x38
|
||||
#define SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration 0x40
|
||||
#define SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters 0x48
|
||||
|
||||
#pragma pack(pop)
|
||||
|
||||
int si_copy_bytes_to_smc(struct amdgpu_device *adev,
|
||||
u32 smc_start_address,
|
||||
const u8 *src, u32 byte_count, u32 limit);
|
||||
void si_start_smc(struct amdgpu_device *adev);
|
||||
void si_reset_smc(struct amdgpu_device *adev);
|
||||
int si_program_jump_on_start(struct amdgpu_device *adev);
|
||||
void si_stop_smc_clock(struct amdgpu_device *adev);
|
||||
void si_start_smc_clock(struct amdgpu_device *adev);
|
||||
bool si_is_smc_running(struct amdgpu_device *adev);
|
||||
PPSMC_Result si_send_msg_to_smc(struct amdgpu_device *adev, PPSMC_Msg msg);
|
||||
PPSMC_Result si_wait_for_smc_inactive(struct amdgpu_device *adev);
|
||||
int si_load_smc_ucode(struct amdgpu_device *adev, u32 limit);
|
||||
int si_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,
|
||||
u32 *value, u32 limit);
|
||||
int si_write_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,
|
||||
u32 value, u32 limit);
|
||||
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue