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ath9k: Fix regulatory compliance 

Adjusting the CCA registers for maximum permissible
noise floor in ETSI/Japan domains has to be done for
all AR9003 family chips.

Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Sujith Manoharan 2013-12-06 16:28:50 +05:30 committed by John W. Linville
parent ca488b921e
commit 0c7c2bb4da
2 changed files with 6 additions and 5 deletions
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5
drivers/net/wireless/ath/ath9k/ar9003_phy.h
View File

@ -341,14 +341,15 @@
#define AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ -95 #define AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ -95
#define AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ -100 #define AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ -100
#define AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ -95
#define AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ -100
#define AR_PHY_CCA_NOM_VAL_9462_2GHZ -127 #define AR_PHY_CCA_NOM_VAL_9462_2GHZ -127
#define AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ -127 #define AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ -127
#define AR_PHY_CCA_MAX_GOOD_VAL_9462_2GHZ -60 #define AR_PHY_CCA_MAX_GOOD_VAL_9462_2GHZ -60
#define AR_PHY_CCA_MAX_GOOD_VAL_9462_FCC_2GHZ -95
#define AR_PHY_CCA_NOM_VAL_9462_5GHZ -127 #define AR_PHY_CCA_NOM_VAL_9462_5GHZ -127
#define AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ -127 #define AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ -127
#define AR_PHY_CCA_MAX_GOOD_VAL_9462_5GHZ -60 #define AR_PHY_CCA_MAX_GOOD_VAL_9462_5GHZ -60
#define AR_PHY_CCA_MAX_GOOD_VAL_9462_FCC_5GHZ -100
#define AR_PHY_CCA_NOM_VAL_9330_2GHZ -118 #define AR_PHY_CCA_NOM_VAL_9330_2GHZ -118

6
drivers/net/wireless/ath/ath9k/hw.c
View File

@ -548,11 +548,11 @@ static int ath9k_hw_post_init(struct ath_hw *ah)
* EEPROM needs to be initialized before we do this. * EEPROM needs to be initialized before we do this.
* This is required for regulatory compliance. * This is required for regulatory compliance.
*/ */
if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { if (AR_SREV_9300_20_OR_LATER(ah)) {
u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0); u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
if ((regdmn & 0xF0) == CTL_FCC) { if ((regdmn & 0xF0) == CTL_FCC) {
ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9462_FCC_2GHZ; ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ;
ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9462_FCC_5GHZ; ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ;
} }
} }