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PCI: brcmstb: support BCM4908 with external PERST# signal controller 

BCM4908 uses external MISC block for controlling PERST# signal. Use it
as a reset controller.

Link: https://lore.kernel.org/r/20201210180421.7230-3-zajec5@gmail.com
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
This commit is contained in:
Rafał Miłecki 2020-12-10 19:04:21 +01:00 committed by Lorenzo Pieralisi
parent f435ce7ebf
commit 0cdfaceb98
2 changed files with 33 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/pci/controller/Kconfig
View File

@ -273,7 +273,7 @@ config VMD
config PCIE_BRCMSTB config PCIE_BRCMSTB
tristate "Broadcom Brcmstb PCIe host controller" tristate "Broadcom Brcmstb PCIe host controller"
depends on ARCH_BRCMSTB || ARCH_BCM2835 || COMPILE_TEST depends on ARCH_BRCMSTB || ARCH_BCM2835 || ARCH_BCM4908 || COMPILE_TEST
depends on OF depends on OF
depends on PCI_MSI_IRQ_DOMAIN depends on PCI_MSI_IRQ_DOMAIN
default ARCH_BRCMSTB default ARCH_BRCMSTB

32
drivers/pci/controller/pcie-brcmstb.c
View File

@ -97,6 +97,7 @@
#define PCIE_MISC_REVISION 0x406c #define PCIE_MISC_REVISION 0x406c
#define BRCM_PCIE_HW_REV_33 0x0303 #define BRCM_PCIE_HW_REV_33 0x0303
#define BRCM_PCIE_HW_REV_3_20 0x0320
#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070
#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000
@ -187,6 +188,7 @@
struct brcm_pcie; struct brcm_pcie;
static inline void brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32 val); static inline void brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32 val);
static inline void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val); static inline void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val);
static inline void brcm_pcie_perst_set_4908(struct brcm_pcie *pcie, u32 val);
static inline void brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val); static inline void brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val);
static inline void brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val); static inline void brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val);
@ -203,6 +205,7 @@ enum {
enum pcie_type { enum pcie_type {
GENERIC, GENERIC,
BCM4908,
BCM7278, BCM7278,
BCM2711, BCM2711,
}; };
@ -227,6 +230,13 @@ static const struct pcie_cfg_data generic_cfg = {
.bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic, .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
}; };
static const struct pcie_cfg_data bcm4908_cfg = {
.offsets = pcie_offsets,
.type = BCM4908,
.perst_set = brcm_pcie_perst_set_4908,
.bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
};
static const int pcie_offset_bcm7278[] = { static const int pcie_offset_bcm7278[] = {
[RGR1_SW_INIT_1] = 0xc010, [RGR1_SW_INIT_1] = 0xc010,
[EXT_CFG_INDEX] = 0x9000, [EXT_CFG_INDEX] = 0x9000,
@ -279,6 +289,7 @@ struct brcm_pcie {
const int *reg_offsets; const int *reg_offsets;
enum pcie_type type; enum pcie_type type;
struct reset_control *rescal; struct reset_control *rescal;
struct reset_control *perst_reset;
int num_memc; int num_memc;
u64 memc_size[PCIE_BRCM_MAX_MEMC]; u64 memc_size[PCIE_BRCM_MAX_MEMC];
u32 hw_rev; u32 hw_rev;
@ -735,6 +746,17 @@ static inline void brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32
writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
} }
static inline void brcm_pcie_perst_set_4908(struct brcm_pcie *pcie, u32 val)
{
if (WARN_ONCE(!pcie->perst_reset, "missing PERST# reset controller\n"))
return;
if (val)
reset_control_assert(pcie->perst_reset);
else
reset_control_deassert(pcie->perst_reset);
}
static inline void brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val) static inline void brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val)
{ {
u32 tmp; u32 tmp;
@ -1194,6 +1216,7 @@ static int brcm_pcie_remove(struct platform_device *pdev)
static const struct of_device_id brcm_pcie_match[] = { static const struct of_device_id brcm_pcie_match[] = {
{ .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg }, { .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg },
{ .compatible = "brcm,bcm4908-pcie", .data = &bcm4908_cfg },
{ .compatible = "brcm,bcm7211-pcie", .data = &generic_cfg }, { .compatible = "brcm,bcm7211-pcie", .data = &generic_cfg },
{ .compatible = "brcm,bcm7278-pcie", .data = &bcm7278_cfg }, { .compatible = "brcm,bcm7278-pcie", .data = &bcm7278_cfg },
{ .compatible = "brcm,bcm7216-pcie", .data = &bcm7278_cfg }, { .compatible = "brcm,bcm7216-pcie", .data = &bcm7278_cfg },
@ -1250,6 +1273,11 @@ static int brcm_pcie_probe(struct platform_device *pdev)
clk_disable_unprepare(pcie->clk); clk_disable_unprepare(pcie->clk);
return PTR_ERR(pcie->rescal); return PTR_ERR(pcie->rescal);
} }
pcie->perst_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "perst");
if (IS_ERR(pcie->perst_reset)) {
clk_disable_unprepare(pcie->clk);
return PTR_ERR(pcie->perst_reset);
}
ret = reset_control_deassert(pcie->rescal); ret = reset_control_deassert(pcie->rescal);
if (ret) if (ret)
@ -1267,6 +1295,10 @@ static int brcm_pcie_probe(struct platform_device *pdev)
goto fail; goto fail;
pcie->hw_rev = readl(pcie->base + PCIE_MISC_REVISION); pcie->hw_rev = readl(pcie->base + PCIE_MISC_REVISION);
if (pcie->type == BCM4908 && pcie->hw_rev >= BRCM_PCIE_HW_REV_3_20) {
dev_err(pcie->dev, "hardware revision with unsupported PERST# setup\n");
goto fail;
}
msi_np = of_parse_phandle(pcie->np, "msi-parent", 0); msi_np = of_parse_phandle(pcie->np, "msi-parent", 0);
if (pci_msi_enabled() && msi_np == pcie->np) { if (pci_msi_enabled() && msi_np == pcie->np) {