mirror of https://gitee.com/openkylin/linux.git
xtensa: add support for the XTFPGA boards
The Avnet LX60/LX110/LX200 board is an FPGA board that can be configured with an Xtensa processor and an OpenCores Ethernet device. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Chris Zankel <chris@zankel.net>
This commit is contained in:
Max Filippov
Chris Zankel
parent
da844a8177
commit
0d456bad36
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@ -151,6 +151,15 @@ config XTENSA_PLATFORM_S6105
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select SERIAL_CONSOLE
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select NO_IOPORT
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config XTENSA_PLATFORM_XTFPGA
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bool "XTFPGA"
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select SERIAL_CONSOLE
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select ETHOC
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select XTENSA_CALIBRATE_CCOUNT
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help
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XTFPGA is the name of Tensilica board family (LX60, LX110, LX200, ML605).
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This hardware is capable of running a full Linux distribution.
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endchoice
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@ -38,6 +38,7 @@ endif
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platform-$(CONFIG_XTENSA_PLATFORM_XT2000) := xt2000
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platform-$(CONFIG_XTENSA_PLATFORM_ISS) := iss
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platform-$(CONFIG_XTENSA_PLATFORM_S6105) := s6105
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platform-$(CONFIG_XTENSA_PLATFORM_XTFPGA) := xtfpga
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PLATFORM = $(platform-y)
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export PLATFORM
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@ -23,6 +23,7 @@ subdir-y := lib
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bootdir-$(CONFIG_XTENSA_PLATFORM_ISS) += boot-elf
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bootdir-$(CONFIG_XTENSA_PLATFORM_XT2000) += boot-redboot boot-elf boot-uboot
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bootdir-$(CONFIG_XTENSA_PLATFORM_XTFPGA) += boot-redboot boot-elf boot-uboot
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BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_BUILTIN_DTB)).dtb.o
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@ -0,0 +1,9 @@
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# Makefile for the Tensilica xtavnet Emulation Board
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#
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# Note! Dependencies are done automagically by 'make dep', which also
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# removes any old dependencies. DON'T put your own dependencies here
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# unless it's something special (ie not a .c file).
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#
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# Note 2! The CFLAGS definitions are in the main makefile...
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obj-y = setup.o lcd.o
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@ -0,0 +1,69 @@
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/*
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* arch/xtensa/platform/xtavnet/include/platform/hardware.h
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2006 Tensilica Inc.
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*/
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/*
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* This file contains the hardware configuration of the XTAVNET boards.
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*/
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#ifndef __XTENSA_XTAVNET_HARDWARE_H
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#define __XTENSA_XTAVNET_HARDWARE_H
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/* By default NO_IRQ is defined to 0 in Linux, but we use the
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interrupt 0 for UART... */
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#define NO_IRQ -1
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/* Memory configuration. */
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#define PLATFORM_DEFAULT_MEM_START 0x00000000
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#define PLATFORM_DEFAULT_MEM_SIZE 0x04000000
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/* Interrupt configuration. */
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#define PLATFORM_NR_IRQS 10
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/* Default assignment of LX60 devices to external interrupts. */
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#ifdef CONFIG_ARCH_HAS_SMP
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#define DUART16552_INTNUM XCHAL_EXTINT3_NUM
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#define OETH_IRQ XCHAL_EXTINT4_NUM
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#else
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#define DUART16552_INTNUM XCHAL_EXTINT0_NUM
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#define OETH_IRQ XCHAL_EXTINT1_NUM
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#endif
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/*
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* Device addresses and parameters.
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*/
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/* UART */
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#define DUART16552_PADDR (XCHAL_KIO_PADDR + 0x0D050020)
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/* LCD instruction and data addresses. */
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#define LCD_INSTR_ADDR ((char *)IOADDR(0x0D040000))
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#define LCD_DATA_ADDR ((char *)IOADDR(0x0D040004))
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/* Misc. */
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#define XTFPGA_FPGAREGS_VADDR IOADDR(0x0D020000)
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/* Clock frequency in Hz (read-only): */
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#define XTFPGA_CLKFRQ_VADDR (XTFPGA_FPGAREGS_VADDR + 0x04)
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/* Setting of 8 DIP switches: */
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#define DIP_SWITCHES_VADDR (XTFPGA_FPGAREGS_VADDR + 0x0C)
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/* Software reset (write 0xdead): */
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#define XTFPGA_SWRST_VADDR (XTFPGA_FPGAREGS_VADDR + 0x10)
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/* OpenCores Ethernet controller: */
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/* regs + RX/TX descriptors */
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#define OETH_REGS_PADDR (XCHAL_KIO_PADDR + 0x0D030000)
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#define OETH_REGS_SIZE 0x1000
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#define OETH_SRAMBUFF_PADDR (XCHAL_KIO_PADDR + 0x0D800000)
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/* 5*rx buffs + 5*tx buffs */
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#define OETH_SRAMBUFF_SIZE (5 * 0x600 + 5 * 0x600)
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#endif /* __XTENSA_XTAVNET_HARDWARE_H */
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@ -0,0 +1,20 @@
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/*
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* arch/xtensa/platform/xtavnet/include/platform/lcd.h
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2001, 2006 Tensilica Inc.
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*/
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#ifndef __XTENSA_XTAVNET_LCD_H
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#define __XTENSA_XTAVNET_LCD_H
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/* Display string STR at position POS on the LCD. */
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void lcd_disp_at_pos(char *str, unsigned char pos);
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/* Shift the contents of the LCD display left or right. */
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void lcd_shiftleft(void);
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void lcd_shiftright(void);
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#endif
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@ -0,0 +1,18 @@
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/*
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* arch/xtensa/platform/xtavnet/include/platform/serial.h
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2001, 2006 Tensilica Inc.
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*/
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#ifndef __ASM_XTENSA_XTAVNET_SERIAL_H
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#define __ASM_XTENSA_XTAVNET_SERIAL_H
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#include <platform/hardware.h>
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#define BASE_BAUD (*(long *)XTFPGA_CLKFRQ_VADDR / 16)
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#endif /* __ASM_XTENSA_XTAVNET_SERIAL_H */
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@ -0,0 +1,76 @@
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/*
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* Driver for the LCD display on the Tensilica LX60 Board.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2001, 2006 Tensilica Inc.
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*/
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/*
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*
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* FIXME: this code is from the examples from the LX60 user guide.
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*
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* The lcd_pause function does busy waiting, which is probably not
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* great. Maybe the code could be changed to use kernel timers, or
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* change the hardware to not need to wait.
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*/
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#include <linux/init.h>
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#include <linux/io.h>
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#include <platform/hardware.h>
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#include <platform/lcd.h>
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#include <linux/delay.h>
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#define LCD_PAUSE_ITERATIONS 4000
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#define LCD_CLEAR 0x1
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#define LCD_DISPLAY_ON 0xc
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/* 8bit and 2 lines display */
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#define LCD_DISPLAY_MODE8BIT 0x38
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#define LCD_DISPLAY_POS 0x80
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#define LCD_SHIFT_LEFT 0x18
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#define LCD_SHIFT_RIGHT 0x1c
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static int __init lcd_init(void)
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{
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*LCD_INSTR_ADDR = LCD_DISPLAY_MODE8BIT;
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mdelay(5);
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*LCD_INSTR_ADDR = LCD_DISPLAY_MODE8BIT;
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udelay(200);
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*LCD_INSTR_ADDR = LCD_DISPLAY_MODE8BIT;
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udelay(50);
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*LCD_INSTR_ADDR = LCD_DISPLAY_ON;
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udelay(50);
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*LCD_INSTR_ADDR = LCD_CLEAR;
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mdelay(10);
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lcd_disp_at_pos("XTENSA LINUX", 0);
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return 0;
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}
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void lcd_disp_at_pos(char *str, unsigned char pos)
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{
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*LCD_INSTR_ADDR = LCD_DISPLAY_POS | pos;
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udelay(100);
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while (*str != 0) {
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*LCD_DATA_ADDR = *str;
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udelay(200);
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str++;
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}
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}
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void lcd_shiftleft(void)
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{
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*LCD_INSTR_ADDR = LCD_SHIFT_LEFT;
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udelay(50);
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}
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void lcd_shiftright(void)
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{
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*LCD_INSTR_ADDR = LCD_SHIFT_RIGHT;
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udelay(50);
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}
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arch_initcall(lcd_init);
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@ -0,0 +1,269 @@
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/*
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*
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* arch/xtensa/platform/xtavnet/setup.c
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*
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* ...
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*
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* Authors: Chris Zankel <chris@zankel.net>
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* Joe Taylor <joe@tensilica.com>
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*
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* Copyright 2001 - 2006 Tensilica Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/reboot.h>
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#include <linux/kdev_t.h>
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#include <linux/types.h>
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#include <linux/major.h>
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#include <linux/console.h>
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#include <linux/delay.h>
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#include <linux/of.h>
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#include <asm/timex.h>
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#include <asm/processor.h>
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#include <asm/platform.h>
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#include <asm/bootparam.h>
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#include <platform/lcd.h>
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void platform_halt(void)
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{
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lcd_disp_at_pos(" HALT ", 0);
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local_irq_disable();
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while (1)
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cpu_relax();
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}
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void platform_power_off(void)
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{
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lcd_disp_at_pos("POWEROFF", 0);
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local_irq_disable();
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while (1)
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cpu_relax();
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}
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void platform_restart(void)
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{
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/* Flush and reset the mmu, simulate a processor reset, and
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* jump to the reset vector. */
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__asm__ __volatile__ ("movi a2, 15\n\t"
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"wsr a2, icountlevel\n\t"
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"movi a2, 0\n\t"
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"wsr a2, icount\n\t"
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"wsr a2, ibreakenable\n\t"
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"wsr a2, lcount\n\t"
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"movi a2, 0x1f\n\t"
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"wsr a2, ps\n\t"
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"isync\n\t"
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"jx %0\n\t"
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:
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: "a" (XCHAL_RESET_VECTOR_VADDR)
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: "a2"
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);
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/* control never gets here */
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}
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void __init platform_setup(char **cmdline)
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{
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}
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#ifdef CONFIG_OF
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static void __init update_clock_frequency(struct device_node *node)
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{
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struct property *newfreq;
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u32 freq;
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if (!of_property_read_u32(node, "clock-frequency", &freq) &&
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freq != 0)
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return;
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newfreq = kzalloc(sizeof(*newfreq) + sizeof(u32), GFP_KERNEL);
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if (!newfreq)
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return;
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newfreq->value = newfreq + 1;
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newfreq->length = sizeof(freq);
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newfreq->name = kstrdup("clock-frequency", GFP_KERNEL);
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if (!newfreq->name) {
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kfree(newfreq);
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return;
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}
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*(u32 *)newfreq->value = cpu_to_be32(*(u32 *)XTFPGA_CLKFRQ_VADDR);
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prom_update_property(node, newfreq);
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}
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static int __init machine_setup(void)
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{
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struct device_node *serial = NULL;
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while ((serial = of_find_compatible_node(serial, NULL, "ns16550a")))
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update_clock_frequency(serial);
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return 0;
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}
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arch_initcall(machine_setup);
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#endif
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/* early initialization */
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void __init platform_init(bp_tag_t *first)
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{
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}
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/* Heartbeat. */
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void platform_heartbeat(void)
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{
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}
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#ifdef CONFIG_XTENSA_CALIBRATE_CCOUNT
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void platform_calibrate_ccount(void)
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{
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long clk_freq = 0;
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#ifdef CONFIG_OF
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struct device_node *cpu =
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of_find_compatible_node(NULL, NULL, "xtensa,cpu");
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if (cpu) {
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u32 freq;
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update_clock_frequency(cpu);
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if (!of_property_read_u32(cpu, "clock-frequency", &freq))
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clk_freq = freq;
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}
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#endif
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if (!clk_freq)
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clk_freq = *(long *)XTFPGA_CLKFRQ_VADDR;
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ccount_per_jiffy = clk_freq / HZ;
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nsec_per_ccount = 1000000000UL / clk_freq;
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}
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#endif
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#ifndef CONFIG_OF
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#include <linux/serial_8250.h>
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#include <linux/if.h>
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#include <net/ethoc.h>
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/*----------------------------------------------------------------------------
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* Ethernet -- OpenCores Ethernet MAC (ethoc driver)
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*/
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static struct resource ethoc_res[] __initdata = {
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[0] = { /* register space */
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.start = OETH_REGS_PADDR,
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.end = OETH_REGS_PADDR + OETH_REGS_SIZE - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = { /* buffer space */
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.start = OETH_SRAMBUFF_PADDR,
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.end = OETH_SRAMBUFF_PADDR + OETH_SRAMBUFF_SIZE - 1,
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.flags = IORESOURCE_MEM,
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},
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[2] = { /* IRQ number */
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.start = OETH_IRQ,
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.end = OETH_IRQ,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct ethoc_platform_data ethoc_pdata __initdata = {
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/*
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* The MAC address for these boards is 00:50:c2:13:6f:xx.
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* The last byte (here as zero) is read from the DIP switches on the
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* board.
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*/
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.hwaddr = { 0x00, 0x50, 0xc2, 0x13, 0x6f, 0 },
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.phy_id = -1,
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};
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static struct platform_device ethoc_device __initdata = {
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.name = "ethoc",
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.id = -1,
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.num_resources = ARRAY_SIZE(ethoc_res),
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.resource = ethoc_res,
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.dev = {
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.platform_data = ðoc_pdata,
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},
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};
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/*----------------------------------------------------------------------------
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* UART
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*/
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static struct resource serial_resource __initdata = {
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.start = DUART16552_PADDR,
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.end = DUART16552_PADDR + 0x1f,
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.flags = IORESOURCE_MEM,
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};
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static struct plat_serial8250_port serial_platform_data[] __initdata = {
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[0] = {
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.mapbase = DUART16552_PADDR,
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.irq = DUART16552_INTNUM,
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.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
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UPF_IOREMAP,
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.iotype = UPIO_MEM32,
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.regshift = 2,
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.uartclk = 0, /* set in xtavnet_init() */
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},
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{ },
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};
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static struct platform_device xtavnet_uart __initdata = {
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.name = "serial8250",
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.id = PLAT8250_DEV_PLATFORM,
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.dev = {
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.platform_data = serial_platform_data,
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},
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.num_resources = 1,
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.resource = &serial_resource,
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};
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/* platform devices */
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static struct platform_device *platform_devices[] __initdata = {
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ðoc_device,
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&xtavnet_uart,
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};
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static int __init xtavnet_init(void)
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{
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/* Ethernet MAC address. */
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ethoc_pdata.hwaddr[5] = *(u32 *)DIP_SWITCHES_VADDR;
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|
||||
/* Clock rate varies among FPGA bitstreams; board specific FPGA register
|
||||
* reports the actual clock rate.
|
||||
*/
|
||||
serial_platform_data[0].uartclk = *(long *)XTFPGA_CLKFRQ_VADDR;
|
||||
|
||||
|
||||
/* register platform devices */
|
||||
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
|
||||
|
||||
/* ETHOC driver is a bit quiet; at least display Ethernet MAC, so user
|
||||
* knows whether they set it correctly on the DIP switches.
|
||||
*/
|
||||
pr_info("XTFPGA: Ethernet MAC %pM\n", ethoc_pdata.hwaddr);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Register to be done during do_initcalls().
|
||||
*/
|
||||
arch_initcall(xtavnet_init);
|
||||
|
||||
#endif /* CONFIG_OF */
|
||||
Loading…
Reference in New Issue