mirror of https://gitee.com/openkylin/linux.git
ASoC: adau: Factor out shared PLL configuration code
Multiple devices from the ADAU family share the same PLL structure and configuration register layout. Introduce a new helper module that can be used to calculated the PLL configuration registers based on a specified input frequency and the desired output frequency of the PLL. The ADAU1761/ADAU1781 and ADAU1373 drivers are updated to make use of this new helper module. But future drivers for additional devices from the ADAU family are also expected to make use of it. In anticipation of sharing more infrastructure code between different devices from the ADAU family the new module is called adau-utils. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -269,8 +269,12 @@ config SND_SOC_AD1980
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config SND_SOC_AD73311
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tristate
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config SND_SOC_ADAU_UTILS
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tristate
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config SND_SOC_ADAU1373
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tristate
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select SND_SOC_ADAU_UTILS
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config SND_SOC_ADAU1701
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tristate "Analog Devices ADAU1701 CODEC"
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@ -280,6 +284,7 @@ config SND_SOC_ADAU1701
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config SND_SOC_ADAU17X1
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tristate
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select SND_SOC_SIGMADSP_REGMAP
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select SND_SOC_ADAU_UTILS
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config SND_SOC_ADAU1761
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tristate
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@ -7,6 +7,7 @@ snd-soc-ad193x-spi-objs := ad193x-spi.o
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snd-soc-ad193x-i2c-objs := ad193x-i2c.o
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snd-soc-ad1980-objs := ad1980.o
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snd-soc-ad73311-objs := ad73311.o
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snd-soc-adau-utils-objs := adau-utils.o
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snd-soc-adau1373-objs := adau1373.o
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snd-soc-adau1701-objs := adau1701.o
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snd-soc-adau17x1-objs := adau17x1.o
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@ -220,6 +221,7 @@ obj-$(CONFIG_SND_SOC_AD193X_SPI) += snd-soc-ad193x-spi.o
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obj-$(CONFIG_SND_SOC_AD193X_I2C) += snd-soc-ad193x-i2c.o
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obj-$(CONFIG_SND_SOC_AD1980) += snd-soc-ad1980.o
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obj-$(CONFIG_SND_SOC_AD73311) += snd-soc-ad73311.o
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obj-$(CONFIG_SND_SOC_ADAU_UTILS) += snd-soc-adau-utils.o
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obj-$(CONFIG_SND_SOC_ADAU1373) += snd-soc-adau1373.o
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obj-$(CONFIG_SND_SOC_ADAU1701) += snd-soc-adau1701.o
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obj-$(CONFIG_SND_SOC_ADAU17X1) += snd-soc-adau17x1.o
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@ -0,0 +1,61 @@
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/*
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* Shared helper functions for devices from the ADAU family
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*
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* Copyright 2011-2016 Analog Devices Inc.
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* Author: Lars-Peter Clausen <lars@metafoo.de>
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <linux/gcd.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include "adau-utils.h"
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int adau_calc_pll_cfg(unsigned int freq_in, unsigned int freq_out,
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uint8_t regs[5])
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{
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unsigned int r, n, m, i, j;
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unsigned int div;
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if (!freq_out) {
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r = 0;
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n = 0;
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m = 0;
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div = 0;
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} else {
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if (freq_out % freq_in != 0) {
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div = DIV_ROUND_UP(freq_in, 13500000);
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freq_in /= div;
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r = freq_out / freq_in;
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i = freq_out % freq_in;
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j = gcd(i, freq_in);
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n = i / j;
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m = freq_in / j;
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div--;
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} else {
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r = freq_out / freq_in;
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n = 0;
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m = 0;
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div = 0;
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}
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if (n > 0xffff || m > 0xffff || div > 3 || r > 8 || r < 2)
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return -EINVAL;
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}
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regs[0] = m >> 8;
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regs[1] = m & 0xff;
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regs[2] = n >> 8;
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regs[3] = n & 0xff;
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regs[4] = (r << 3) | (div << 1);
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if (m != 0)
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regs[4] |= 1; /* Fractional mode */
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return 0;
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}
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EXPORT_SYMBOL_GPL(adau_calc_pll_cfg);
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MODULE_DESCRIPTION("ASoC ADAU audio CODECs shared helper functions");
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MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
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MODULE_LICENSE("GPL v2");
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@ -0,0 +1,7 @@
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#ifndef SOUND_SOC_CODECS_ADAU_PLL_H
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#define SOUND_SOC_CODECS_ADAU_PLL_H
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int adau_calc_pll_cfg(unsigned int freq_in, unsigned int freq_out,
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uint8_t regs[5]);
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#endif
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@ -23,6 +23,7 @@
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#include <sound/adau1373.h>
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#include "adau1373.h"
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#include "adau-utils.h"
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struct adau1373_dai {
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unsigned int clk_src;
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@ -1254,7 +1255,8 @@ static int adau1373_set_pll(struct snd_soc_codec *codec, int pll_id,
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{
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struct adau1373 *adau1373 = snd_soc_codec_get_drvdata(codec);
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unsigned int dpll_div = 0;
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unsigned int x, r, n, m, i, j, mode;
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uint8_t pll_regs[5];
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int ret;
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switch (pll_id) {
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case ADAU1373_PLL1:
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@ -1295,27 +1297,8 @@ static int adau1373_set_pll(struct snd_soc_codec *codec, int pll_id,
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dpll_div++;
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}
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if (freq_out % freq_in != 0) {
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/* fout = fin * (r + (n/m)) / x */
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x = DIV_ROUND_UP(freq_in, 13500000);
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freq_in /= x;
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r = freq_out / freq_in;
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i = freq_out % freq_in;
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j = gcd(i, freq_in);
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n = i / j;
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m = freq_in / j;
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x--;
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mode = 1;
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} else {
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/* fout = fin / r */
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r = freq_out / freq_in;
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n = 0;
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m = 0;
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x = 0;
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mode = 0;
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}
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if (r < 2 || r > 8 || x > 3 || m > 0xffff || n > 0xffff)
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ret = adau_calc_pll_cfg(freq_in, freq_out, pll_regs);
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if (ret)
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return -EINVAL;
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if (dpll_div) {
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@ -1330,12 +1313,11 @@ static int adau1373_set_pll(struct snd_soc_codec *codec, int pll_id,
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regmap_write(adau1373->regmap, ADAU1373_DPLL_CTRL(pll_id),
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(source << 4) | dpll_div);
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regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL1(pll_id), (m >> 8) & 0xff);
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regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL2(pll_id), m & 0xff);
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regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL3(pll_id), (n >> 8) & 0xff);
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regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL4(pll_id), n & 0xff);
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regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL5(pll_id),
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(r << 3) | (x << 1) | mode);
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regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL1(pll_id), pll_regs[0]);
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regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL2(pll_id), pll_regs[1]);
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regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL3(pll_id), pll_regs[2]);
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regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL4(pll_id), pll_regs[3]);
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regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL5(pll_id), pll_regs[4]);
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/* Set sysclk to pll_rate / 4 */
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regmap_update_bits(adau1373->regmap, ADAU1373_CLK_SRC_DIV(pll_id), 0x3f, 0x09);
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@ -23,6 +23,7 @@
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#include "sigmadsp.h"
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#include "adau17x1.h"
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#include "adau-utils.h"
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static const char * const adau17x1_capture_mixer_boost_text[] = {
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"Normal operation", "Boost Level 1", "Boost Level 2", "Boost Level 3",
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@ -391,45 +392,14 @@ static int adau17x1_set_dai_pll(struct snd_soc_dai *dai, int pll_id,
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{
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struct snd_soc_codec *codec = dai->codec;
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struct adau *adau = snd_soc_codec_get_drvdata(codec);
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unsigned int r, n, m, i, j;
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unsigned int div;
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int ret;
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if (freq_in < 8000000 || freq_in > 27000000)
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return -EINVAL;
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if (!freq_out) {
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r = 0;
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n = 0;
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m = 0;
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div = 0;
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} else {
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if (freq_out % freq_in != 0) {
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div = DIV_ROUND_UP(freq_in, 13500000);
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freq_in /= div;
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r = freq_out / freq_in;
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i = freq_out % freq_in;
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j = gcd(i, freq_in);
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n = i / j;
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m = freq_in / j;
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div--;
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} else {
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r = freq_out / freq_in;
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n = 0;
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m = 0;
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div = 0;
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}
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if (n > 0xffff || m > 0xffff || div > 3 || r > 8 || r < 2)
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return -EINVAL;
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}
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adau->pll_regs[0] = m >> 8;
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adau->pll_regs[1] = m & 0xff;
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adau->pll_regs[2] = n >> 8;
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adau->pll_regs[3] = n & 0xff;
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adau->pll_regs[4] = (r << 3) | (div << 1);
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if (m != 0)
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adau->pll_regs[4] |= 1; /* Fractional mode */
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ret = adau_calc_pll_cfg(freq_in, freq_out, adau->pll_regs);
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if (ret < 0)
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return ret;
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/* The PLL register is 6 bytes long and can only be written at once. */
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ret = regmap_raw_write(adau->regmap, ADAU17X1_PLL_CONTROL,
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