mirror of https://gitee.com/openkylin/linux.git
drm/i915: Pass dev_priv to intel_wait_for_vblank()
Unify our approach to things by passing around dev_priv instead of dev. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1477946245-14134-8-git-send-email-ville.syrjala@linux.intel.com Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
parent
e2af48c66b
commit
0f0f74bc83
|
@ -4211,7 +4211,7 @@ static int pipe_crc_set_source(struct drm_i915_private *dev_priv,
|
|||
|
||||
drm_modeset_lock(&crtc->base.mutex, NULL);
|
||||
if (crtc->base.state->active)
|
||||
intel_wait_for_vblank(dev, pipe);
|
||||
intel_wait_for_vblank(dev_priv, pipe);
|
||||
drm_modeset_unlock(&crtc->base.mutex);
|
||||
|
||||
spin_lock_irq(&pipe_crc->lock);
|
||||
|
|
|
@ -573,7 +573,7 @@ intel_crt_load_detect(struct intel_crt *crt, uint32_t pipe)
|
|||
POSTING_READ(pipeconf_reg);
|
||||
/* Wait for next Vblank to substitue
|
||||
* border color for Color info */
|
||||
intel_wait_for_vblank(dev, pipe);
|
||||
intel_wait_for_vblank(dev_priv, pipe);
|
||||
st00 = I915_READ8(_VGA_MSR_WRITE);
|
||||
status = ((st00 & (1 << 4)) != 0) ?
|
||||
connector_status_connected :
|
||||
|
|
|
@ -4249,6 +4249,7 @@ static void ironlake_fdi_disable(struct drm_crtc *crtc)
|
|||
|
||||
bool intel_has_pending_fb_unpin(struct drm_device *dev)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(dev);
|
||||
struct intel_crtc *crtc;
|
||||
|
||||
/* Note that we don't need to be called with mode_config.lock here
|
||||
|
@ -4263,7 +4264,7 @@ bool intel_has_pending_fb_unpin(struct drm_device *dev)
|
|||
continue;
|
||||
|
||||
if (crtc->flip_work)
|
||||
intel_wait_for_vblank(dev, crtc->pipe);
|
||||
intel_wait_for_vblank(dev_priv, crtc->pipe);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
@ -4940,7 +4941,7 @@ void hsw_disable_ips(struct intel_crtc *crtc)
|
|||
}
|
||||
|
||||
/* We need to wait for a vblank before we can disable the plane. */
|
||||
intel_wait_for_vblank(dev, crtc->pipe);
|
||||
intel_wait_for_vblank(dev_priv, crtc->pipe);
|
||||
}
|
||||
|
||||
static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
|
||||
|
@ -5052,7 +5053,7 @@ intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
|
|||
if (HAS_GMCH_DISPLAY(dev_priv)) {
|
||||
intel_set_memory_cxsr(dev_priv, false);
|
||||
dev_priv->wm.vlv.cxsr = false;
|
||||
intel_wait_for_vblank(dev, pipe);
|
||||
intel_wait_for_vblank(dev_priv, pipe);
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -5129,7 +5130,7 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
|
|||
if (old_crtc_state->base.active) {
|
||||
intel_set_memory_cxsr(dev_priv, false);
|
||||
dev_priv->wm.vlv.cxsr = false;
|
||||
intel_wait_for_vblank(dev, crtc->pipe);
|
||||
intel_wait_for_vblank(dev_priv, crtc->pipe);
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -5142,7 +5143,7 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
|
|||
*/
|
||||
if (pipe_config->disable_lp_wm) {
|
||||
ilk_disable_lp_wm(dev);
|
||||
intel_wait_for_vblank(dev, crtc->pipe);
|
||||
intel_wait_for_vblank(dev_priv, crtc->pipe);
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -5397,7 +5398,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
|
|||
|
||||
/* Must wait for vblank to avoid spurious PCH FIFO underruns */
|
||||
if (intel_crtc->config->has_pch_encoder)
|
||||
intel_wait_for_vblank(dev, pipe);
|
||||
intel_wait_for_vblank(dev_priv, pipe);
|
||||
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
|
||||
intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
|
||||
}
|
||||
|
@ -5507,8 +5508,8 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
|
|||
intel_encoders_enable(crtc, pipe_config, old_state);
|
||||
|
||||
if (intel_crtc->config->has_pch_encoder) {
|
||||
intel_wait_for_vblank(dev, pipe);
|
||||
intel_wait_for_vblank(dev, pipe);
|
||||
intel_wait_for_vblank(dev_priv, pipe);
|
||||
intel_wait_for_vblank(dev_priv, pipe);
|
||||
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
|
||||
intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
|
||||
true);
|
||||
|
@ -5518,8 +5519,8 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
|
|||
* to change the workaround. */
|
||||
hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
|
||||
if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
|
||||
intel_wait_for_vblank(dev, hsw_workaround_pipe);
|
||||
intel_wait_for_vblank(dev, hsw_workaround_pipe);
|
||||
intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
|
||||
intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -6833,7 +6834,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
|
|||
* wait for planes to fully turn off before disabling the pipe.
|
||||
*/
|
||||
if (IS_GEN2(dev_priv))
|
||||
intel_wait_for_vblank(dev, pipe);
|
||||
intel_wait_for_vblank(dev_priv, pipe);
|
||||
|
||||
intel_encoders_disable(crtc, old_crtc_state, old_state);
|
||||
|
||||
|
@ -11129,6 +11130,7 @@ bool intel_get_load_detect_pipe(struct drm_connector *connector,
|
|||
struct drm_encoder *encoder = &intel_encoder->base;
|
||||
struct drm_crtc *crtc = NULL;
|
||||
struct drm_device *dev = encoder->dev;
|
||||
struct drm_i915_private *dev_priv = to_i915(dev);
|
||||
struct drm_framebuffer *fb;
|
||||
struct drm_mode_config *config = &dev->mode_config;
|
||||
struct drm_atomic_state *state = NULL, *restore_state = NULL;
|
||||
|
@ -11281,7 +11283,7 @@ bool intel_get_load_detect_pipe(struct drm_connector *connector,
|
|||
old->restore_state = restore_state;
|
||||
|
||||
/* let the connector get through one full cycle before testing */
|
||||
intel_wait_for_vblank(dev, intel_crtc->pipe);
|
||||
intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
|
||||
return true;
|
||||
|
||||
fail:
|
||||
|
@ -14277,7 +14279,7 @@ static void intel_update_crtcs(struct drm_atomic_state *state,
|
|||
static void skl_update_crtcs(struct drm_atomic_state *state,
|
||||
unsigned int *crtc_vblank_mask)
|
||||
{
|
||||
struct drm_device *dev = state->dev;
|
||||
struct drm_i915_private *dev_priv = to_i915(state->dev);
|
||||
struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
|
||||
struct drm_crtc *crtc;
|
||||
struct intel_crtc *intel_crtc;
|
||||
|
@ -14328,7 +14330,7 @@ static void skl_update_crtcs(struct drm_atomic_state *state,
|
|||
crtc_vblank_mask);
|
||||
|
||||
if (vbl_wait)
|
||||
intel_wait_for_vblank(dev, pipe);
|
||||
intel_wait_for_vblank(dev_priv, pipe);
|
||||
|
||||
progress = true;
|
||||
}
|
||||
|
|
|
@ -2364,7 +2364,7 @@ static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
|
|||
* 2. Program DP PLL enable
|
||||
*/
|
||||
if (IS_GEN5(dev_priv))
|
||||
intel_wait_for_vblank_if_active(&dev_priv->drm, !crtc->pipe);
|
||||
intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
|
||||
|
||||
intel_dp->DP |= DP_PLL_ENABLE;
|
||||
|
||||
|
@ -3487,7 +3487,7 @@ intel_dp_link_down(struct intel_dp *intel_dp)
|
|||
I915_WRITE(intel_dp->output_reg, DP);
|
||||
POSTING_READ(intel_dp->output_reg);
|
||||
|
||||
intel_wait_for_vblank_if_active(&dev_priv->drm, PIPE_A);
|
||||
intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
|
||||
intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
|
||||
intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
|
||||
}
|
||||
|
@ -3667,7 +3667,7 @@ intel_dp_configure_mst(struct intel_dp *intel_dp)
|
|||
static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
|
||||
{
|
||||
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
|
||||
struct drm_device *dev = dig_port->base.base.dev;
|
||||
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
|
||||
struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
|
||||
u8 buf;
|
||||
int ret = 0;
|
||||
|
@ -3688,7 +3688,7 @@ static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
|
|||
}
|
||||
|
||||
do {
|
||||
intel_wait_for_vblank(dev, intel_crtc->pipe);
|
||||
intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
|
||||
|
||||
if (drm_dp_dpcd_readb(&intel_dp->aux,
|
||||
DP_TEST_SINK_MISC, &buf) < 0) {
|
||||
|
@ -3711,7 +3711,7 @@ static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
|
|||
static int intel_dp_sink_crc_start(struct intel_dp *intel_dp)
|
||||
{
|
||||
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
|
||||
struct drm_device *dev = dig_port->base.base.dev;
|
||||
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
|
||||
struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
|
||||
u8 buf;
|
||||
int ret;
|
||||
|
@ -3739,14 +3739,14 @@ static int intel_dp_sink_crc_start(struct intel_dp *intel_dp)
|
|||
return -EIO;
|
||||
}
|
||||
|
||||
intel_wait_for_vblank(dev, intel_crtc->pipe);
|
||||
intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
|
||||
{
|
||||
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
|
||||
struct drm_device *dev = dig_port->base.base.dev;
|
||||
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
|
||||
struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
|
||||
u8 buf;
|
||||
int count, ret;
|
||||
|
@ -3757,7 +3757,7 @@ int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
|
|||
return ret;
|
||||
|
||||
do {
|
||||
intel_wait_for_vblank(dev, intel_crtc->pipe);
|
||||
intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
|
||||
|
||||
if (drm_dp_dpcd_readb(&intel_dp->aux,
|
||||
DP_TEST_SINK_MISC, &buf) < 0) {
|
||||
|
@ -3990,7 +3990,7 @@ intel_dp_retrain_link(struct intel_dp *intel_dp)
|
|||
intel_dp_stop_link_train(intel_dp);
|
||||
|
||||
/* Keep underrun reporting disabled until things are stable */
|
||||
intel_wait_for_vblank(&dev_priv->drm, crtc->pipe);
|
||||
intel_wait_for_vblank(dev_priv, crtc->pipe);
|
||||
|
||||
intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
|
||||
if (crtc->config->has_pch_encoder)
|
||||
|
|
|
@ -1244,17 +1244,17 @@ intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
|
|||
(1 << INTEL_OUTPUT_EDP));
|
||||
}
|
||||
static inline void
|
||||
intel_wait_for_vblank(struct drm_device *dev, int pipe)
|
||||
intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
|
||||
{
|
||||
drm_wait_one_vblank(dev, pipe);
|
||||
drm_wait_one_vblank(&dev_priv->drm, pipe);
|
||||
}
|
||||
static inline void
|
||||
intel_wait_for_vblank_if_active(struct drm_device *dev, int pipe)
|
||||
intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
|
||||
{
|
||||
const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev, pipe);
|
||||
const struct intel_crtc *crtc = intel_get_crtc_for_pipe(&dev_priv->drm, pipe);
|
||||
|
||||
if (crtc->active)
|
||||
intel_wait_for_vblank(dev, pipe);
|
||||
intel_wait_for_vblank(dev_priv, pipe);
|
||||
}
|
||||
|
||||
u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
|
||||
|
|
|
@ -1164,7 +1164,7 @@ static void intel_disable_hdmi(struct intel_encoder *encoder,
|
|||
I915_WRITE(intel_hdmi->hdmi_reg, temp);
|
||||
POSTING_READ(intel_hdmi->hdmi_reg);
|
||||
|
||||
intel_wait_for_vblank_if_active(&dev_priv->drm, PIPE_A);
|
||||
intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
|
||||
intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
|
||||
intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
|
||||
}
|
||||
|
|
|
@ -1472,7 +1472,7 @@ static void intel_disable_sdvo(struct intel_encoder *encoder,
|
|||
temp &= ~SDVO_ENABLE;
|
||||
intel_sdvo_write_sdvox(intel_sdvo, temp);
|
||||
|
||||
intel_wait_for_vblank_if_active(&dev_priv->drm, PIPE_A);
|
||||
intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
|
||||
intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
|
||||
intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
|
||||
}
|
||||
|
@ -1509,7 +1509,7 @@ static void intel_enable_sdvo(struct intel_encoder *encoder,
|
|||
intel_sdvo_write_sdvox(intel_sdvo, temp);
|
||||
|
||||
for (i = 0; i < 2; i++)
|
||||
intel_wait_for_vblank(dev, intel_crtc->pipe);
|
||||
intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
|
||||
|
||||
success = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
|
||||
/* Warn if the device reported failure to sync.
|
||||
|
|
|
@ -856,7 +856,7 @@ intel_enable_tv(struct intel_encoder *encoder,
|
|||
struct drm_i915_private *dev_priv = to_i915(dev);
|
||||
|
||||
/* Prevents vblank waits from timing out in intel_tv_detect_type() */
|
||||
intel_wait_for_vblank(encoder->base.dev,
|
||||
intel_wait_for_vblank(dev_priv,
|
||||
to_intel_crtc(encoder->base.crtc)->pipe);
|
||||
|
||||
I915_WRITE(TV_CTL, I915_READ(TV_CTL) | TV_ENC_ENABLE);
|
||||
|
@ -1238,7 +1238,7 @@ intel_tv_detect_type(struct intel_tv *intel_tv,
|
|||
I915_WRITE(TV_DAC, tv_dac);
|
||||
POSTING_READ(TV_DAC);
|
||||
|
||||
intel_wait_for_vblank(dev, intel_crtc->pipe);
|
||||
intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
|
||||
|
||||
type = -1;
|
||||
tv_dac = I915_READ(TV_DAC);
|
||||
|
@ -1268,7 +1268,7 @@ intel_tv_detect_type(struct intel_tv *intel_tv,
|
|||
POSTING_READ(TV_CTL);
|
||||
|
||||
/* For unknown reasons the hw barfs if we don't do this vblank wait. */
|
||||
intel_wait_for_vblank(dev, intel_crtc->pipe);
|
||||
intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
|
||||
|
||||
/* Restore interrupt config */
|
||||
if (connector->polled & DRM_CONNECTOR_POLL_HPD) {
|
||||
|
|
Loading…
Reference in New Issue