mirror of https://gitee.com/openkylin/linux.git
mfd: stmpe: Add STMPE_IDX_SYS_CTRL/2 enum
As STMPE1801/1601/24xx has a SYS_CTRL register and STMPE1601/2403 has even a SYS_CTRL2 register, add STMPE_IDX_SYS_CTRL/2 and update driver code accordingly This update prepares the ground for not yet supported STMPE1600 which share similar REG_SYS_CTRL register. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>
This commit is contained in:
parent
29b4817d40
commit
0f4be8cf63
|
@ -469,6 +469,8 @@ static const struct mfd_cell stmpe_ts_cell = {
|
|||
|
||||
static const u8 stmpe811_regs[] = {
|
||||
[STMPE_IDX_CHIP_ID] = STMPE811_REG_CHIP_ID,
|
||||
[STMPE_IDX_SYS_CTRL] = STMPE811_REG_SYS_CTRL,
|
||||
[STMPE_IDX_SYS_CTRL2] = STMPE811_REG_SYS_CTRL2,
|
||||
[STMPE_IDX_ICR_LSB] = STMPE811_REG_INT_CTRL,
|
||||
[STMPE_IDX_IER_LSB] = STMPE811_REG_INT_EN,
|
||||
[STMPE_IDX_ISR_MSB] = STMPE811_REG_INT_STA,
|
||||
|
@ -511,7 +513,7 @@ static int stmpe811_enable(struct stmpe *stmpe, unsigned int blocks,
|
|||
if (blocks & STMPE_BLOCK_TOUCHSCREEN)
|
||||
mask |= STMPE811_SYS_CTRL2_TSC_OFF;
|
||||
|
||||
return __stmpe_set_bits(stmpe, STMPE811_REG_SYS_CTRL2, mask,
|
||||
return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL2], mask,
|
||||
enable ? 0 : mask);
|
||||
}
|
||||
|
||||
|
@ -556,6 +558,8 @@ static struct stmpe_variant_info stmpe610 = {
|
|||
|
||||
static const u8 stmpe1601_regs[] = {
|
||||
[STMPE_IDX_CHIP_ID] = STMPE1601_REG_CHIP_ID,
|
||||
[STMPE_IDX_SYS_CTRL] = STMPE1601_REG_SYS_CTRL,
|
||||
[STMPE_IDX_SYS_CTRL2] = STMPE1601_REG_SYS_CTRL2,
|
||||
[STMPE_IDX_ICR_LSB] = STMPE1601_REG_ICR_LSB,
|
||||
[STMPE_IDX_IER_LSB] = STMPE1601_REG_IER_LSB,
|
||||
[STMPE_IDX_ISR_MSB] = STMPE1601_REG_ISR_MSB,
|
||||
|
@ -640,13 +644,13 @@ static int stmpe1601_autosleep(struct stmpe *stmpe,
|
|||
return timeout;
|
||||
}
|
||||
|
||||
ret = __stmpe_set_bits(stmpe, STMPE1601_REG_SYS_CTRL2,
|
||||
ret = __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL2],
|
||||
STMPE1601_AUTOSLEEP_TIMEOUT_MASK,
|
||||
timeout);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
return __stmpe_set_bits(stmpe, STMPE1601_REG_SYS_CTRL2,
|
||||
return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL2],
|
||||
STPME1601_AUTOSLEEP_ENABLE,
|
||||
STPME1601_AUTOSLEEP_ENABLE);
|
||||
}
|
||||
|
@ -671,7 +675,7 @@ static int stmpe1601_enable(struct stmpe *stmpe, unsigned int blocks,
|
|||
else
|
||||
mask &= ~STMPE1601_SYS_CTRL_ENABLE_SPWM;
|
||||
|
||||
return __stmpe_set_bits(stmpe, STMPE1601_REG_SYS_CTRL, mask,
|
||||
return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL], mask,
|
||||
enable ? mask : 0);
|
||||
}
|
||||
|
||||
|
@ -710,6 +714,7 @@ static struct stmpe_variant_info stmpe1601 = {
|
|||
*/
|
||||
static const u8 stmpe1801_regs[] = {
|
||||
[STMPE_IDX_CHIP_ID] = STMPE1801_REG_CHIP_ID,
|
||||
[STMPE_IDX_SYS_CTRL] = STMPE1801_REG_SYS_CTRL,
|
||||
[STMPE_IDX_ICR_LSB] = STMPE1801_REG_INT_CTRL_LOW,
|
||||
[STMPE_IDX_IER_LSB] = STMPE1801_REG_INT_EN_MASK_LOW,
|
||||
[STMPE_IDX_ISR_LSB] = STMPE1801_REG_INT_STA_LOW,
|
||||
|
@ -756,14 +761,14 @@ static int stmpe1801_reset(struct stmpe *stmpe)
|
|||
unsigned long timeout;
|
||||
int ret = 0;
|
||||
|
||||
ret = __stmpe_set_bits(stmpe, STMPE1801_REG_SYS_CTRL,
|
||||
ret = __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL],
|
||||
STMPE1801_MSK_SYS_CTRL_RESET, STMPE1801_MSK_SYS_CTRL_RESET);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
timeout = jiffies + msecs_to_jiffies(100);
|
||||
while (time_before(jiffies, timeout)) {
|
||||
ret = __stmpe_reg_read(stmpe, STMPE1801_REG_SYS_CTRL);
|
||||
ret = __stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL]);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
if (!(ret & STMPE1801_MSK_SYS_CTRL_RESET))
|
||||
|
@ -794,6 +799,8 @@ static struct stmpe_variant_info stmpe1801 = {
|
|||
|
||||
static const u8 stmpe24xx_regs[] = {
|
||||
[STMPE_IDX_CHIP_ID] = STMPE24XX_REG_CHIP_ID,
|
||||
[STMPE_IDX_SYS_CTRL] = STMPE24XX_REG_SYS_CTRL,
|
||||
[STMPE_IDX_SYS_CTRL2] = STMPE24XX_REG_SYS_CTRL2,
|
||||
[STMPE_IDX_ICR_LSB] = STMPE24XX_REG_ICR_LSB,
|
||||
[STMPE_IDX_IER_LSB] = STMPE24XX_REG_IER_LSB,
|
||||
[STMPE_IDX_ISR_MSB] = STMPE24XX_REG_ISR_MSB,
|
||||
|
@ -840,7 +847,7 @@ static int stmpe24xx_enable(struct stmpe *stmpe, unsigned int blocks,
|
|||
if (blocks & STMPE_BLOCK_KEYPAD)
|
||||
mask |= STMPE24XX_SYS_CTRL_ENABLE_KPC;
|
||||
|
||||
return __stmpe_set_bits(stmpe, STMPE24XX_REG_SYS_CTRL, mask,
|
||||
return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL], mask,
|
||||
enable ? mask : 0);
|
||||
}
|
||||
|
||||
|
|
|
@ -138,6 +138,7 @@ int stmpe_remove(struct stmpe *stmpe);
|
|||
#define STMPE811_NR_INTERNAL_IRQS 8
|
||||
|
||||
#define STMPE811_REG_CHIP_ID 0x00
|
||||
#define STMPE811_REG_SYS_CTRL 0x03
|
||||
#define STMPE811_REG_SYS_CTRL2 0x04
|
||||
#define STMPE811_REG_SPI_CFG 0x08
|
||||
#define STMPE811_REG_INT_CTRL 0x09
|
||||
|
@ -264,6 +265,7 @@ int stmpe_remove(struct stmpe *stmpe);
|
|||
#define STMPE24XX_NR_INTERNAL_IRQS 9
|
||||
|
||||
#define STMPE24XX_REG_SYS_CTRL 0x02
|
||||
#define STMPE24XX_REG_SYS_CTRL2 0x03
|
||||
#define STMPE24XX_REG_ICR_LSB 0x11
|
||||
#define STMPE24XX_REG_IER_LSB 0x13
|
||||
#define STMPE24XX_REG_ISR_MSB 0x14
|
||||
|
|
|
@ -39,6 +39,8 @@ enum stmpe_partnum {
|
|||
*/
|
||||
enum {
|
||||
STMPE_IDX_CHIP_ID,
|
||||
STMPE_IDX_SYS_CTRL,
|
||||
STMPE_IDX_SYS_CTRL2,
|
||||
STMPE_IDX_ICR_LSB,
|
||||
STMPE_IDX_IER_LSB,
|
||||
STMPE_IDX_ISR_LSB,
|
||||
|
|
Loading…
Reference in New Issue