mirror of https://gitee.com/openkylin/linux.git
bnx2x: Add support for BCM84834
Add support for the 10G-baseT PHY - BCM84834, which is the quad-port version of the dual-port BCM84833. Signed-off-by: Yaniv Rosner <yanivr@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Yaniv Rosner
David S. Miller
parent
5a1fbf4046
commit
0f6bb03dd0
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@ -695,6 +695,7 @@ struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */
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#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54618SE 0x00000e00
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#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8722 0x00000f00
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#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54616 0x00001000
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#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84834 0x00001100
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#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE 0x0000fd00
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#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN 0x0000ff00
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@ -751,6 +752,7 @@ struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */
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#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE 0x00000e00
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#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722 0x00000f00
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#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616 0x00001000
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#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834 0x00001100
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#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT_WC 0x0000fc00
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#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00
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#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00
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@ -9519,7 +9519,8 @@ static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy,
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{
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u16 val, fw_ver1, fw_ver2, cnt;
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if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
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if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
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(phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
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bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1);
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bnx2x_save_spirom_version(bp, port, fw_ver1 & 0xfff,
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phy->ver_addr);
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@ -9619,7 +9620,8 @@ static void bnx2x_848xx_set_led(struct bnx2x *bp,
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MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH,
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MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ);
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if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
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if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
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(phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834))
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offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1;
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else
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offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1;
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@ -9643,7 +9645,8 @@ static void bnx2x_848xx_specific_func(struct bnx2x_phy *phy,
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struct bnx2x *bp = params->bp;
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switch (action) {
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case PHY_INIT:
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if (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
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if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
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(phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
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/* Save spirom version */
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bnx2x_save_848xx_spirom_version(phy, bp, params->port);
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}
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@ -9763,10 +9766,11 @@ static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
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if (phy->req_duplex == DUPLEX_FULL)
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autoneg_val |= (1<<8);
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/* Always write this if this is not 84833.
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* For 84833, write it only when it's a forced speed.
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/* Always write this if this is not 84833/4.
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* For 84833/4, write it only when it's a forced speed.
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*/
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if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
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if (((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
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(phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) ||
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((autoneg_val & (1<<12)) == 0))
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bnx2x_cl45_write(bp, phy,
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MDIO_AN_DEVAD,
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@ -10049,7 +10053,8 @@ static int bnx2x_848x3_config_init(struct bnx2x_phy *phy,
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/* Wait for GPHY to come out of reset */
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msleep(50);
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if (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
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if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
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(phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
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/* BCM84823 requires that XGXS links up first @ 10G for normal
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* behavior.
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*/
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@ -10105,7 +10110,8 @@ static int bnx2x_848x3_config_init(struct bnx2x_phy *phy,
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DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n",
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params->multi_phy_config, val);
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if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
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if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
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(phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
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bnx2x_84833_pair_swap_cfg(phy, params, vars);
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/* Keep AutogrEEEn disabled. */
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@ -10169,7 +10175,8 @@ static int bnx2x_848x3_config_init(struct bnx2x_phy *phy,
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vars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK;
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}
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if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
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if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
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(phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
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/* Bring PHY out of super isolate mode as the final step. */
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bnx2x_cl45_read(bp, phy,
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MDIO_CTL_DEVAD,
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@ -11607,6 +11614,40 @@ static struct bnx2x_phy phy_84833 = {
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.phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
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};
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static const struct bnx2x_phy phy_84834 = {
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.type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834,
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.addr = 0xff,
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.def_md_devad = 0,
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.flags = FLAGS_FAN_FAILURE_DET_REQ |
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FLAGS_REARM_LATCH_SIGNAL,
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.rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
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.tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
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.mdio_ctrl = 0,
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.supported = (SUPPORTED_100baseT_Half |
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SUPPORTED_100baseT_Full |
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SUPPORTED_1000baseT_Full |
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SUPPORTED_10000baseT_Full |
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SUPPORTED_TP |
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SUPPORTED_Autoneg |
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SUPPORTED_Pause |
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SUPPORTED_Asym_Pause),
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.media_type = ETH_PHY_BASE_T,
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.ver_addr = 0,
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.req_flow_ctrl = 0,
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.req_line_speed = 0,
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.speed_cap_mask = 0,
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.req_duplex = 0,
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.rsrv = 0,
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.config_init = (config_init_t)bnx2x_848x3_config_init,
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.read_status = (read_status_t)bnx2x_848xx_read_status,
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.link_reset = (link_reset_t)bnx2x_848x3_link_reset,
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.config_loopback = (config_loopback_t)NULL,
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.format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
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.hw_reset = (hw_reset_t)bnx2x_84833_hw_reset_phy,
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.set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
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.phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
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};
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static struct bnx2x_phy phy_54618se = {
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.type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE,
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.addr = 0xff,
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@ -11888,6 +11929,9 @@ static int bnx2x_populate_ext_phy(struct bnx2x *bp,
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case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
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*phy = phy_84833;
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break;
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case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834:
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*phy = phy_84834;
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break;
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case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616:
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case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE:
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*phy = phy_54618se;
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@ -11944,9 +11988,10 @@ static int bnx2x_populate_ext_phy(struct bnx2x *bp,
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}
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phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);
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if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
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if (((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
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(phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) &&
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(phy->ver_addr)) {
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/* Remove 100Mb link supported for BCM84833 when phy fw
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/* Remove 100Mb link supported for BCM84833/4 when phy fw
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* version lower than or equal to 1.39
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*/
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u32 raw_ver = REG_RD(bp, phy->ver_addr);
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@ -13015,7 +13060,8 @@ static int bnx2x_84833_common_init_phy(struct bnx2x *bp,
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}
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static int bnx2x_84833_pre_init_phy(struct bnx2x *bp,
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struct bnx2x_phy *phy)
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struct bnx2x_phy *phy,
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u8 port)
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{
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u16 val, cnt;
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/* Wait for FW completing its initialization. */
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@ -13042,26 +13088,28 @@ static int bnx2x_84833_pre_init_phy(struct bnx2x *bp,
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MDIO_84833_TOP_CFG_XGPHY_STRAP1, val);
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/* Save spirom version */
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bnx2x_save_848xx_spirom_version(phy, bp, PORT_0);
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bnx2x_save_848xx_spirom_version(phy, bp, port);
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return 0;
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}
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int bnx2x_pre_init_phy(struct bnx2x *bp,
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u32 shmem_base,
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u32 shmem2_base,
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u32 chip_id)
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u32 chip_id,
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u8 port)
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{
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int rc = 0;
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struct bnx2x_phy phy;
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if (bnx2x_populate_phy(bp, EXT_PHY1, shmem_base, shmem2_base,
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PORT_0, &phy)) {
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port, &phy) != 0) {
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DP(NETIF_MSG_LINK, "populate_phy failed\n");
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return -EINVAL;
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}
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bnx2x_set_mdio_clk(bp, chip_id, phy.mdio_ctrl);
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switch (phy.type) {
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case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
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rc = bnx2x_84833_pre_init_phy(bp, &phy);
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case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834:
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rc = bnx2x_84833_pre_init_phy(bp, &phy, port);
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break;
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default:
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break;
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@ -13098,6 +13146,7 @@ static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[],
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phy_index, chip_id);
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break;
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case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
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case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834:
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/* GPIO3's are linked, and so both need to be toggled
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* to obtain required 2us pulse.
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*/
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