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drm/i915: Performed deferred clflush inside set-cache-level 

Currently we are hitting the WARN inside
i915_gem_object_set_cache_level() as we can now have an unbound object
in the GTT write domain (due to 43566dedde "drm/i915: Broaden
application of set-domain(GTT)"). To avoid the warning, we need to track
when we elided the clflush on a cacheable object and then evict the
cache for the object when we move the object out of a cacheable domain.

Reported-by: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Tested-by: Jani Nikula <jani.nikula@intel.com>
Testcase: igt/gem_mmap_wc/set-cache-level
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88607
Tested-by: huax.lu@intel.com
[danvet: Split if into nested if as discussion on the m-l.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Chris Wilson 2015-01-13 13:32:52 +00:00 committed by Daniel Vetter
parent a7cbedec83
commit 0f71979ab7
2 changed files with 10 additions and 22 deletions
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1
drivers/gpu/drm/i915/i915_drv.h
View File

@ -2055,6 +2055,7 @@ struct drm_i915_gem_object {
*/ */
unsigned long gt_ro:1; unsigned long gt_ro:1;
unsigned int cache_level:3; unsigned int cache_level:3;
unsigned int cache_dirty:1;
unsigned int has_dma_mapping:1; unsigned int has_dma_mapping:1;

31
drivers/gpu/drm/i915/i915_gem.c
View File

@ -3637,11 +3637,14 @@ i915_gem_clflush_object(struct drm_i915_gem_object *obj,
* snooping behaviour occurs naturally as the result of our domain * snooping behaviour occurs naturally as the result of our domain
* tracking. * tracking.
*/ */
if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) {
obj->cache_dirty = true;
return false; return false;
}
trace_i915_gem_object_clflush(obj); trace_i915_gem_object_clflush(obj);
drm_clflush_sg(obj->pages); drm_clflush_sg(obj->pages);
obj->cache_dirty = false;
return true; return true;
} }
@ -3824,27 +3827,11 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
vma->node.color = cache_level; vma->node.color = cache_level;
obj->cache_level = cache_level; obj->cache_level = cache_level;
if (cpu_write_needs_clflush(obj)) { if (obj->cache_dirty &&
u32 old_read_domains, old_write_domain; obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
cpu_write_needs_clflush(obj)) {
/* If we're coming from LLC cached, then we haven't if (i915_gem_clflush_object(obj, true))
* actually been tracking whether the data is in the i915_gem_chipset_flush(obj->base.dev);
* CPU cache or not, since we only allow one bit set
* in obj->write_domain and have been skipping the clflushes.
* Just set it to the CPU cache for now.
*/
i915_gem_object_retire(obj);
WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
old_read_domains = obj->base.read_domains;
old_write_domain = obj->base.write_domain;
obj->base.read_domains = I915_GEM_DOMAIN_CPU;
obj->base.write_domain = I915_GEM_DOMAIN_CPU;
trace_i915_gem_object_change_domain(obj,
old_read_domains,
old_write_domain);
} }
return 0; return 0;