mirror of https://gitee.com/openkylin/linux.git
ARM: consolidate SMP cross call implementation
Rather than having each platform class provide a mach/smp.h header for smp_cross_call(), arrange for them to register the function with the core ARM SMP code instead. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King
parent
43b3e18982
commit
0f7b332f97
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@ -14,8 +14,6 @@
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#include <linux/cpumask.h>
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#include <linux/thread_info.h>
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#include <mach/smp.h>
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#ifndef CONFIG_SMP
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# error "<asm/smp.h> included in non-SMP build"
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#endif
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@ -47,9 +45,9 @@ extern void smp_init_cpus(void);
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/*
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* Raise an IPI cross call on CPUs in callmap.
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* Provide a function to raise an IPI cross call on CPUs in callmap.
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*/
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extern void smp_cross_call(const struct cpumask *mask, int ipi);
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extern void set_smp_cross_call(void (*)(const struct cpumask *, unsigned int));
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/*
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* Boot a secondary CPU, and assign it the specified idle task.
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@ -376,6 +376,13 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
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}
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}
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static void (*smp_cross_call)(const struct cpumask *, unsigned int);
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void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int))
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{
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smp_cross_call = fn;
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}
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void arch_send_call_function_ipi_mask(const struct cpumask *mask)
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{
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smp_cross_call(mask, IPI_CALL_FUNC);
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@ -1,19 +0,0 @@
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/* linux/arch/arm/mach-exynos4/include/mach/smp.h
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*
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* Cloned from arch/arm/mach-realview/include/mach/smp.h
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*/
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#ifndef ASM_ARCH_SMP_H
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#define ASM_ARCH_SMP_H __FILE__
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#include <asm/hardware/gic.h>
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/*
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* We use IRQ1 as the IPI
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*/
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static inline void smp_cross_call(const struct cpumask *mask, int ipi)
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{
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gic_raise_softirq(mask, ipi);
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}
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#endif
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@ -22,6 +22,7 @@
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#include <linux/io.h>
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#include <asm/cacheflush.h>
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#include <asm/hardware/gic.h>
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#include <asm/smp_scu.h>
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#include <asm/unified.h>
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@ -104,7 +105,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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* the boot monitor to read the system wide flags register,
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* and branch to the address found there.
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*/
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smp_cross_call(cpumask_of(cpu), 1);
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gic_raise_softirq(cpumask_of(cpu), 1);
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timeout = jiffies + (1 * HZ);
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while (time_before(jiffies, timeout)) {
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@ -147,6 +148,8 @@ void __init smp_init_cpus(void)
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for (i = 0; i < ncores; i++)
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set_cpu_possible(i, true);
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set_smp_cross_call(gic_raise_softirq);
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}
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void __init platform_smp_prepare_cpus(unsigned int max_cpus)
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@ -1,23 +0,0 @@
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/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __ASM_ARCH_MSM_SMP_H
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#define __ASM_ARCH_MSM_SMP_H
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#include <asm/hardware/gic.h>
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static inline void smp_cross_call(const struct cpumask *mask, int ipi)
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{
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gic_raise_softirq(mask, ipi);
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}
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#endif
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@ -119,7 +119,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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* the boot monitor to read the system wide flags register,
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* and branch to the address found there.
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*/
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smp_cross_call(cpumask_of(cpu), 1);
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gic_raise_softirq(cpumask_of(cpu), 1);
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timeout = jiffies + (1 * HZ);
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while (time_before(jiffies, timeout)) {
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@ -151,6 +151,8 @@ void __init smp_init_cpus(void)
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for (i = 0; i < NR_CPUS; i++)
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set_cpu_possible(i, true);
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set_smp_cross_call(gic_raise_softirq);
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}
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void __init platform_smp_prepare_cpus(unsigned int max_cpus)
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@ -21,6 +21,7 @@
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#include <linux/io.h>
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#include <asm/cacheflush.h>
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#include <asm/hardware/gic.h>
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#include <asm/smp_scu.h>
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#include <mach/hardware.h>
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#include <mach/omap4-common.h>
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@ -63,7 +64,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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omap_modify_auxcoreboot0(0x200, 0xfffffdff);
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flush_cache_all();
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smp_wmb();
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smp_cross_call(cpumask_of(cpu), 1);
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gic_raise_softirq(cpumask_of(cpu), 1);
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/*
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* Now the secondary core is starting up let it run its
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@ -118,6 +119,8 @@ void __init smp_init_cpus(void)
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for (i = 0; i < ncores; i++)
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set_cpu_possible(i, true);
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set_smp_cross_call(gic_raise_softirq);
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}
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void __init platform_smp_prepare_cpus(unsigned int max_cpus)
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@ -1,14 +0,0 @@
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#ifndef ASMARM_ARCH_SMP_H
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#define ASMARM_ARCH_SMP_H
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#include <asm/hardware/gic.h>
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/*
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* We use IRQ1 as the IPI
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*/
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static inline void smp_cross_call(const struct cpumask *mask, int ipi)
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{
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gic_raise_softirq(mask, ipi);
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}
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#endif
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@ -14,6 +14,7 @@
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#include <linux/io.h>
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#include <mach/hardware.h>
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#include <asm/hardware/gic.h>
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#include <asm/mach-types.h>
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#include <asm/smp_scu.h>
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#include <asm/unified.h>
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@ -61,6 +62,8 @@ void __init smp_init_cpus(void)
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for (i = 0; i < ncores; i++)
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set_cpu_possible(i, true);
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set_smp_cross_call(gic_raise_softirq);
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}
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void __init platform_smp_prepare_cpus(unsigned int max_cpus)
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@ -1,16 +0,0 @@
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#ifndef __MACH_SMP_H
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#define __MACH_SMP_H
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#include <asm/hardware/gic.h>
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/*
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* We use IRQ1 as the IPI
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*/
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static inline void smp_cross_call(const struct cpumask *mask, int ipi)
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{
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#if defined(CONFIG_ARM_GIC)
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gic_raise_softirq(mask, ipi);
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#endif
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}
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#endif
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@ -16,6 +16,7 @@
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#include <linux/device.h>
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#include <linux/smp.h>
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#include <linux/io.h>
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#include <asm/hardware/gic.h>
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#include <asm/localtimer.h>
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#include <asm/mach-types.h>
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#include <mach/common.h>
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@ -57,6 +58,8 @@ void __init smp_init_cpus(void)
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for (i = 0; i < ncores; i++)
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set_cpu_possible(i, true);
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set_smp_cross_call(gic_raise_softirq);
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}
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void __init platform_smp_prepare_cpus(unsigned int max_cpus)
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@ -1,14 +0,0 @@
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#ifndef ASMARM_ARCH_SMP_H
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#define ASMARM_ARCH_SMP_H
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#include <asm/hardware/gic.h>
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/*
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* We use IRQ1 as the IPI
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*/
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static inline void smp_cross_call(const struct cpumask *mask, int ipi)
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{
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gic_raise_softirq(mask, ipi);
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}
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#endif
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@ -20,6 +20,7 @@
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#include <linux/io.h>
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#include <asm/cacheflush.h>
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#include <asm/hardware/gic.h>
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#include <mach/hardware.h>
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#include <asm/mach-types.h>
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#include <asm/smp_scu.h>
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@ -122,6 +123,8 @@ void __init smp_init_cpus(void)
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for (i = 0; i < ncores; i++)
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cpu_set(i, cpu_possible_map);
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set_smp_cross_call(gic_raise_softirq);
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}
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void __init platform_smp_prepare_cpus(unsigned int max_cpus)
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@ -1,24 +0,0 @@
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/*
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* This file is based ARM realview platform.
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* Copyright (C) ARM Limited.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef ASMARM_ARCH_SMP_H
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#define ASMARM_ARCH_SMP_H
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#include <asm/hardware/gic.h>
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/* This is required to wakeup the secondary core */
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extern void u8500_secondary_startup(void);
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/*
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* We use IRQ1 as the IPI
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*/
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static inline void smp_cross_call(const struct cpumask *mask, int ipi)
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{
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gic_raise_softirq(mask, ipi);
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}
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#endif
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@ -18,6 +18,7 @@
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#include <linux/io.h>
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#include <asm/cacheflush.h>
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#include <asm/hardware/gic.h>
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#include <asm/smp_scu.h>
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#include <mach/hardware.h>
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#include <mach/setup.h>
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@ -94,7 +95,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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*/
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write_pen_release(cpu);
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smp_cross_call(cpumask_of(cpu), 1);
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gic_raise_softirq(cpumask_of(cpu), 1);
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timeout = jiffies + (1 * HZ);
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while (time_before(jiffies, timeout)) {
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@ -162,6 +163,8 @@ void __init smp_init_cpus(void)
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for (i = 0; i < ncores; i++)
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set_cpu_possible(i, true);
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set_smp_cross_call(gic_raise_softirq);
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}
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void __init platform_smp_prepare_cpus(unsigned int max_cpus)
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@ -210,6 +210,8 @@ static void ct_ca9x4_init_cpu_map(void)
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for (i = 0; i < ncores; ++i)
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set_cpu_possible(i, true);
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set_smp_cross_call(gic_raise_softirq);
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}
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static void ct_ca9x4_smp_enable(unsigned int max_cpus)
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@ -1,13 +0,0 @@
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#ifndef __MACH_SMP_H
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#define __MACH_SMP_H
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#include <asm/hardware/gic.h>
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/*
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* We use IRQ1 as the IPI
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*/
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static inline void smp_cross_call(const struct cpumask *mask, int ipi)
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{
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gic_raise_softirq(mask, ipi);
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}
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#endif
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@ -1,30 +0,0 @@
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/*
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* OMAP4 machine specific smp.h
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*
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* Copyright (C) 2009 Texas Instruments, Inc.
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*
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* Author:
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* Santosh Shilimkar <santosh.shilimkar@ti.com>
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*
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* Interface functions needed for the SMP. This file is based on arm
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* realview smp platform.
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* Copyright (c) 2003 ARM Limited.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef OMAP_ARCH_SMP_H
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#define OMAP_ARCH_SMP_H
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#include <asm/hardware/gic.h>
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/*
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* We use Soft IRQ1 as the IPI
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*/
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static inline void smp_cross_call(const struct cpumask *mask, int ipi)
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{
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gic_raise_softirq(mask, ipi);
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}
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#endif
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@ -16,6 +16,7 @@
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#include <linux/smp.h>
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#include <asm/cacheflush.h>
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#include <asm/hardware/gic.h>
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/*
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* control for which core is the next to come out of the secondary
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@ -83,7 +84,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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* the boot monitor to read the system wide flags register,
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* and branch to the address found there.
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*/
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smp_cross_call(cpumask_of(cpu), 1);
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gic_raise_softirq(cpumask_of(cpu), 1);
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timeout = jiffies + (1 * HZ);
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while (time_before(jiffies, timeout)) {
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