openkylin
/
linux
mirror of https://gitee.com/openkylin/linux.git
9
0
Fork 0
Code Issues Projects Releases Wiki Activity

dt-bindings: clock: meson8b: describe the embedded reset controller 

The Amlogic Meson8/Meson8b/Meson8m2 clock controller provides some reset
lines. These are used for example to boot the secondary CPU cores.

This patch describes the reset controller which is embedded into the
clock controller on these SoCs.
A header file is provided which provides preprocessor macros for each
reset line (to make the .dts files easier to read).

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
This commit is contained in:
Martin Blumenstingl 2017-07-28 23:13:11 +02:00 committed by Neil Armstrong
parent 5771a8c088
commit 0f9b973b65
2 changed files with 35 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
View File

@ -16,18 +16,25 @@ Required Properties:
mapped region.
- #clock-cells: should be 1.
- #reset-cells: should be 1.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. All available clocks are defined as
preprocessor macros in the dt-bindings/clock/meson8b-clkc.h header and can be
used in device tree sources.
Similarly a preprocessor macro for each reset line is defined in
dt-bindings/reset/amlogic,meson8b-clkc-reset.h (which can be used from the
device tree sources).
Example: Clock controller node:
clkc: clock-controller@c1104000 {
#clock-cells = <1>;
compatible = "amlogic,meson8b-clkc";
reg = <0xc1108000 0x4>, <0xc1104000 0x460>;
#clock-cells = <1>;
#reset-cells = <1>;
};

27
include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h Normal file
View File

@ -0,0 +1,27 @@
/*
* Copyright (c) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
#ifndef _DT_BINDINGS_AMLOGIC_MESON8B_CLKC_RESET_H
#define _DT_BINDINGS_AMLOGIC_MESON8B_CLKC_RESET_H
#define CLKC_RESET_L2_CACHE_SOFT_RESET 0
#define CLKC_RESET_AXI_64_TO_128_BRIDGE_A5_SOFT_RESET 1
#define CLKC_RESET_SCU_SOFT_RESET 2
#define CLKC_RESET_CPU0_SOFT_RESET 3
#define CLKC_RESET_CPU1_SOFT_RESET 4
#define CLKC_RESET_CPU2_SOFT_RESET 5
#define CLKC_RESET_CPU3_SOFT_RESET 6
#define CLKC_RESET_A5_GLOBAL_RESET 7
#define CLKC_RESET_A5_AXI_SOFT_RESET 8
#define CLKC_RESET_A5_ABP_SOFT_RESET 9
#define CLKC_RESET_AXI_64_TO_128_BRIDGE_MMC_SOFT_RESET 10
#define CLKC_RESET_VID_CLK_CNTL_SOFT_RESET 11
#define CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_POST 12
#define CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_PRE 13
#define CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST 14
#define CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE 15
#endif /* _DT_BINDINGS_AMLOGIC_MESON8B_CLKC_RESET_H */