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drm/radeon: implement tn_set_vce_clocks 

This implements the function to set the vce clocks
on TN hardware.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher 2015-05-11 22:01:50 +02:00
parent b7af630c13
commit 0fda42ac40
4 changed files with 40 additions and 0 deletions
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31
drivers/gpu/drm/radeon/ni.c
View File

@ -2554,3 +2554,34 @@ void cayman_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
radeon_ring_write(ring, 0x0); radeon_ring_write(ring, 0x0);
} }
int tn_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk)
{
struct atom_clock_dividers dividers;
int r, i;
r = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
ecclk, false, &dividers);
if (r)
return r;
for (i = 0; i < 100; i++) {
if (RREG32(CG_ECLK_STATUS) & ECLK_STATUS)
break;
mdelay(10);
}
if (i == 100)
return -ETIMEDOUT;
WREG32_P(CG_ECLK_CNTL, dividers.post_div, ~(ECLK_DIR_CNTL_EN|ECLK_DIVIDER_MASK));
for (i = 0; i < 100; i++) {
if (RREG32(CG_ECLK_STATUS) & ECLK_STATUS)
break;
mdelay(10);
}
if (i == 100)
return -ETIMEDOUT;
return 0;
}

7
drivers/gpu/drm/radeon/nid.h
View File

@ -46,6 +46,13 @@
#define DMIF_ADDR_CONFIG 0xBD4 #define DMIF_ADDR_CONFIG 0xBD4
/* fusion vce clocks */
#define CG_ECLK_CNTL 0x620
# define ECLK_DIVIDER_MASK 0x7f
# define ECLK_DIR_CNTL_EN (1 << 8)
#define CG_ECLK_STATUS 0x624
# define ECLK_STATUS (1 << 0)
/* DCE6 only */ /* DCE6 only */
#define DMIF_ADDR_CALC 0xC00 #define DMIF_ADDR_CALC 0xC00

1
drivers/gpu/drm/radeon/radeon_asic.c
View File

@ -1838,6 +1838,7 @@ static struct radeon_asic trinity_asic = {
.set_pcie_lanes = NULL, .set_pcie_lanes = NULL,
.set_clock_gating = NULL, .set_clock_gating = NULL,
.set_uvd_clocks = &sumo_set_uvd_clocks, .set_uvd_clocks = &sumo_set_uvd_clocks,
.set_vce_clocks = &tn_set_vce_clocks,
.get_temperature = &tn_get_temp, .get_temperature = &tn_get_temp,
}, },
.dpm = { .dpm = {

1
drivers/gpu/drm/radeon/radeon_asic.h
View File

@ -694,6 +694,7 @@ int trinity_dpm_force_performance_level(struct radeon_device *rdev,
void trinity_dpm_enable_bapm(struct radeon_device *rdev, bool enable); void trinity_dpm_enable_bapm(struct radeon_device *rdev, bool enable);
u32 trinity_dpm_get_current_sclk(struct radeon_device *rdev); u32 trinity_dpm_get_current_sclk(struct radeon_device *rdev);
u32 trinity_dpm_get_current_mclk(struct radeon_device *rdev); u32 trinity_dpm_get_current_mclk(struct radeon_device *rdev);
int tn_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk);
/* DCE6 - SI */ /* DCE6 - SI */
void dce6_bandwidth_update(struct radeon_device *rdev); void dce6_bandwidth_update(struct radeon_device *rdev);