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drm/i915: Unifiy GT powersave suspend logic 

Jesse's patch to only quiescent our rps work and Imre's fix to address
a race with runtime pm and the forcewake reference held by the used
diverging means to address the same bug: Jesse's patch uses
flush_delayed_work while (since we want to make sure rps is set up)
while Imre's used a cancel+manuel refcount adjustment.

Unify them again by simply reusing intel_suspend_gt_powersave in
intel_disable_gt_powersave.

Cc: Imre Deak <imre.deak@intel.com>
Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Daniel Vetter 2014-06-12 17:48:52 +02:00
parent 156c7ca081
commit 10d8d36679
1 changed files with 1 additions and 3 deletions
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4
drivers/gpu/drm/i915/intel_pm.c
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@ -4706,10 +4706,8 @@ void intel_disable_gt_powersave(struct drm_device *dev)
ironlake_disable_drps(dev);
ironlake_disable_rc6(dev);
} else if (IS_GEN6(dev) || IS_GEN7(dev) || IS_BROADWELL(dev)) {
if (cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work))
intel_runtime_pm_put(dev_priv);
intel_suspend_gt_powersave(dev);
cancel_work_sync(&dev_priv->rps.work);
mutex_lock(&dev_priv->rps.hw_lock);
if (IS_VALLEYVIEW(dev))
valleyview_disable_rps(dev);