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ARM: sunxi: dt: add nodes for the mbus clock
mbus is the memory bus clock, and it is present on both sun5i and sun7i machines. Its register layout is compatible with the mod0 one. Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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@ -257,6 +257,14 @@ ir0_clk: clk@01c200b0 {
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "ir0";
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};
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mbus_clk: clk@01c2015c {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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reg = <0x01c2015c 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "mbus";
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};
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};
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soc@01c00000 {
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@ -258,6 +258,14 @@ ir0_clk: clk@01c200b0 {
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "ir0";
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};
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mbus_clk: clk@01c2015c {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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reg = <0x01c2015c 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "mbus";
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};
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};
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soc@01c00000 {
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@ -290,6 +290,14 @@ spi3_clk: clk@01c200d4 {
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "spi3";
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};
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mbus_clk: clk@01c2015c {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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reg = <0x01c2015c 0x4>;
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clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
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clock-output-names = "mbus";
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};
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};
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soc@01c00000 {
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