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Merge branch 'powerpc-next' of master.kernel.org:/pub/scm/linux/kernel/git/galak/powerpc

This commit is contained in:
Paul Mackerras 2008-04-18 13:34:30 +10:00
parent 858c52d15f 1a9ebc0cd2
commit 11a55f2274
100 changed files with 4273 additions and 2531 deletions
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6
Documentation/powerpc/booting-without-of.txt
View File

@ -1645,8 +1645,7 @@ platforms are moved over to use the flattened-device-tree model.
- device_type : should be "network", "hldc", "uart", "transparent"
"bisync", "atm", or "serial".
- compatible : could be "ucc_geth" or "fsl_atm" and so on.
- model : should be "UCC".
- device-id : the ucc number(1-8), corresponding to UCCx in UM.
- cell-index : the ucc number(1-8), corresponding to UCCx in UM.
- reg : Offset and length of the register set for the device
- interrupts : <a b> where a is the interrupt number and b is a
field that represents an encoding of the sense and level
@ -1699,8 +1698,7 @@ platforms are moved over to use the flattened-device-tree model.
ucc@2000 {
device_type = "network";
compatible = "ucc_geth";
model = "UCC";
device-id = <1>;
cell-index = <1>;
reg = <2000 200>;
interrupts = <a0 0>;
interrupt-parent = <700>;

5
arch/powerpc/Kconfig
View File

@ -520,6 +520,11 @@ config FSL_PCI
config 4xx_SOC
bool
config FSL_LBC
bool
help
Freescale Localbus support
# Yes MCA RS/6000s exist but Linux-PPC does not currently support any
config MCA
bool

2
arch/powerpc/Kconfig.debug
View File

@ -269,7 +269,7 @@ config PPC_EARLY_DEBUG_CPM_ADDR
hex "CPM UART early debug transmit descriptor address"
depends on PPC_EARLY_DEBUG_CPM
default "0xfa202008" if PPC_EP88XC
default "0xf0000008" if CPM2
default "0xf0001ff8" if CPM2
default "0xff002008" if CPM1
help
This specifies the address of the transmit descriptor

115
arch/powerpc/boot/cpm-serial.c
View File

@ -11,6 +11,7 @@
#include "types.h"
#include "io.h"
#include "ops.h"
#include "page.h"
struct cpm_scc {
u32 gsmrl;
@ -42,6 +43,22 @@ struct cpm_param {
u16 tbase;
u8 rfcr;
u8 tfcr;
u16 mrblr;
u32 rstate;
u8 res1[4];
u16 rbptr;
u8 res2[6];
u32 tstate;
u8 res3[4];
u16 tbptr;
u8 res4[6];
u16 maxidl;
u16 idlc;
u16 brkln;
u16 brkec;
u16 brkcr;
u16 rmask;
u8 res5[4];
};
struct cpm_bd {
@ -54,10 +71,10 @@ static void *cpcr;
static struct cpm_param *param;
static struct cpm_smc *smc;
static struct cpm_scc *scc;
struct cpm_bd *tbdf, *rbdf;
static struct cpm_bd *tbdf, *rbdf;
static u32 cpm_cmd;
static u8 *muram_start;
static u32 muram_offset;
static void *cbd_addr;
static u32 cbd_offset;
static void (*do_cmd)(int op);
static void (*enable_port)(void);
@ -119,20 +136,25 @@ static int cpm_serial_open(void)
out_8(&param->rfcr, 0x10);
out_8(&param->tfcr, 0x10);
out_be16(&param->mrblr, 1);
out_be16(&param->maxidl, 0);
out_be16(&param->brkec, 0);
out_be16(&param->brkln, 0);
out_be16(&param->brkcr, 0);
rbdf = (struct cpm_bd *)muram_start;
rbdf->addr = (u8 *)(rbdf + 2);
rbdf = cbd_addr;
rbdf->addr = (u8 *)rbdf - 1;
rbdf->sc = 0xa000;
rbdf->len = 1;
tbdf = rbdf + 1;
tbdf->addr = (u8 *)(rbdf + 2) + 1;
tbdf->addr = (u8 *)rbdf - 2;
tbdf->sc = 0x2000;
tbdf->len = 1;
sync();
out_be16(&param->rbase, muram_offset);
out_be16(&param->tbase, muram_offset + sizeof(struct cpm_bd));
out_be16(&param->rbase, cbd_offset);
out_be16(&param->tbase, cbd_offset + sizeof(struct cpm_bd));
do_cmd(CPM_CMD_INIT_RX_TX);
@ -175,10 +197,12 @@ static unsigned char cpm_serial_getc(void)
int cpm_console_init(void *devp, struct serial_console_data *scdp)
{
void *reg_virt[2];
int is_smc = 0, is_cpm2 = 0, n;
unsigned long reg_phys;
void *vreg[2];
u32 reg[2];
int is_smc = 0, is_cpm2 = 0;
void *parent, *muram;
void *muram_addr;
unsigned long muram_offset, muram_size;
if (dt_is_compatible(devp, "fsl,cpm1-smc-uart")) {
is_smc = 1;
@ -202,63 +226,64 @@ int cpm_console_init(void *devp, struct serial_console_data *scdp)
else
do_cmd = cpm1_cmd;
n = getprop(devp, "fsl,cpm-command", &cpm_cmd, 4);
if (n < 4)
if (getprop(devp, "fsl,cpm-command", &cpm_cmd, 4) < 4)
return -1;
n = getprop(devp, "virtual-reg", reg_virt, sizeof(reg_virt));
if (n < (int)sizeof(reg_virt)) {
for (n = 0; n < 2; n++) {
if (!dt_xlate_reg(devp, n, &reg_phys, NULL))
return -1;
reg_virt[n] = (void *)reg_phys;
}
}
if (dt_get_virtual_reg(devp, vreg, 2) < 2)
return -1;
if (is_smc)
smc = reg_virt[0];
smc = vreg[0];
else
scc = reg_virt[0];
scc = vreg[0];
param = reg_virt[1];
param = vreg[1];
parent = get_parent(devp);
if (!parent)
return -1;
n = getprop(parent, "virtual-reg", reg_virt, sizeof(reg_virt));
if (n < (int)sizeof(reg_virt)) {
if (!dt_xlate_reg(parent, 0, &reg_phys, NULL))
return -1;
reg_virt[0] = (void *)reg_phys;
}
cpcr = reg_virt[0];
if (dt_get_virtual_reg(parent, &cpcr, 1) < 1)
return -1;
muram = finddevice("/soc/cpm/muram/data");
if (!muram)
return -1;
/* For bootwrapper-compatible device trees, we assume that the first
* entry has at least 18 bytes, and that #address-cells/#data-cells
* entry has at least 128 bytes, and that #address-cells/#data-cells
* is one for both parent and child.
*/
n = getprop(muram, "virtual-reg", reg_virt, sizeof(reg_virt));
if (n < (int)sizeof(reg_virt)) {
if (!dt_xlate_reg(muram, 0, &reg_phys, NULL))
return -1;
if (dt_get_virtual_reg(muram, &muram_addr, 1) < 1)
return -1;
reg_virt[0] = (void *)reg_phys;
if (getprop(muram, "reg", reg, 8) < 8)
return -1;
muram_offset = reg[0];
muram_size = reg[1];
/* Store the buffer descriptors at the end of the first muram chunk.
* For SMC ports on CPM2-based platforms, relocate the parameter RAM
* just before the buffer descriptors.
*/
cbd_offset = muram_offset + muram_size - 2 * sizeof(struct cpm_bd);
if (is_cpm2 && is_smc) {
u16 *smc_base = (u16 *)param;
u16 pram_offset;
pram_offset = cbd_offset - 64;
pram_offset = _ALIGN_DOWN(pram_offset, 64);
disable_port();
out_be16(smc_base, pram_offset);
param = muram_addr - muram_offset + pram_offset;
}
muram_start = reg_virt[0];
n = getprop(muram, "reg", &muram_offset, 4);
if (n < 4)
return -1;
cbd_addr = muram_addr - muram_offset + cbd_offset;
scdp->open = cpm_serial_open;
scdp->putc = cpm_serial_putc;

27
arch/powerpc/boot/cuboot-pq2.c
View File

@ -128,7 +128,7 @@ static void fixup_pci(void)
u8 *soc_regs;
int i, len;
void *node, *parent_node;
u32 naddr, nsize, mem_log2;
u32 naddr, nsize, mem_pow2, mem_mask;
node = finddevice("/pci");
if (!node || !dt_is_compatible(node, "fsl,pq2-pci"))
@ -141,7 +141,7 @@ static void fixup_pci(void)
soc_regs = (u8 *)fsl_get_immr();
if (!soc_regs)
goto err;
goto unhandled;
dt_get_reg_format(node, &naddr, &nsize);
if (naddr != 3 || nsize != 2)
@ -153,7 +153,7 @@ static void fixup_pci(void)
dt_get_reg_format(parent_node, &naddr, &nsize);
if (naddr != 1 || nsize != 1)
goto err;
goto unhandled;
len = getprop(node, "ranges", pci_ranges_buf,
sizeof(pci_ranges_buf));
@ -170,14 +170,20 @@ static void fixup_pci(void)
}
if (!mem || !mmio || !io)
goto err;
goto unhandled;
if (mem->size[1] != mmio->size[1])
goto unhandled;
if (mem->size[1] & (mem->size[1] - 1))
goto unhandled;
if (io->size[1] & (io->size[1] - 1))
goto unhandled;
if (mem->phys_addr + mem->size[1] == mmio->phys_addr)
mem_base = mem;
else if (mmio->phys_addr + mmio->size[1] == mem->phys_addr)
mem_base = mmio;
else
goto err;
goto unhandled;
out_be32(&pci_regs[1][0], mem_base->phys_addr | 1);
out_be32(&pci_regs[2][0], ~(mem->size[1] + mmio->size[1] - 1));
@ -201,8 +207,9 @@ static void fixup_pci(void)
out_le32(&pci_regs[0][58], 0);
out_le32(&pci_regs[0][60], 0);
mem_log2 = 1 << (__ilog2_u32(bd.bi_memsize - 1) + 1);
out_le32(&pci_regs[0][62], 0xa0000000 | ~((1 << (mem_log2 - 12)) - 1));
mem_pow2 = 1 << (__ilog2_u32(bd.bi_memsize - 1) + 1);
mem_mask = ~(mem_pow2 - 1) >> 12;
out_le32(&pci_regs[0][62], 0xa0000000 | mem_mask);
/* If PCI is disabled, drive RST high to enable. */
if (!(in_le32(&pci_regs[0][32]) & 1)) {
@ -228,7 +235,11 @@ static void fixup_pci(void)
return;
err:
printf("Bad PCI node\r\n");
printf("Bad PCI node -- using existing firmware setup.\r\n");
return;
unhandled:
printf("Unsupported PCI node -- using existing firmware setup.\r\n");
}
static void pq2_platform_fixups(void)

20
arch/powerpc/boot/devtree.c
View File

@ -350,3 +350,23 @@ int dt_is_compatible(void *node, const char *compat)
return 0;
}
int dt_get_virtual_reg(void *node, void **addr, int nres)
{
unsigned long xaddr;
int n;
n = getprop(node, "virtual-reg", addr, nres * 4);
if (n > 0)
return n / 4;
for (n = 0; n < nres; n++) {
if (!dt_xlate_reg(node, n, &xaddr, NULL))
break;
addr[n] = (void *)xaddr;
}
return n;
}

5
arch/powerpc/boot/dts/ep8248e.dts
View File

@ -121,8 +121,7 @@ muram {
data@0 {
compatible = "fsl,cpm-muram-data";
reg = <0 0x1100 0x1140
0xec0 0x9800 0x800>;
reg = <0 0x2000 0x9800 0x800>;
};
};
@ -138,7 +137,7 @@ smc1: serial@11a80 {
device_type = "serial";
compatible = "fsl,mpc8248-smc-uart",
"fsl,cpm2-smc-uart";
reg = <0x11a80 0x20 0x1100 0x40>;
reg = <0x11a80 0x20 0x87fc 2>;
interrupts = <4 8>;
interrupt-parent = <&PIC>;
fsl,cpm-brg = <7>;

73
arch/powerpc/boot/dts/ep88xc.dts
View File

@ -2,7 +2,7 @@
* EP88xC Device Tree Source
*
* Copyright 2006 MontaVista Software, Inc.
* Copyright 2007 Freescale Semiconductor, Inc.
* Copyright 2007,2008 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@ -10,6 +10,7 @@
* option) any later version.
*/
/dts-v1/;
/ {
model = "EP88xC";
@ -23,44 +24,44 @@ cpus {
PowerPC,885@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <d#16>;
i-cache-line-size = <d#16>;
d-cache-size = <d#8192>;
i-cache-size = <d#8192>;
reg = <0x0>;
d-cache-line-size = <16>;
i-cache-line-size = <16>;
d-cache-size = <8192>;
i-cache-size = <8192>;
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
interrupts = <f 2>; // decrementer interrupt
interrupts = <15 2>; // decrementer interrupt
interrupt-parent = <&PIC>;
};
};
memory {
device_type = "memory";
reg = <0 0>;
reg = <0x0 0x0>;
};
localbus@fa200100 {
compatible = "fsl,mpc885-localbus", "fsl,pq1-localbus";
#address-cells = <2>;
#size-cells = <1>;
reg = <fa200100 40>;
reg = <0xfa200100 0x40>;
ranges = <
0 0 fc000000 04000000
3 0 fa000000 01000000
0x0 0x0 0xfc000000 0x4000000
0x3 0x0 0xfa000000 0x1000000
>;
flash@0,2000000 {
compatible = "cfi-flash";
reg = <0 2000000 2000000>;
reg = <0x0 0x2000000 0x2000000>;
bank-width = <4>;
device-width = <2>;
};
board-control@3,400000 {
reg = <3 400000 10>;
reg = <0x3 0x400000 0x10>;
compatible = "fsl,ep88xc-bcsr";
};
};
@ -70,25 +71,25 @@ soc@fa200000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
ranges = <0 fa200000 00004000>;
ranges = <0x0 0xfa200000 0x4000>;
bus-frequency = <0>;
// Temporary -- will go away once kernel uses ranges for get_immrbase().
reg = <fa200000 4000>;
reg = <0xfa200000 0x4000>;
mdio@e00 {
compatible = "fsl,mpc885-fec-mdio", "fsl,pq1-fec-mdio";
reg = <e00 188>;
reg = <0xe00 0x188>;
#address-cells = <1>;
#size-cells = <0>;
PHY0: ethernet-phy@0 {
reg = <0>;
reg = <0x0>;
device_type = "ethernet-phy";
};
PHY1: ethernet-phy@1 {
reg = <1>;
reg = <0x1>;
device_type = "ethernet-phy";
};
};
@ -97,7 +98,7 @@ ethernet@e00 {
device_type = "network";
compatible = "fsl,mpc885-fec-enet",
"fsl,pq1-fec-enet";
reg = <e00 188>;
reg = <0xe00 0x188>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <3 1>;
interrupt-parent = <&PIC>;
@ -109,7 +110,7 @@ ethernet@1e00 {
device_type = "network";
compatible = "fsl,mpc885-fec-enet",
"fsl,pq1-fec-enet";
reg = <1e00 188>;
reg = <0x1e00 0x188>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <7 1>;
interrupt-parent = <&PIC>;
@ -120,7 +121,7 @@ ethernet@1e00 {
PIC: interrupt-controller@0 {
interrupt-controller;
#interrupt-cells = <2>;
reg = <0 24>;
reg = <0x0 0x24>;
compatible = "fsl,mpc885-pic", "fsl,pq1-pic";
};
@ -130,29 +131,29 @@ pcmcia@80 {
#size-cells = <2>;
compatible = "fsl,pq-pcmcia";
device_type = "pcmcia";
reg = <80 80>;
reg = <0x80 0x80>;
interrupt-parent = <&PIC>;
interrupts = <d 1>;
interrupts = <13 1>;
};
cpm@9c0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc885-cpm", "fsl,cpm1";
command-proc = <9c0>;
command-proc = <0x9c0>;
interrupts = <0>; // cpm error interrupt
interrupt-parent = <&CPM_PIC>;
reg = <9c0 40>;
reg = <0x9c0 0x40>;
ranges;
muram@2000 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 2000 2000>;
ranges = <0x0 0x2000 0x2000>;
data@0 {
compatible = "fsl,cpm-muram-data";
reg = <0 1c00>;
reg = <0x0 0x1c00>;
};
};
@ -160,7 +161,7 @@ brg@9f0 {
compatible = "fsl,mpc885-brg",
"fsl,cpm1-brg",
"fsl,cpm-brg";
reg = <9f0 10>;
reg = <0x9f0 0x10>;
};
CPM_PIC: interrupt-controller@930 {
@ -168,7 +169,7 @@ CPM_PIC: interrupt-controller@930 {
#interrupt-cells = <1>;
interrupts = <5 2 0 2>;
interrupt-parent = <&PIC>;
reg = <930 20>;
reg = <0x930 0x20>;
compatible = "fsl,mpc885-cpm-pic",
"fsl,cpm1-pic";
};
@ -178,11 +179,11 @@ serial@a80 {
device_type = "serial";
compatible = "fsl,mpc885-smc-uart",
"fsl,cpm1-smc-uart";
reg = <a80 10 3e80 40>;
reg = <0xa80 0x10 0x3e80 0x40>;
interrupts = <4>;
interrupt-parent = <&CPM_PIC>;
fsl,cpm-brg = <1>;
fsl,cpm-command = <0090>;
fsl,cpm-command = <0x90>;
linux,planetcore-label = "SMC1";
};
@ -191,11 +192,11 @@ serial@a20 {
device_type = "serial";
compatible = "fsl,mpc885-scc-uart",
"fsl,cpm1-scc-uart";
reg = <a20 20 3d00 80>;
interrupts = <1d>;
reg = <0xa20 0x20 0x3d00 0x80>;
interrupts = <29>;
interrupt-parent = <&CPM_PIC>;
fsl,cpm-brg = <2>;
fsl,cpm-command = <0040>;
fsl,cpm-command = <0x40>;
linux,planetcore-label = "SCC2";
};
@ -204,9 +205,9 @@ usb@a00 {
#size-cells = <0>;
compatible = "fsl,mpc885-usb",
"fsl,cpm1-usb";
reg = <a00 18 1c00 80>;
reg = <0xa00 0x18 0x1c00 0x80>;
interrupt-parent = <&CPM_PIC>;
interrupts = <1e>;
interrupts = <30>;
fsl,cpm-command = <0000>;
};
};

83
arch/powerpc/boot/dts/kuroboxHD.dts
View File

@ -7,6 +7,7 @@
* Based on sandpoint.dts
*
* 2006 (c) G. Liakhovetski <g.liakhovetski@gmx.de>
* Copyright 2008 Freescale Semiconductor, Inc.
*
* This file is licensed under
* the terms of the GNU General Public License version 2. This program
@ -17,6 +18,8 @@ XXXX add flash parts, rtc, ??
*/
/dts-v1/;
/ {
model = "KuroboxHD";
compatible = "linkstation";
@ -35,19 +38,19 @@ cpus {
PowerPC,603e { /* Really 8241 */
device_type = "cpu";
reg = <0>;
clock-frequency = <bebc200>; /* Fixed by bootloader */
timebase-frequency = <1743000>; /* Fixed by bootloader */
reg = <0x0>;
clock-frequency = <200000000>; /* Fixed by bootloader */
timebase-frequency = <24391680>; /* Fixed by bootloader */
bus-frequency = <0>; /* Fixed by bootloader */
/* Following required by dtc but not used */
i-cache-size = <4000>;
d-cache-size = <4000>;
i-cache-size = <0x4000>;
d-cache-size = <0x4000>;
};
};
memory {
device_type = "memory";
reg = <00000000 04000000>;
reg = <0x0 0x4000000>;
};
soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */
@ -56,26 +59,26 @@ soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */
device_type = "soc";
compatible = "mpc10x";
store-gathering = <0>; /* 0 == off, !0 == on */
reg = <80000000 00100000>;
ranges = <80000000 80000000 70000000 /* pci mem space */
fc000000 fc000000 00100000 /* EUMB */
fe000000 fe000000 00c00000 /* pci i/o space */
fec00000 fec00000 00300000 /* pci cfg regs */
fef00000 fef00000 00100000>; /* pci iack */
reg = <0x80000000 0x100000>;
ranges = <0x80000000 0x80000000 0x70000000 /* pci mem space */
0xfc000000 0xfc000000 0x100000 /* EUMB */
0xfe000000 0xfe000000 0xc00000 /* pci i/o space */
0xfec00000 0xfec00000 0x300000 /* pci cfg regs */
0xfef00000 0xfef00000 0x100000>; /* pci iack */
i2c@80003000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
reg = <80003000 1000>;
reg = <0x80003000 0x1000>;
interrupts = <5 2>;
interrupt-parent = <&mpic>;
rtc@32 {
device_type = "rtc";
compatible = "ricoh,rs5c372a";
reg = <32>;
reg = <0x32>;
};
};
@ -83,9 +86,9 @@ serial0: serial@80004500 {
cell-index = <0>;
device_type = "serial";
compatible = "ns16550";
reg = <80004500 8>;
clock-frequency = <5d08d88>;
current-speed = <2580>;
reg = <0x80004500 0x8>;
clock-frequency = <97553800>;
current-speed = <9600>;
interrupts = <9 0>;
interrupt-parent = <&mpic>;
};
@ -94,10 +97,10 @@ serial1: serial@80004600 {
cell-index = <1>;
device_type = "serial";
compatible = "ns16550";
reg = <80004600 8>;
clock-frequency = <5d08d88>;
current-speed = <e100>;
interrupts = <a 0>;
reg = <0x80004600 0x8>;
clock-frequency = <97553800>;
current-speed = <57600>;
interrupts = <10 0>;
interrupt-parent = <&mpic>;
};
@ -107,7 +110,7 @@ mpic: interrupt-controller@80040000 {
device_type = "open-pic";
compatible = "chrp,open-pic";
interrupt-controller;
reg = <80040000 40000>;
reg = <0x80040000 0x40000>;
};
pci0: pci@fec00000 {
@ -116,29 +119,29 @@ pci0: pci@fec00000 {
#interrupt-cells = <1>;
device_type = "pci";
compatible = "mpc10x-pci";
reg = <fec00000 400000>;
ranges = <01000000 0 0 fe000000 0 00c00000
02000000 0 80000000 80000000 0 70000000>;
bus-range = <0 ff>;
clock-frequency = <7f28155>;
reg = <0xfec00000 0x400000>;
ranges = <0x1000000 0x0 0x0 0xfe000000 0x0 0xc00000
0x2000000 0x0 0x80000000 0x80000000 0x0 0x70000000>;
bus-range = <0 255>;
clock-frequency = <133333333>;
interrupt-parent = <&mpic>;
interrupt-map-mask = <f800 0 0 7>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 11 - IRQ0 ETH */
5800 0 0 1 &mpic 0 1
5800 0 0 2 &mpic 1 1
5800 0 0 3 &mpic 2 1
5800 0 0 4 &mpic 3 1
0x5800 0x0 0x0 0x1 &mpic 0x0 0x1
0x5800 0x0 0x0 0x2 &mpic 0x1 0x1
0x5800 0x0 0x0 0x3 &mpic 0x2 0x1
0x5800 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 12 - IRQ1 IDE0 */
6000 0 0 1 &mpic 1 1
6000 0 0 2 &mpic 2 1
6000 0 0 3 &mpic 3 1
6000 0 0 4 &mpic 0 1
0x6000 0x0 0x0 0x1 &mpic 0x1 0x1
0x6000 0x0 0x0 0x2 &mpic 0x2 0x1
0x6000 0x0 0x0 0x3 &mpic 0x3 0x1
0x6000 0x0 0x0 0x4 &mpic 0x0 0x1
/* IDSEL 14 - IRQ3 USB2.0 */
7000 0 0 1 &mpic 3 1
7000 0 0 2 &mpic 3 1
7000 0 0 3 &mpic 3 1
7000 0 0 4 &mpic 3 1
0x7000 0x0 0x0 0x1 &mpic 0x3 0x1
0x7000 0x0 0x0 0x2 &mpic 0x3 0x1
0x7000 0x0 0x0 0x3 &mpic 0x3 0x1
0x7000 0x0 0x0 0x4 &mpic 0x3 0x1
>;
};
};

83
arch/powerpc/boot/dts/kuroboxHG.dts
View File

@ -7,6 +7,7 @@
* Based on sandpoint.dts
*
* 2006 (c) G. Liakhovetski <g.liakhovetski@gmx.de>
* Copyright 2008 Freescale Semiconductor, Inc.
*
* This file is licensed under
* the terms of the GNU General Public License version 2. This program
@ -17,6 +18,8 @@ XXXX add flash parts, rtc, ??
*/
/dts-v1/;
/ {
model = "KuroboxHG";
compatible = "linkstation";
@ -35,19 +38,19 @@ cpus {
PowerPC,603e { /* Really 8241 */
device_type = "cpu";
reg = <0>;
clock-frequency = <fdad680>; /* Fixed by bootloader */
timebase-frequency = <1F04000>; /* Fixed by bootloader */
reg = <0x0>;
clock-frequency = <266000000>; /* Fixed by bootloader */
timebase-frequency = <32522240>; /* Fixed by bootloader */
bus-frequency = <0>; /* Fixed by bootloader */
/* Following required by dtc but not used */
i-cache-size = <4000>;
d-cache-size = <4000>;
i-cache-size = <0x4000>;
d-cache-size = <0x4000>;
};
};
memory {
device_type = "memory";
reg = <00000000 08000000>;
reg = <0x0 0x8000000>;
};
soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */
@ -56,26 +59,26 @@ soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */
device_type = "soc";
compatible = "mpc10x";
store-gathering = <0>; /* 0 == off, !0 == on */
reg = <80000000 00100000>;
ranges = <80000000 80000000 70000000 /* pci mem space */
fc000000 fc000000 00100000 /* EUMB */
fe000000 fe000000 00c00000 /* pci i/o space */
fec00000 fec00000 00300000 /* pci cfg regs */
fef00000 fef00000 00100000>; /* pci iack */
reg = <0x80000000 0x100000>;
ranges = <0x80000000 0x80000000 0x70000000 /* pci mem space */
0xfc000000 0xfc000000 0x100000 /* EUMB */
0xfe000000 0xfe000000 0xc00000 /* pci i/o space */
0xfec00000 0xfec00000 0x300000 /* pci cfg regs */
0xfef00000 0xfef00000 0x100000>; /* pci iack */
i2c@80003000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
reg = <80003000 1000>;
reg = <0x80003000 0x1000>;
interrupts = <5 2>;
interrupt-parent = <&mpic>;
rtc@32 {
device_type = "rtc";
compatible = "ricoh,rs5c372a";
reg = <32>;
reg = <0x32>;
};
};
@ -83,9 +86,9 @@ serial0: serial@80004500 {
cell-index = <0>;
device_type = "serial";
compatible = "ns16550";
reg = <80004500 8>;
clock-frequency = <7c044a8>;
current-speed = <2580>;
reg = <0x80004500 0x8>;
clock-frequency = <130041000>;
current-speed = <9600>;
interrupts = <9 0>;
interrupt-parent = <&mpic>;
};
@ -94,10 +97,10 @@ serial1: serial@80004600 {
cell-index = <1>;
device_type = "serial";
compatible = "ns16550";
reg = <80004600 8>;
clock-frequency = <7c044a8>;
current-speed = <e100>;
interrupts = <a 0>;
reg = <0x80004600 0x8>;
clock-frequency = <130041000>;
current-speed = <57600>;
interrupts = <10 0>;
interrupt-parent = <&mpic>;
};
@ -107,7 +110,7 @@ mpic: interrupt-controller@80040000 {
device_type = "open-pic";
compatible = "chrp,open-pic";
interrupt-controller;
reg = <80040000 40000>;
reg = <0x80040000 0x40000>;
};
pci0: pci@fec00000 {
@ -116,29 +119,29 @@ pci0: pci@fec00000 {
#interrupt-cells = <1>;
device_type = "pci";
compatible = "mpc10x-pci";
reg = <fec00000 400000>;
ranges = <01000000 0 0 fe000000 0 00c00000
02000000 0 80000000 80000000 0 70000000>;
bus-range = <0 ff>;
clock-frequency = <7f28155>;
reg = <0xfec00000 0x400000>;
ranges = <0x1000000 0x0 0x0 0xfe000000 0x0 0xc00000
0x2000000 0x0 0x80000000 0x80000000 0x0 0x70000000>;
bus-range = <0 255>;
clock-frequency = <133333333>;
interrupt-parent = <&mpic>;
interrupt-map-mask = <f800 0 0 7>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 11 - IRQ0 ETH */
5800 0 0 1 &mpic 0 1
5800 0 0 2 &mpic 1 1
5800 0 0 3 &mpic 2 1
5800 0 0 4 &mpic 3 1
0x5800 0x0 0x0 0x1 &mpic 0x0 0x1
0x5800 0x0 0x0 0x2 &mpic 0x1 0x1
0x5800 0x0 0x0 0x3 &mpic 0x2 0x1
0x5800 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 12 - IRQ1 IDE0 */
6000 0 0 1 &mpic 1 1
6000 0 0 2 &mpic 2 1
6000 0 0 3 &mpic 3 1
6000 0 0 4 &mpic 0 1
0x6000 0x0 0x0 0x1 &mpic 0x1 0x1
0x6000 0x0 0x0 0x2 &mpic 0x2 0x1
0x6000 0x0 0x0 0x3 &mpic 0x3 0x1
0x6000 0x0 0x0 0x4 &mpic 0x0 0x1
/* IDSEL 14 - IRQ3 USB2.0 */
7000 0 0 1 &mpic 3 1
7000 0 0 2 &mpic 3 1
7000 0 0 3 &mpic 3 1
7000 0 0 4 &mpic 3 1
0x7000 0x0 0x0 0x1 &mpic 0x3 0x1
0x7000 0x0 0x0 0x2 &mpic 0x3 0x1
0x7000 0x0 0x0 0x3 &mpic 0x3 0x1
0x7000 0x0 0x0 0x4 &mpic 0x3 0x1
>;
};
};

97
arch/powerpc/boot/dts/mpc7448hpc2.dts
View File

@ -1,7 +1,7 @@
/*
* MPC7448HPC2 (Taiga) board Device Tree Source
*
* Copyright 2006 Freescale Semiconductor Inc.
* Copyright 2006, 2008 Freescale Semiconductor Inc.
* 2006 Roy Zang <Roy Zang at freescale.com>.
*
* This program is free software; you can redistribute it and/or modify it
@ -10,6 +10,7 @@
* option) any later version.
*/
/dts-v1/;
/ {
model = "mpc7448hpc2";
@ -23,11 +24,11 @@ cpus {
PowerPC,7448@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <20>; // 32 bytes
i-cache-line-size = <20>; // 32 bytes
d-cache-size = <8000>; // L1, 32K bytes
i-cache-size = <8000>; // L1, 32K bytes
reg = <0x0>;
d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <32>; // 32 bytes
d-cache-size = <0x8000>; // L1, 32K bytes
i-cache-size = <0x8000>; // L1, 32K bytes
timebase-frequency = <0>; // 33 MHz, from uboot
clock-frequency = <0>; // From U-Boot
bus-frequency = <0>; // From U-Boot
@ -36,7 +37,7 @@ PowerPC,7448@0 {
memory {
device_type = "memory";
reg = <00000000 20000000 // DDR2 512M at 0
reg = <0x0 0x20000000 // DDR2 512M at 0
>;
};
@ -44,14 +45,14 @@ tsi108@c0000000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "tsi-bridge";
ranges = <00000000 c0000000 00010000>;
reg = <c0000000 00010000>;
ranges = <0x0 0xc0000000 0x10000>;
reg = <0xc0000000 0x10000>;
bus-frequency = <0>;
i2c@7000 {
interrupt-parent = <&mpic>;
interrupts = <E 0>;
reg = <7000 400>;
interrupts = <14 0>;
reg = <0x7000 0x400>;
device_type = "i2c";
compatible = "tsi108-i2c";
};
@ -59,20 +60,20 @@ i2c@7000 {
MDIO: mdio@6000 {
device_type = "mdio";
compatible = "tsi108-mdio";
reg = <6000 50>;
reg = <0x6000 0x50>;
#address-cells = <1>;
#size-cells = <0>;
phy8: ethernet-phy@8 {
interrupt-parent = <&mpic>;
interrupts = <2 1>;
reg = <8>;
reg = <0x8>;
};
phy9: ethernet-phy@9 {
interrupt-parent = <&mpic>;
interrupts = <2 1>;
reg = <9>;
reg = <0x9>;
};
};
@ -82,9 +83,9 @@ ethernet@6200 {
#size-cells = <0>;
device_type = "network";
compatible = "tsi108-ethernet";
reg = <6000 200>;
reg = <0x6000 0x200>;
address = [ 00 06 D2 00 00 01 ];
interrupts = <10 2>;
interrupts = <16 2>;
interrupt-parent = <&mpic>;
mdio-handle = <&MDIO>;
phy-handle = <&phy8>;
@ -96,9 +97,9 @@ ethernet@6600 {
#size-cells = <0>;
device_type = "network";
compatible = "tsi108-ethernet";
reg = <6400 200>;
reg = <0x6400 0x200>;
address = [ 00 06 D2 00 00 02 ];
interrupts = <11 2>;
interrupts = <17 2>;
interrupt-parent = <&mpic>;
mdio-handle = <&MDIO>;
phy-handle = <&phy9>;
@ -107,18 +108,18 @@ ethernet@6600 {
serial@7808 {
device_type = "serial";
compatible = "ns16550";
reg = <7808 200>;
clock-frequency = <3f6b5a00>;
interrupts = <c 0>;
reg = <0x7808 0x200>;
clock-frequency = <1064000000>;
interrupts = <12 0>;
interrupt-parent = <&mpic>;
};
serial@7c08 {
device_type = "serial";
compatible = "ns16550";
reg = <7c08 200>;
clock-frequency = <3f6b5a00>;
interrupts = <d 0>;
reg = <0x7c08 0x200>;
clock-frequency = <1064000000>;
interrupts = <13 0>;
interrupt-parent = <&mpic>;
};
@ -127,7 +128,7 @@ mpic: pic@7400 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <7400 400>;
reg = <0x7400 0x400>;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
@ -138,39 +139,39 @@ pci@1000 {
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <1000 1000>;
reg = <0x1000 0x1000>;
bus-range = <0 0>;
ranges = <02000000 0 e0000000 e0000000 0 1A000000
01000000 0 00000000 fa000000 0 00010000>;
clock-frequency = <7f28154>;
ranges = <0x2000000 0x0 0xe0000000 0xe0000000 0x0 0x1a000000
0x1000000 0x0 0x0 0xfa000000 0x0 0x10000>;
clock-frequency = <133333332>;
interrupt-parent = <&mpic>;
interrupts = <17 2>;
interrupt-map-mask = <f800 0 0 7>;
interrupts = <23 2>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x11 */
0800 0 0 1 &RT0 24 0
0800 0 0 2 &RT0 25 0
0800 0 0 3 &RT0 26 0
0800 0 0 4 &RT0 27 0
0x800 0x0 0x0 0x1 &RT0 0x24 0x0
0x800 0x0 0x0 0x2 &RT0 0x25 0x0
0x800 0x0 0x0 0x3 &RT0 0x26 0x0
0x800 0x0 0x0 0x4 &RT0 0x27 0x0
/* IDSEL 0x12 */
1000 0 0 1 &RT0 25 0
1000 0 0 2 &RT0 26 0
1000 0 0 3 &RT0 27 0
1000 0 0 4 &RT0 24 0
0x1000 0x0 0x0 0x1 &RT0 0x25 0x0
0x1000 0x0 0x0 0x2 &RT0 0x26 0x0
0x1000 0x0 0x0 0x3 &RT0 0x27 0x0
0x1000 0x0 0x0 0x4 &RT0 0x24 0x0
/* IDSEL 0x13 */
1800 0 0 1 &RT0 26 0
1800 0 0 2 &RT0 27 0
1800 0 0 3 &RT0 24 0
1800 0 0 4 &RT0 25 0
0x1800 0x0 0x0 0x1 &RT0 0x26 0x0
0x1800 0x0 0x0 0x2 &RT0 0x27 0x0
0x1800 0x0 0x0 0x3 &RT0 0x24 0x0
0x1800 0x0 0x0 0x4 &RT0 0x25 0x0
/* IDSEL 0x14 */
2000 0 0 1 &RT0 27 0
2000 0 0 2 &RT0 24 0
2000 0 0 3 &RT0 25 0
2000 0 0 4 &RT0 26 0
0x2000 0x0 0x0 0x1 &RT0 0x27 0x0
0x2000 0x0 0x0 0x2 &RT0 0x24 0x0
0x2000 0x0 0x0 0x3 &RT0 0x25 0x0
0x2000 0x0 0x0 0x4 &RT0 0x26 0x0
>;
RT0: router@1180 {
@ -180,7 +181,7 @@ RT0: router@1180 {
#address-cells = <0>;
#interrupt-cells = <2>;
big-endian;
interrupts = <17 2>;
interrupts = <23 2>;
interrupt-parent = <&mpic>;
};
};

132
arch/powerpc/boot/dts/mpc8272ads.dts
View File

@ -1,7 +1,7 @@
/*
* MPC8272 ADS Device Tree Source
*
* Copyright 2005 Freescale Semiconductor Inc.
* Copyright 2005,2008 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@ -9,6 +9,8 @@
* option) any later version.
*/
/dts-v1/;
/ {
model = "MPC8272ADS";
compatible = "fsl,mpc8272ads";
@ -21,11 +23,11 @@ cpus {
PowerPC,8272@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <d#32>;
i-cache-line-size = <d#32>;
d-cache-size = <d#16384>;
i-cache-size = <d#16384>;
reg = <0x0>;
d-cache-line-size = <32>;
i-cache-line-size = <32>;
d-cache-size = <16384>;
i-cache-size = <16384>;
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
@ -34,7 +36,7 @@ PowerPC,8272@0 {
memory {
device_type = "memory";
reg = <0 0>;
reg = <0x0 0x0>;
};
localbus@f0010100 {
@ -42,21 +44,21 @@ localbus@f0010100 {
"fsl,pq2-localbus";
#address-cells = <2>;
#size-cells = <1>;
reg = <f0010100 40>;
reg = <0xf0010100 0x40>;
ranges = <0 0 fe000000 02000000
1 0 f4500000 00008000
3 0 f8200000 00008000>;
ranges = <0x0 0x0 0xfe000000 0x2000000
0x1 0x0 0xf4500000 0x8000
0x3 0x0 0xf8200000 0x8000>;
flash@0,0 {
compatible = "jedec-flash";
reg = <0 0 2000000>;
reg = <0x0 0x0 0x2000000>;
bank-width = <4>;
device-width = <1>;
};
board-control@1,0 {
reg = <1 0 20>;
reg = <0x1 0x0 0x20>;
compatible = "fsl,mpc8272ads-bcsr";
};
@ -65,46 +67,46 @@ PCI_PIC: interrupt-controller@3,0 {
"fsl,pq2ads-pci-pic";
#interrupt-cells = <1>;
interrupt-controller;
reg = <3 0 8>;
reg = <0x3 0x0 0x8>;
interrupt-parent = <&PIC>;
interrupts = <14 8>;
interrupts = <20 8>;
};
};
pci@f0010800 {
device_type = "pci";
reg = <f0010800 10c f00101ac 8 f00101c4 8>;
reg = <0xf0010800 0x10c 0xf00101ac 0x8 0xf00101c4 0x8>;
compatible = "fsl,mpc8272-pci", "fsl,pq2-pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
clock-frequency = <d#66666666>;
interrupt-map-mask = <f800 0 0 7>;
clock-frequency = <66666666>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x16 */
b000 0 0 1 &PCI_PIC 0
b000 0 0 2 &PCI_PIC 1
b000 0 0 3 &PCI_PIC 2
b000 0 0 4 &PCI_PIC 3
0xb000 0x0 0x0 0x1 &PCI_PIC 0
0xb000 0x0 0x0 0x2 &PCI_PIC 1
0xb000 0x0 0x0 0x3 &PCI_PIC 2
0xb000 0x0 0x0 0x4 &PCI_PIC 3
/* IDSEL 0x17 */
b800 0 0 1 &PCI_PIC 4
b800 0 0 2 &PCI_PIC 5
b800 0 0 3 &PCI_PIC 6
b800 0 0 4 &PCI_PIC 7
0xb800 0x0 0x0 0x1 &PCI_PIC 4
0xb800 0x0 0x0 0x2 &PCI_PIC 5
0xb800 0x0 0x0 0x3 &PCI_PIC 6
0xb800 0x0 0x0 0x4 &PCI_PIC 7
/* IDSEL 0x18 */
c000 0 0 1 &PCI_PIC 8
c000 0 0 2 &PCI_PIC 9
c000 0 0 3 &PCI_PIC a
c000 0 0 4 &PCI_PIC b>;
0xc000 0x0 0x0 0x1 &PCI_PIC 8
0xc000 0x0 0x0 0x2 &PCI_PIC 9
0xc000 0x0 0x0 0x3 &PCI_PIC 10
0xc000 0x0 0x0 0x4 &PCI_PIC 11>;
interrupt-parent = <&PIC>;
interrupts = <12 8>;
ranges = <42000000 0 80000000 80000000 0 20000000
02000000 0 a0000000 a0000000 0 20000000
01000000 0 00000000 f6000000 0 02000000>;
interrupts = <18 8>;
ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x20000000
0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
0x1000000 0x0 0x0 0xf6000000 0x0 0x2000000>;
};
soc@f0000000 {
@ -112,26 +114,26 @@ soc@f0000000 {
#size-cells = <1>;
device_type = "soc";
compatible = "fsl,mpc8272", "fsl,pq2-soc";
ranges = <00000000 f0000000 00053000>;
ranges = <0x0 0xf0000000 0x53000>;
// Temporary -- will go away once kernel uses ranges for get_immrbase().
reg = <f0000000 00053000>;
reg = <0xf0000000 0x53000>;
cpm@119c0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8272-cpm", "fsl,cpm2";
reg = <119c0 30>;
reg = <0x119c0 0x30>;
ranges;
muram@0 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 10000>;
ranges = <0x0 0x0 0x10000>;
data@0 {
compatible = "fsl,cpm-muram-data";
reg = <0 2000 9800 800>;
reg = <0x0 0x2000 0x9800 0x800>;
};
};
@ -139,29 +141,29 @@ brg@119f0 {
compatible = "fsl,mpc8272-brg",
"fsl,cpm2-brg",
"fsl,cpm-brg";
reg = <119f0 10 115f0 10>;
reg = <0x119f0 0x10 0x115f0 0x10>;
};
serial@11a00 {
device_type = "serial";
compatible = "fsl,mpc8272-scc-uart",
"fsl,cpm2-scc-uart";
reg = <11a00 20 8000 100>;
interrupts = <28 8>;
reg = <0x11a00 0x20 0x8000 0x100>;
interrupts = <40 8>;
interrupt-parent = <&PIC>;
fsl,cpm-brg = <1>;
fsl,cpm-command = <00800000>;
fsl,cpm-command = <0x800000>;
};
serial@11a60 {
device_type = "serial";
compatible = "fsl,mpc8272-scc-uart",
"fsl,cpm2-scc-uart";
reg = <11a60 20 8300 100>;
interrupts = <2b 8>;
reg = <0x11a60 0x20 0x8300 0x100>;
interrupts = <43 8>;
interrupt-parent = <&PIC>;
fsl,cpm-brg = <4>;
fsl,cpm-command = <0ce00000>;
fsl,cpm-command = <0xce00000>;
};
mdio@10d40 {
@ -169,23 +171,23 @@ mdio@10d40 {
compatible = "fsl,mpc8272ads-mdio-bitbang",
"fsl,mpc8272-mdio-bitbang",
"fsl,cpm2-mdio-bitbang";
reg = <10d40 14>;
reg = <0x10d40 0x14>;
#address-cells = <1>;
#size-cells = <0>;
fsl,mdio-pin = <12>;
fsl,mdc-pin = <13>;
fsl,mdio-pin = <18>;
fsl,mdc-pin = <19>;
PHY0: ethernet-phy@0 {
interrupt-parent = <&PIC>;
interrupts = <17 8>;
reg = <0>;
interrupts = <23 8>;
reg = <0x0>;
device_type = "ethernet-phy";
};
PHY1: ethernet-phy@1 {
interrupt-parent = <&PIC>;
interrupts = <17 8>;
reg = <3>;
interrupts = <23 8>;
reg = <0x3>;
device_type = "ethernet-phy";
};
};
@ -194,33 +196,33 @@ ethernet@11300 {
device_type = "network";
compatible = "fsl,mpc8272-fcc-enet",
"fsl,cpm2-fcc-enet";
reg = <11300 20 8400 100 11390 1>;
reg = <0x11300 0x20 0x8400 0x100 0x11390 0x1>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <20 8>;
interrupts = <32 8>;
interrupt-parent = <&PIC>;
phy-handle = <&PHY0>;
linux,network-index = <0>;
fsl,cpm-command = <12000300>;
fsl,cpm-command = <0x12000300>;
};
ethernet@11320 {
device_type = "network";
compatible = "fsl,mpc8272-fcc-enet",
"fsl,cpm2-fcc-enet";
reg = <11320 20 8500 100 113b0 1>;
reg = <0x11320 0x20 0x8500 0x100 0x113b0 0x1>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <21 8>;
interrupts = <33 8>;
interrupt-parent = <&PIC>;
phy-handle = <&PHY1>;
linux,network-index = <1>;
fsl,cpm-command = <16200300>;
fsl,cpm-command = <0x16200300>;
};
};
PIC: interrupt-controller@10c00 {
#interrupt-cells = <2>;
interrupt-controller;
reg = <10c00 80>;
reg = <0x10c00 0x80>;
compatible = "fsl,mpc8272-pic", "fsl,cpm2-pic";
};
@ -232,14 +234,14 @@ crypto@30000 {
"fsl,talitos-sec2",
"fsl,talitos",
"talitos";
reg = <30000 10000>;
interrupts = <b 8>;
reg = <0x30000 0x10000>;
interrupts = <11 8>;
interrupt-parent = <&PIC>;
num-channels = <4>;
channel-fifo-len = <18>;
exec-units-mask = <0000007e>;
channel-fifo-len = <24>;
exec-units-mask = <0x7e>;
/* desc mask is for rev1.x, we need runtime fixup for >=2.x */
descriptor-types-mask = <01010ebf>;
descriptor-types-mask = <0x1010ebf>;
};
};

7
arch/powerpc/boot/dts/mpc832x_mds.dts
View File

@ -255,9 +255,7 @@ usb@6c0 {
enet0: ucc@2200 {
device_type = "network";
compatible = "ucc_geth";
model = "UCC";
cell-index = <3>;
device-id = <3>;
reg = <0x2200 0x200>;
interrupts = <34>;
interrupt-parent = <&qeic>;
@ -271,9 +269,7 @@ enet0: ucc@2200 {
enet1: ucc@3200 {
device_type = "network";
compatible = "ucc_geth";
model = "UCC";
cell-index = <4>;
device-id = <4>;
reg = <0x3200 0x200>;
interrupts = <35>;
interrupt-parent = <&qeic>;
@ -287,8 +283,7 @@ enet1: ucc@3200 {
ucc@2400 {
device_type = "serial";
compatible = "ucc_uart";
model = "UCC";
device-id = <5>; /* The UCC number, 1-7*/
cell-index = <5>; /* The UCC number, 1-7*/
port-number = <0>; /* Which ttyQEx device */
soft-uart; /* We need Soft-UART */
reg = <0x2400 0x200>;

4
arch/powerpc/boot/dts/mpc832x_rdb.dts
View File

@ -208,9 +208,7 @@ spi@500 {
enet0: ucc@3000 {
device_type = "network";
compatible = "ucc_geth";
model = "UCC";
cell-index = <2>;
device-id = <2>;
reg = <0x3000 0x200>;
interrupts = <33>;
interrupt-parent = <&qeic>;
@ -224,9 +222,7 @@ enet0: ucc@3000 {
enet1: ucc@2200 {
device_type = "network";
compatible = "ucc_geth";
model = "UCC";
cell-index = <3>;
device-id = <3>;
reg = <0x2200 0x200>;
interrupts = <34>;
interrupt-parent = <&qeic>;

4
arch/powerpc/boot/dts/mpc836x_mds.dts
View File

@ -257,9 +257,7 @@ usb@6c0 {
enet0: ucc@2000 {
device_type = "network";
compatible = "ucc_geth";
model = "UCC";
cell-index = <1>;
device-id = <1>;
reg = <0x2000 0x200>;
interrupts = <32>;
interrupt-parent = <&qeic>;
@ -274,9 +272,7 @@ enet0: ucc@2000 {
enet1: ucc@3000 {
device_type = "network";
compatible = "ucc_geth";
model = "UCC";
cell-index = <2>;
device-id = <2>;
reg = <0x3000 0x200>;
interrupts = <33>;
interrupt-parent = <&qeic>;

173
arch/powerpc/boot/dts/mpc8540ads.dts
View File

@ -1,7 +1,7 @@
/*
* MPC8540 ADS Device Tree Source
*
* Copyright 2006 Freescale Semiconductor Inc.
* Copyright 2006, 2008 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@ -9,6 +9,7 @@
* option) any later version.
*/
/dts-v1/;
/ {
model = "MPC8540ADS";
@ -31,11 +32,11 @@ cpus {
PowerPC,8540@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <20>; // 32 bytes
i-cache-line-size = <20>; // 32 bytes
d-cache-size = <8000>; // L1, 32K
i-cache-size = <8000>; // L1, 32K
reg = <0x0>;
d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <32>; // 32 bytes
d-cache-size = <0x8000>; // L1, 32K
i-cache-size = <0x8000>; // L1, 32K
timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // 166 MHz
clock-frequency = <0>; // 825 MHz, from uboot
@ -44,31 +45,31 @@ PowerPC,8540@0 {
memory {
device_type = "memory";
reg = <00000000 08000000>; // 128M at 0x0
reg = <0x0 0x8000000>; // 128M at 0x0
};
soc8540@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00100000>; // CCSRBAR 1M
ranges = <0x0 0xe0000000 0x100000>;
reg = <0xe0000000 0x100000>; // CCSRBAR 1M
bus-frequency = <0>;
memory-controller@2000 {
compatible = "fsl,8540-memory-controller";
reg = <2000 1000>;
reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <12 2>;
interrupts = <18 2>;
};
l2-cache-controller@20000 {
compatible = "fsl,8540-l2-cache-controller";
reg = <20000 1000>;
cache-line-size = <20>; // 32 bytes
cache-size = <40000>; // L2, 256K
reg = <0x20000 0x1000>;
cache-line-size = <32>; // 32 bytes
cache-size = <0x40000>; // L2, 256K
interrupt-parent = <&mpic>;
interrupts = <10 2>;
interrupts = <16 2>;
};
i2c@3000 {
@ -76,8 +77,8 @@ i2c@3000 {
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
reg = <3000 100>;
interrupts = <2b 2>;
reg = <0x3000 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
};
@ -86,24 +87,24 @@ mdio@24520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
reg = <24520 20>;
reg = <0x24520 0x20>;
phy0: ethernet-phy@0 {
interrupt-parent = <&mpic>;
interrupts = <5 1>;
reg = <0>;
reg = <0x0>;
device_type = "ethernet-phy";
};
phy1: ethernet-phy@1 {
interrupt-parent = <&mpic>;
interrupts = <5 1>;
reg = <1>;
reg = <0x1>;
device_type = "ethernet-phy";
};
phy3: ethernet-phy@3 {
interrupt-parent = <&mpic>;
interrupts = <7 1>;
reg = <3>;
reg = <0x3>;
device_type = "ethernet-phy";
};
};
@ -113,9 +114,9 @@ enet0: ethernet@24000 {
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <24000 1000>;
reg = <0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <1d 2 1e 2 22 2>;
interrupts = <29 2 30 2 34 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy0>;
};
@ -125,9 +126,9 @@ enet1: ethernet@25000 {
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <25000 1000>;
reg = <0x25000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <23 2 24 2 28 2>;
interrupts = <35 2 36 2 40 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy1>;
};
@ -137,9 +138,9 @@ enet2: ethernet@26000 {
device_type = "network";
model = "FEC";
compatible = "gianfar";
reg = <26000 1000>;
reg = <0x26000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <29 2>;
interrupts = <41 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy3>;
};
@ -148,9 +149,9 @@ serial0: serial@4500 {
cell-index = <0>;
device_type = "serial";
compatible = "ns16550";
reg = <4500 100>; // reg base, size
reg = <0x4500 0x100>; // reg base, size
clock-frequency = <0>; // should we fill in in uboot?
interrupts = <2a 2>;
interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
@ -158,9 +159,9 @@ serial1: serial@4600 {
cell-index = <1>;
device_type = "serial";
compatible = "ns16550";
reg = <4600 100>; // reg base, size
reg = <0x4600 0x100>; // reg base, size
clock-frequency = <0>; // should we fill in in uboot?
interrupts = <2a 2>;
interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
mpic: pic@40000 {
@ -168,7 +169,7 @@ mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <40000 40000>;
reg = <0x40000 0x40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
@ -177,90 +178,90 @@ mpic: pic@40000 {
pci0: pci@e0008000 {
cell-index = <0>;
interrupt-map-mask = <f800 0 0 7>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x02 */
1000 0 0 1 &mpic 1 1
1000 0 0 2 &mpic 2 1
1000 0 0 3 &mpic 3 1
1000 0 0 4 &mpic 4 1
0x1000 0x0 0x0 0x1 &mpic 0x1 0x1
0x1000 0x0 0x0 0x2 &mpic 0x2 0x1
0x1000 0x0 0x0 0x3 &mpic 0x3 0x1
0x1000 0x0 0x0 0x4 &mpic 0x4 0x1
/* IDSEL 0x03 */
1800 0 0 1 &mpic 4 1
1800 0 0 2 &mpic 1 1
1800 0 0 3 &mpic 2 1
1800 0 0 4 &mpic 3 1
0x1800 0x0 0x0 0x1 &mpic 0x4 0x1
0x1800 0x0 0x0 0x2 &mpic 0x1 0x1
0x1800 0x0 0x0 0x3 &mpic 0x2 0x1
0x1800 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 0x04 */
2000 0 0 1 &mpic 3 1
2000 0 0 2 &mpic 4 1
2000 0 0 3 &mpic 1 1
2000 0 0 4 &mpic 2 1
0x2000 0x0 0x0 0x1 &mpic 0x3 0x1
0x2000 0x0 0x0 0x2 &mpic 0x4 0x1
0x2000 0x0 0x0 0x3 &mpic 0x1 0x1
0x2000 0x0 0x0 0x4 &mpic 0x2 0x1
/* IDSEL 0x05 */
2800 0 0 1 &mpic 2 1
2800 0 0 2 &mpic 3 1
2800 0 0 3 &mpic 4 1
2800 0 0 4 &mpic 1 1
0x2800 0x0 0x0 0x1 &mpic 0x2 0x1
0x2800 0x0 0x0 0x2 &mpic 0x3 0x1
0x2800 0x0 0x0 0x3 &mpic 0x4 0x1
0x2800 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x0c */
6000 0 0 1 &mpic 1 1
6000 0 0 2 &mpic 2 1
6000 0 0 3 &mpic 3 1
6000 0 0 4 &mpic 4 1
0x6000 0x0 0x0 0x1 &mpic 0x1 0x1
0x6000 0x0 0x0 0x2 &mpic 0x2 0x1
0x6000 0x0 0x0 0x3 &mpic 0x3 0x1
0x6000 0x0 0x0 0x4 &mpic 0x4 0x1
/* IDSEL 0x0d */
6800 0 0 1 &mpic 4 1
6800 0 0 2 &mpic 1 1
6800 0 0 3 &mpic 2 1
6800 0 0 4 &mpic 3 1
0x6800 0x0 0x0 0x1 &mpic 0x4 0x1
0x6800 0x0 0x0 0x2 &mpic 0x1 0x1
0x6800 0x0 0x0 0x3 &mpic 0x2 0x1
0x6800 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 0x0e */
7000 0 0 1 &mpic 3 1
7000 0 0 2 &mpic 4 1
7000 0 0 3 &mpic 1 1
7000 0 0 4 &mpic 2 1
0x7000 0x0 0x0 0x1 &mpic 0x3 0x1
0x7000 0x0 0x0 0x2 &mpic 0x4 0x1
0x7000 0x0 0x0 0x3 &mpic 0x1 0x1
0x7000 0x0 0x0 0x4 &mpic 0x2 0x1
/* IDSEL 0x0f */
7800 0 0 1 &mpic 2 1
7800 0 0 2 &mpic 3 1
7800 0 0 3 &mpic 4 1
7800 0 0 4 &mpic 1 1
0x7800 0x0 0x0 0x1 &mpic 0x2 0x1
0x7800 0x0 0x0 0x2 &mpic 0x3 0x1
0x7800 0x0 0x0 0x3 &mpic 0x4 0x1
0x7800 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x12 */
9000 0 0 1 &mpic 1 1
9000 0 0 2 &mpic 2 1
9000 0 0 3 &mpic 3 1
9000 0 0 4 &mpic 4 1
0x9000 0x0 0x0 0x1 &mpic 0x1 0x1
0x9000 0x0 0x0 0x2 &mpic 0x2 0x1
0x9000 0x0 0x0 0x3 &mpic 0x3 0x1
0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
/* IDSEL 0x13 */
9800 0 0 1 &mpic 4 1
9800 0 0 2 &mpic 1 1
9800 0 0 3 &mpic 2 1
9800 0 0 4 &mpic 3 1
0x9800 0x0 0x0 0x1 &mpic 0x4 0x1
0x9800 0x0 0x0 0x2 &mpic 0x1 0x1
0x9800 0x0 0x0 0x3 &mpic 0x2 0x1
0x9800 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 0x14 */
a000 0 0 1 &mpic 3 1
a000 0 0 2 &mpic 4 1
a000 0 0 3 &mpic 1 1
a000 0 0 4 &mpic 2 1
0xa000 0x0 0x0 0x1 &mpic 0x3 0x1
0xa000 0x0 0x0 0x2 &mpic 0x4 0x1
0xa000 0x0 0x0 0x3 &mpic 0x1 0x1
0xa000 0x0 0x0 0x4 &mpic 0x2 0x1
/* IDSEL 0x15 */
a800 0 0 1 &mpic 2 1
a800 0 0 2 &mpic 3 1
a800 0 0 3 &mpic 4 1
a800 0 0 4 &mpic 1 1>;
0xa800 0x0 0x0 0x1 &mpic 0x2 0x1
0xa800 0x0 0x0 0x2 &mpic 0x3 0x1
0xa800 0x0 0x0 0x3 &mpic 0x4 0x1
0xa800 0x0 0x0 0x4 &mpic 0x1 0x1>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
interrupts = <24 2>;
bus-range = <0 0>;
ranges = <02000000 0 80000000 80000000 0 20000000
01000000 0 00000000 e2000000 0 00100000>;
clock-frequency = <3f940aa>;
ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
clock-frequency = <66666666>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <e0008000 1000>;
reg = <0xe0008000 0x1000>;
compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
device_type = "pci";
};

161
arch/powerpc/boot/dts/mpc8541cds.dts
View File

@ -1,7 +1,7 @@
/*
* MPC8541 CDS Device Tree Source
*
* Copyright 2006 Freescale Semiconductor Inc.
* Copyright 2006, 2008 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@ -9,6 +9,7 @@
* option) any later version.
*/
/dts-v1/;
/ {
model = "MPC8541CDS";
@ -31,11 +32,11 @@ cpus {
PowerPC,8541@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <20>; // 32 bytes
i-cache-line-size = <20>; // 32 bytes
d-cache-size = <8000>; // L1, 32K
i-cache-size = <8000>; // L1, 32K
reg = <0x0>;
d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <32>; // 32 bytes
d-cache-size = <0x8000>; // L1, 32K
i-cache-size = <0x8000>; // L1, 32K
timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // 166 MHz
clock-frequency = <0>; // 825 MHz, from uboot
@ -44,31 +45,31 @@ PowerPC,8541@0 {
memory {
device_type = "memory";
reg = <00000000 08000000>; // 128M at 0x0
reg = <0x0 0x8000000>; // 128M at 0x0
};
soc8541@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00001000>; // CCSRBAR 1M
ranges = <0x0 0xe0000000 0x100000>;
reg = <0xe0000000 0x1000>; // CCSRBAR 1M
bus-frequency = <0>;
memory-controller@2000 {
compatible = "fsl,8541-memory-controller";
reg = <2000 1000>;
reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <12 2>;
interrupts = <18 2>;
};
l2-cache-controller@20000 {
compatible = "fsl,8541-l2-cache-controller";
reg = <20000 1000>;
cache-line-size = <20>; // 32 bytes
cache-size = <40000>; // L2, 256K
reg = <0x20000 0x1000>;
cache-line-size = <32>; // 32 bytes
cache-size = <0x40000>; // L2, 256K
interrupt-parent = <&mpic>;
interrupts = <10 2>;
interrupts = <16 2>;
};
i2c@3000 {
@ -76,8 +77,8 @@ i2c@3000 {
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
reg = <3000 100>;
interrupts = <2b 2>;
reg = <0x3000 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
};
@ -86,18 +87,18 @@ mdio@24520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
reg = <24520 20>;
reg = <0x24520 0x20>;
phy0: ethernet-phy@0 {
interrupt-parent = <&mpic>;
interrupts = <5 1>;
reg = <0>;
reg = <0x0>;
device_type = "ethernet-phy";
};
phy1: ethernet-phy@1 {
interrupt-parent = <&mpic>;
interrupts = <5 1>;
reg = <1>;
reg = <0x1>;
device_type = "ethernet-phy";
};
};
@ -107,9 +108,9 @@ enet0: ethernet@24000 {
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <24000 1000>;
reg = <0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <1d 2 1e 2 22 2>;
interrupts = <29 2 30 2 34 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy0>;
};
@ -119,9 +120,9 @@ enet1: ethernet@25000 {
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <25000 1000>;
reg = <0x25000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <23 2 24 2 28 2>;
interrupts = <35 2 36 2 40 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy1>;
};
@ -130,9 +131,9 @@ serial0: serial@4500 {
cell-index = <0>;
device_type = "serial";
compatible = "ns16550";
reg = <4500 100>; // reg base, size
reg = <0x4500 0x100>; // reg base, size
clock-frequency = <0>; // should we fill in in uboot?
interrupts = <2a 2>;
interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
@ -140,9 +141,9 @@ serial1: serial@4600 {
cell-index = <1>;
device_type = "serial";
compatible = "ns16550";
reg = <4600 100>; // reg base, size
reg = <0x4600 0x100>; // reg base, size
clock-frequency = <0>; // should we fill in in uboot?
interrupts = <2a 2>;
interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
@ -151,7 +152,7 @@ mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <40000 40000>;
reg = <0x40000 0x40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
@ -161,17 +162,17 @@ cpm@919c0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8541-cpm", "fsl,cpm2";
reg = <919c0 30>;
reg = <0x919c0 0x30>;
ranges;
muram@80000 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 80000 10000>;
ranges = <0x0 0x80000 0x10000>;
data@0 {
compatible = "fsl,cpm-muram-data";
reg = <0 2000 9000 1000>;
reg = <0x0 0x2000 0x9000 0x1000>;
};
};
@ -179,16 +180,16 @@ brg@919f0 {
compatible = "fsl,mpc8541-brg",
"fsl,cpm2-brg",
"fsl,cpm-brg";
reg = <919f0 10 915f0 10>;
reg = <0x919f0 0x10 0x915f0 0x10>;
};
cpmpic: pic@90c00 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
interrupts = <2e 2>;
interrupts = <46 2>;
interrupt-parent = <&mpic>;
reg = <90c00 80>;
reg = <0x90c00 0x80>;
compatible = "fsl,mpc8541-cpm-pic", "fsl,cpm2-pic";
};
};
@ -196,68 +197,68 @@ cpmpic: pic@90c00 {
pci0: pci@e0008000 {
cell-index = <0>;
interrupt-map-mask = <1f800 0 0 7>;
interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x10 */
08000 0 0 1 &mpic 0 1
08000 0 0 2 &mpic 1 1
08000 0 0 3 &mpic 2 1
08000 0 0 4 &mpic 3 1
0x8000 0x0 0x0 0x1 &mpic 0x0 0x1
0x8000 0x0 0x0 0x2 &mpic 0x1 0x1
0x8000 0x0 0x0 0x3 &mpic 0x2 0x1
0x8000 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 0x11 */
08800 0 0 1 &mpic 0 1
08800 0 0 2 &mpic 1 1
08800 0 0 3 &mpic 2 1
08800 0 0 4 &mpic 3 1
0x8800 0x0 0x0 0x1 &mpic 0x0 0x1
0x8800 0x0 0x0 0x2 &mpic 0x1 0x1
0x8800 0x0 0x0 0x3 &mpic 0x2 0x1
0x8800 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 0x12 (Slot 1) */
09000 0 0 1 &mpic 0 1
09000 0 0 2 &mpic 1 1
09000 0 0 3 &mpic 2 1
09000 0 0 4 &mpic 3 1
0x9000 0x0 0x0 0x1 &mpic 0x0 0x1
0x9000 0x0 0x0 0x2 &mpic 0x1 0x1
0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
0x9000 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 0x13 (Slot 2) */
09800 0 0 1 &mpic 1 1
09800 0 0 2 &mpic 2 1
09800 0 0 3 &mpic 3 1
09800 0 0 4 &mpic 0 1
0x9800 0x0 0x0 0x1 &mpic 0x1 0x1
0x9800 0x0 0x0 0x2 &mpic 0x2 0x1
0x9800 0x0 0x0 0x3 &mpic 0x3 0x1
0x9800 0x0 0x0 0x4 &mpic 0x0 0x1
/* IDSEL 0x14 (Slot 3) */
0a000 0 0 1 &mpic 2 1
0a000 0 0 2 &mpic 3 1
0a000 0 0 3 &mpic 0 1
0a000 0 0 4 &mpic 1 1
0xa000 0x0 0x0 0x1 &mpic 0x2 0x1
0xa000 0x0 0x0 0x2 &mpic 0x3 0x1
0xa000 0x0 0x0 0x3 &mpic 0x0 0x1
0xa000 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x15 (Slot 4) */
0a800 0 0 1 &mpic 3 1
0a800 0 0 2 &mpic 0 1
0a800 0 0 3 &mpic 1 1
0a800 0 0 4 &mpic 2 1
0xa800 0x0 0x0 0x1 &mpic 0x3 0x1
0xa800 0x0 0x0 0x2 &mpic 0x0 0x1
0xa800 0x0 0x0 0x3 &mpic 0x1 0x1
0xa800 0x0 0x0 0x4 &mpic 0x2 0x1
/* Bus 1 (Tundra Bridge) */
/* IDSEL 0x12 (ISA bridge) */
19000 0 0 1 &mpic 0 1
19000 0 0 2 &mpic 1 1
19000 0 0 3 &mpic 2 1
19000 0 0 4 &mpic 3 1>;
0x19000 0x0 0x0 0x1 &mpic 0x0 0x1
0x19000 0x0 0x0 0x2 &mpic 0x1 0x1
0x19000 0x0 0x0 0x3 &mpic 0x2 0x1
0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
interrupts = <24 2>;
bus-range = <0 0>;
ranges = <02000000 0 80000000 80000000 0 20000000
01000000 0 00000000 e2000000 0 00100000>;
clock-frequency = <3f940aa>;
ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
clock-frequency = <66666666>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <e0008000 1000>;
reg = <0xe0008000 0x1000>;
compatible = "fsl,mpc8540-pci";
device_type = "pci";
i8259@19000 {
interrupt-controller;
device_type = "interrupt-controller";
reg = <19000 0 0 0 1>;
reg = <0x19000 0x0 0x0 0x0 0x1>;
#address-cells = <0>;
#interrupt-cells = <2>;
compatible = "chrp,iic";
@ -268,24 +269,24 @@ i8259@19000 {
pci1: pci@e0009000 {
cell-index = <1>;
interrupt-map-mask = <f800 0 0 7>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x15 */
a800 0 0 1 &mpic b 1
a800 0 0 2 &mpic b 1
a800 0 0 3 &mpic b 1
a800 0 0 4 &mpic b 1>;
0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
0xa800 0x0 0x0 0x2 &mpic 0xb 0x1
0xa800 0x0 0x0 0x3 &mpic 0xb 0x1
0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>;
interrupt-parent = <&mpic>;
interrupts = <19 2>;
interrupts = <25 2>;
bus-range = <0 0>;
ranges = <02000000 0 a0000000 a0000000 0 20000000
01000000 0 00000000 e3000000 0 00100000>;
clock-frequency = <3f940aa>;
ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
clock-frequency = <66666666>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <e0009000 1000>;
reg = <0xe0009000 0x1000>;
compatible = "fsl,mpc8540-pci";
device_type = "pci";
};

299
arch/powerpc/boot/dts/mpc8544ds.dts
View File

@ -1,7 +1,7 @@
/*
* MPC8544 DS Device Tree Source
*
* Copyright 2007 Freescale Semiconductor Inc.
* Copyright 2007, 2008 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@ -9,6 +9,7 @@
* option) any later version.
*/
/dts-v1/;
/ {
model = "MPC8544DS";
compatible = "MPC8544DS", "MPC85xxDS";
@ -27,17 +28,16 @@ aliases {
};
cpus {
#cpus = <1>;
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8544@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <20>; // 32 bytes
i-cache-line-size = <20>; // 32 bytes
d-cache-size = <8000>; // L1, 32K
i-cache-size = <8000>; // L1, 32K
reg = <0x0>;
d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <32>; // 32 bytes
d-cache-size = <0x8000>; // L1, 32K
i-cache-size = <0x8000>; // L1, 32K
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
@ -46,7 +46,7 @@ PowerPC,8544@0 {
memory {
device_type = "memory";
reg = <00000000 00000000>; // Filled by U-Boot
reg = <0x0 0x0>; // Filled by U-Boot
};
soc8544@e0000000 {
@ -54,24 +54,24 @@ soc8544@e0000000 {
#size-cells = <1>;
device_type = "soc";
ranges = <00000000 e0000000 00100000>;
reg = <e0000000 00001000>; // CCSRBAR 1M
ranges = <0x0 0xe0000000 0x100000>;
reg = <0xe0000000 0x1000>; // CCSRBAR 1M
bus-frequency = <0>; // Filled out by uboot.
memory-controller@2000 {
compatible = "fsl,8544-memory-controller";
reg = <2000 1000>;
reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <12 2>;
interrupts = <18 2>;
};
l2-cache-controller@20000 {
compatible = "fsl,8544-l2-cache-controller";
reg = <20000 1000>;
cache-line-size = <20>; // 32 bytes
cache-size = <40000>; // L2, 256K
reg = <0x20000 0x1000>;
cache-line-size = <32>; // 32 bytes
cache-size = <0x40000>; // L2, 256K
interrupt-parent = <&mpic>;
interrupts = <10 2>;
interrupts = <16 2>;
};
i2c@3000 {
@ -79,8 +79,8 @@ i2c@3000 {
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
reg = <3000 100>;
interrupts = <2b 2>;
reg = <0x3000 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
};
@ -90,8 +90,8 @@ i2c@3100 {
#size-cells = <0>;
cell-index = <1>;
compatible = "fsl-i2c";
reg = <3100 100>;
interrupts = <2b 2>;
reg = <0x3100 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
};
@ -100,30 +100,71 @@ mdio@24520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
reg = <24520 20>;
reg = <0x24520 0x20>;
phy0: ethernet-phy@0 {
interrupt-parent = <&mpic>;
interrupts = <a 1>;
reg = <0>;
interrupts = <10 1>;
reg = <0x0>;
device_type = "ethernet-phy";
};
phy1: ethernet-phy@1 {
interrupt-parent = <&mpic>;
interrupts = <a 1>;
reg = <1>;
interrupts = <10 1>;
reg = <0x1>;
device_type = "ethernet-phy";
};
};
dma@21300 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8544-dma", "fsl,eloplus-dma";
reg = <0x21300 0x4>;
ranges = <0x0 0x21100 0x200>;
cell-index = <0>;
dma-channel@0 {
compatible = "fsl,mpc8544-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x0 0x80>;
cell-index = <0>;
interrupt-parent = <&mpic>;
interrupts = <20 2>;
};
dma-channel@80 {
compatible = "fsl,mpc8544-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupt-parent = <&mpic>;
interrupts = <21 2>;
};
dma-channel@100 {
compatible = "fsl,mpc8544-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupt-parent = <&mpic>;
interrupts = <22 2>;
};
dma-channel@180 {
compatible = "fsl,mpc8544-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x180 0x80>;
cell-index = <3>;
interrupt-parent = <&mpic>;
interrupts = <23 2>;
};
};
enet0: ethernet@24000 {
cell-index = <0>;
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <24000 1000>;
reg = <0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <1d 2 1e 2 22 2>;
interrupts = <29 2 30 2 34 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy0>;
phy-connection-type = "rgmii-id";
@ -134,9 +175,9 @@ enet1: ethernet@26000 {
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <26000 1000>;
reg = <0x26000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <1f 2 20 2 21 2>;
interrupts = <31 2 32 2 33 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy1>;
phy-connection-type = "rgmii-id";
@ -146,9 +187,9 @@ serial0: serial@4500 {
cell-index = <0>;
device_type = "serial";
compatible = "ns16550";
reg = <4500 100>;
reg = <0x4500 0x100>;
clock-frequency = <0>;
interrupts = <2a 2>;
interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
@ -156,15 +197,15 @@ serial1: serial@4600 {
cell-index = <1>;
device_type = "serial";
compatible = "ns16550";
reg = <4600 100>;
reg = <0x4600 0x100>;
clock-frequency = <0>;
interrupts = <2a 2>;
interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
global-utilities@e0000 { //global utilities block
compatible = "fsl,mpc8548-guts";
reg = <e0000 1000>;
reg = <0xe0000 0x1000>;
fsl,has-rstcr;
};
@ -173,7 +214,7 @@ mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <40000 40000>;
reg = <0x40000 0x40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
@ -184,32 +225,32 @@ pci0: pci@e0008000 {
cell-index = <0>;
compatible = "fsl,mpc8540-pci";
device_type = "pci";
interrupt-map-mask = <f800 0 0 7>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x11 J17 Slot 1 */
8800 0 0 1 &mpic 2 1
8800 0 0 2 &mpic 3 1
8800 0 0 3 &mpic 4 1
8800 0 0 4 &mpic 1 1
0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x12 J16 Slot 2 */
9000 0 0 1 &mpic 3 1
9000 0 0 2 &mpic 4 1
9000 0 0 3 &mpic 2 1
9000 0 0 4 &mpic 1 1>;
0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
0x9000 0x0 0x0 0x4 &mpic 0x1 0x1>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
bus-range = <0 ff>;
ranges = <02000000 0 c0000000 c0000000 0 20000000
01000000 0 00000000 e1000000 0 00010000>;
clock-frequency = <3f940aa>;
interrupts = <24 2>;
bus-range = <0 255>;
ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
0x1000000 0x0 0x0 0xe1000000 0x0 0x10000>;
clock-frequency = <66666666>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <e0008000 1000>;
reg = <0xe0008000 0x1000>;
};
pci1: pcie@e0009000 {
@ -219,33 +260,33 @@ pci1: pcie@e0009000 {
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <e0009000 1000>;
bus-range = <0 ff>;
ranges = <02000000 0 80000000 80000000 0 20000000
01000000 0 00000000 e1010000 0 00010000>;
clock-frequency = <1fca055>;
reg = <0xe0009000 0x1000>;
bus-range = <0 255>;
ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
0x1000000 0x0 0x0 0xe1010000 0x0 0x10000>;
clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
interrupts = <1a 2>;
interrupt-map-mask = <f800 0 0 7>;
interrupts = <26 2>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x0 */
0000 0 0 1 &mpic 4 1
0000 0 0 2 &mpic 5 1
0000 0 0 3 &mpic 6 1
0000 0 0 4 &mpic 7 1
0000 0x0 0x0 0x1 &mpic 0x4 0x1
0000 0x0 0x0 0x2 &mpic 0x5 0x1
0000 0x0 0x0 0x3 &mpic 0x6 0x1
0000 0x0 0x0 0x4 &mpic 0x7 0x1
>;
pcie@0 {
reg = <0 0 0 0 0>;
reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <02000000 0 80000000
02000000 0 80000000
0 20000000
ranges = <0x2000000 0x0 0x80000000
0x2000000 0x0 0x80000000
0x0 0x20000000
01000000 0 00000000
01000000 0 00000000
0 00010000>;
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x10000>;
};
};
@ -256,33 +297,33 @@ pci2: pcie@e000a000 {
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <e000a000 1000>;
bus-range = <0 ff>;
ranges = <02000000 0 a0000000 a0000000 0 10000000
01000000 0 00000000 e1020000 0 00010000>;
clock-frequency = <1fca055>;
reg = <0xe000a000 0x1000>;
bus-range = <0 255>;
ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
0x1000000 0x0 0x0 0xe1020000 0x0 0x10000>;
clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
interrupts = <19 2>;
interrupt-map-mask = <f800 0 0 7>;
interrupts = <25 2>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x0 */
0000 0 0 1 &mpic 0 1
0000 0 0 2 &mpic 1 1
0000 0 0 3 &mpic 2 1
0000 0 0 4 &mpic 3 1
0000 0x0 0x0 0x1 &mpic 0x0 0x1
0000 0x0 0x0 0x2 &mpic 0x1 0x1
0000 0x0 0x0 0x3 &mpic 0x2 0x1
0000 0x0 0x0 0x4 &mpic 0x3 0x1
>;
pcie@0 {
reg = <0 0 0 0 0>;
reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <02000000 0 a0000000
02000000 0 a0000000
0 10000000
ranges = <0x2000000 0x0 0xa0000000
0x2000000 0x0 0xa0000000
0x0 0x10000000
01000000 0 00000000
01000000 0 00000000
0 00010000>;
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x10000>;
};
};
@ -293,72 +334,72 @@ pci3: pcie@e000b000 {
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <e000b000 1000>;
bus-range = <0 ff>;
ranges = <02000000 0 b0000000 b0000000 0 00100000
01000000 0 00000000 b0100000 0 00100000>;
clock-frequency = <1fca055>;
reg = <0xe000b000 0x1000>;
bus-range = <0 255>;
ranges = <0x2000000 0x0 0xb0000000 0xb0000000 0x0 0x100000
0x1000000 0x0 0x0 0xb0100000 0x0 0x100000>;
clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
interrupts = <1b 2>;
interrupt-map-mask = <ff00 0 0 1>;
interrupts = <27 2>;
interrupt-map-mask = <0xff00 0x0 0x0 0x1>;
interrupt-map = <
// IDSEL 0x1c USB
e000 0 0 1 &i8259 c 2
e100 0 0 2 &i8259 9 2
e200 0 0 3 &i8259 a 2
e300 0 0 4 &i8259 b 2
0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
// IDSEL 0x1d Audio
e800 0 0 1 &i8259 6 2
0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
// IDSEL 0x1e Legacy
f000 0 0 1 &i8259 7 2
f100 0 0 1 &i8259 7 2
0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
// IDSEL 0x1f IDE/SATA
f800 0 0 1 &i8259 e 2
f900 0 0 1 &i8259 5 2
0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
>;
pcie@0 {
reg = <0 0 0 0 0>;
reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <02000000 0 b0000000
02000000 0 b0000000
0 00100000
ranges = <0x2000000 0x0 0xb0000000
0x2000000 0x0 0xb0000000
0x0 0x100000
01000000 0 00000000
01000000 0 00000000
0 00100000>;
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
uli1575@0 {
reg = <0 0 0 0 0>;
reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
#address-cells = <3>;
ranges = <02000000 0 b0000000
02000000 0 b0000000
0 00100000
ranges = <0x2000000 0x0 0xb0000000
0x2000000 0x0 0xb0000000
0x0 0x100000
01000000 0 00000000
01000000 0 00000000
0 00100000>;
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
isa@1e {
device_type = "isa";
#interrupt-cells = <2>;
#size-cells = <1>;
#address-cells = <2>;
reg = <f000 0 0 0 0>;
ranges = <1 0
01000000 0 0
00001000>;
reg = <0xf000 0x0 0x0 0x0 0x0>;
ranges = <0x1 0x0
0x1000000 0x0 0x0
0x1000>;
interrupt-parent = <&i8259>;
i8259: interrupt-controller@20 {
reg = <1 20 2
1 a0 2
1 4d0 2>;
reg = <0x1 0x20 0x2
0x1 0xa0 0x2
0x1 0x4d0 0x2>;
interrupt-controller;
device_type = "interrupt-controller";
#address-cells = <0>;
@ -371,28 +412,28 @@ i8259: interrupt-controller@20 {
i8042@60 {
#size-cells = <0>;
#address-cells = <1>;
reg = <1 60 1 1 64 1>;
interrupts = <1 3 c 3>;
reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
interrupts = <1 3 12 3>;
interrupt-parent = <&i8259>;
keyboard@0 {
reg = <0>;
reg = <0x0>;
compatible = "pnpPNP,303";
};
mouse@1 {
reg = <1>;
reg = <0x1>;
compatible = "pnpPNP,f03";
};
};
rtc@70 {
compatible = "pnpPNP,b00";
reg = <1 70 2>;
reg = <0x1 0x70 0x2>;
};
gpio@400 {
reg = <1 400 80>;
reg = <0x1 0x400 0x80>;
};
};
};

289
arch/powerpc/boot/dts/mpc8548cds.dts
View File

@ -1,7 +1,7 @@
/*
* MPC8548 CDS Device Tree Source
*
* Copyright 2006 Freescale Semiconductor Inc.
* Copyright 2006, 2008 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@ -9,6 +9,7 @@
* option) any later version.
*/
/dts-v1/;
/ {
model = "MPC8548CDS";
@ -36,11 +37,11 @@ cpus {
PowerPC,8548@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <20>; // 32 bytes
i-cache-line-size = <20>; // 32 bytes
d-cache-size = <8000>; // L1, 32K
i-cache-size = <8000>; // L1, 32K
reg = <0x0>;
d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <32>; // 32 bytes
d-cache-size = <0x8000>; // L1, 32K
i-cache-size = <0x8000>; // L1, 32K
timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // 166 MHz
clock-frequency = <0>; // 825 MHz, from uboot
@ -49,31 +50,31 @@ PowerPC,8548@0 {
memory {
device_type = "memory";
reg = <00000000 08000000>; // 128M at 0x0
reg = <0x0 0x8000000>; // 128M at 0x0
};
soc8548@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
ranges = <00000000 e0000000 00100000>;
reg = <e0000000 00001000>; // CCSRBAR
ranges = <0x0 0xe0000000 0x100000>;
reg = <0xe0000000 0x1000>; // CCSRBAR
bus-frequency = <0>;
memory-controller@2000 {
compatible = "fsl,8548-memory-controller";
reg = <2000 1000>;
reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <12 2>;
interrupts = <18 2>;
};
l2-cache-controller@20000 {
compatible = "fsl,8548-l2-cache-controller";
reg = <20000 1000>;
cache-line-size = <20>; // 32 bytes
cache-size = <80000>; // L2, 512K
reg = <0x20000 0x1000>;
cache-line-size = <32>; // 32 bytes
cache-size = <0x80000>; // L2, 512K
interrupt-parent = <&mpic>;
interrupts = <10 2>;
interrupts = <16 2>;
};
i2c@3000 {
@ -81,8 +82,8 @@ i2c@3000 {
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
reg = <3000 100>;
interrupts = <2b 2>;
reg = <0x3000 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
};
@ -92,8 +93,8 @@ i2c@3100 {
#size-cells = <0>;
cell-index = <1>;
compatible = "fsl-i2c";
reg = <3100 100>;
interrupts = <2b 2>;
reg = <0x3100 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
};
@ -102,30 +103,30 @@ mdio@24520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
reg = <24520 20>;
reg = <0x24520 0x20>;
phy0: ethernet-phy@0 {
interrupt-parent = <&mpic>;
interrupts = <5 1>;
reg = <0>;
reg = <0x0>;
device_type = "ethernet-phy";
};
phy1: ethernet-phy@1 {
interrupt-parent = <&mpic>;
interrupts = <5 1>;
reg = <1>;
reg = <0x1>;
device_type = "ethernet-phy";
};
phy2: ethernet-phy@2 {
interrupt-parent = <&mpic>;
interrupts = <5 1>;
reg = <2>;
reg = <0x2>;
device_type = "ethernet-phy";
};
phy3: ethernet-phy@3 {
interrupt-parent = <&mpic>;
interrupts = <5 1>;
reg = <3>;
reg = <0x3>;
device_type = "ethernet-phy";
};
};
@ -135,9 +136,9 @@ enet0: ethernet@24000 {
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <24000 1000>;
reg = <0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <1d 2 1e 2 22 2>;
interrupts = <29 2 30 2 34 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy0>;
};
@ -147,9 +148,9 @@ enet1: ethernet@25000 {
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <25000 1000>;
reg = <0x25000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <23 2 24 2 28 2>;
interrupts = <35 2 36 2 40 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy1>;
};
@ -160,9 +161,9 @@ enet2: ethernet@26000 {
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <26000 1000>;
reg = <0x26000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <1f 2 20 2 21 2>;
interrupts = <31 2 32 2 33 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy2>;
};
@ -172,9 +173,9 @@ enet3: ethernet@27000 {
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <27000 1000>;
reg = <0x27000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <25 2 26 2 27 2>;
interrupts = <37 2 38 2 39 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy3>;
};
@ -184,9 +185,9 @@ serial0: serial@4500 {
cell-index = <0>;
device_type = "serial";
compatible = "ns16550";
reg = <4500 100>; // reg base, size
reg = <0x4500 0x100>; // reg base, size
clock-frequency = <0>; // should we fill in in uboot?
interrupts = <2a 2>;
interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
@ -194,15 +195,15 @@ serial1: serial@4600 {
cell-index = <1>;
device_type = "serial";
compatible = "ns16550";
reg = <4600 100>; // reg base, size
reg = <0x4600 0x100>; // reg base, size
clock-frequency = <0>; // should we fill in in uboot?
interrupts = <2a 2>;
interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
global-utilities@e0000 { //global utilities reg
compatible = "fsl,mpc8548-guts";
reg = <e0000 1000>;
reg = <0xe0000 0x1000>;
fsl,has-rstcr;
};
@ -211,7 +212,7 @@ mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <40000 40000>;
reg = <0x40000 0x40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
@ -220,139 +221,139 @@ mpic: pic@40000 {
pci0: pci@e0008000 {
cell-index = <0>;
interrupt-map-mask = <f800 0 0 7>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x4 (PCIX Slot 2) */
02000 0 0 1 &mpic 0 1
02000 0 0 2 &mpic 1 1
02000 0 0 3 &mpic 2 1
02000 0 0 4 &mpic 3 1
0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
0x2000 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 0x5 (PCIX Slot 3) */
02800 0 0 1 &mpic 1 1
02800 0 0 2 &mpic 2 1
02800 0 0 3 &mpic 3 1
02800 0 0 4 &mpic 0 1
0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
0x2800 0x0 0x0 0x2 &mpic 0x2 0x1
0x2800 0x0 0x0 0x3 &mpic 0x3 0x1
0x2800 0x0 0x0 0x4 &mpic 0x0 0x1
/* IDSEL 0x6 (PCIX Slot 4) */
03000 0 0 1 &mpic 2 1
03000 0 0 2 &mpic 3 1
03000 0 0 3 &mpic 0 1
03000 0 0 4 &mpic 1 1
0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
0x3000 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x8 (PCIX Slot 5) */
04000 0 0 1 &mpic 0 1
04000 0 0 2 &mpic 1 1
04000 0 0 3 &mpic 2 1
04000 0 0 4 &mpic 3 1
0x4000 0x0 0x0 0x1 &mpic 0x0 0x1
0x4000 0x0 0x0 0x2 &mpic 0x1 0x1
0x4000 0x0 0x0 0x3 &mpic 0x2 0x1
0x4000 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 0xC (Tsi310 bridge) */
06000 0 0 1 &mpic 0 1
06000 0 0 2 &mpic 1 1
06000 0 0 3 &mpic 2 1
06000 0 0 4 &mpic 3 1
0x6000 0x0 0x0 0x1 &mpic 0x0 0x1
0x6000 0x0 0x0 0x2 &mpic 0x1 0x1
0x6000 0x0 0x0 0x3 &mpic 0x2 0x1
0x6000 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 0x14 (Slot 2) */
0a000 0 0 1 &mpic 0 1
0a000 0 0 2 &mpic 1 1
0a000 0 0 3 &mpic 2 1
0a000 0 0 4 &mpic 3 1
0xa000 0x0 0x0 0x1 &mpic 0x0 0x1
0xa000 0x0 0x0 0x2 &mpic 0x1 0x1
0xa000 0x0 0x0 0x3 &mpic 0x2 0x1
0xa000 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 0x15 (Slot 3) */
0a800 0 0 1 &mpic 1 1
0a800 0 0 2 &mpic 2 1
0a800 0 0 3 &mpic 3 1
0a800 0 0 4 &mpic 0 1
0xa800 0x0 0x0 0x1 &mpic 0x1 0x1
0xa800 0x0 0x0 0x2 &mpic 0x2 0x1
0xa800 0x0 0x0 0x3 &mpic 0x3 0x1
0xa800 0x0 0x0 0x4 &mpic 0x0 0x1
/* IDSEL 0x16 (Slot 4) */
0b000 0 0 1 &mpic 2 1
0b000 0 0 2 &mpic 3 1
0b000 0 0 3 &mpic 0 1
0b000 0 0 4 &mpic 1 1
0xb000 0x0 0x0 0x1 &mpic 0x2 0x1
0xb000 0x0 0x0 0x2 &mpic 0x3 0x1
0xb000 0x0 0x0 0x3 &mpic 0x0 0x1
0xb000 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x18 (Slot 5) */
0c000 0 0 1 &mpic 0 1
0c000 0 0 2 &mpic 1 1
0c000 0 0 3 &mpic 2 1
0c000 0 0 4 &mpic 3 1
0xc000 0x0 0x0 0x1 &mpic 0x0 0x1
0xc000 0x0 0x0 0x2 &mpic 0x1 0x1
0xc000 0x0 0x0 0x3 &mpic 0x2 0x1
0xc000 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 0x1C (Tsi310 bridge PCI primary) */
0E000 0 0 1 &mpic 0 1
0E000 0 0 2 &mpic 1 1
0E000 0 0 3 &mpic 2 1
0E000 0 0 4 &mpic 3 1>;
0xe000 0x0 0x0 0x1 &mpic 0x0 0x1
0xe000 0x0 0x0 0x2 &mpic 0x1 0x1
0xe000 0x0 0x0 0x3 &mpic 0x2 0x1
0xe000 0x0 0x0 0x4 &mpic 0x3 0x1>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
interrupts = <24 2>;
bus-range = <0 0>;
ranges = <02000000 0 80000000 80000000 0 10000000
01000000 0 00000000 e2000000 0 00800000>;
clock-frequency = <3f940aa>;
ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x10000000
0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
clock-frequency = <66666666>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <e0008000 1000>;
reg = <0xe0008000 0x1000>;
compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
device_type = "pci";
pci_bridge@1c {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x00 (PrPMC Site) */
0000 0 0 1 &mpic 0 1
0000 0 0 2 &mpic 1 1
0000 0 0 3 &mpic 2 1
0000 0 0 4 &mpic 3 1
0000 0x0 0x0 0x1 &mpic 0x0 0x1
0000 0x0 0x0 0x2 &mpic 0x1 0x1
0000 0x0 0x0 0x3 &mpic 0x2 0x1
0000 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 0x04 (VIA chip) */
2000 0 0 1 &mpic 0 1
2000 0 0 2 &mpic 1 1
2000 0 0 3 &mpic 2 1
2000 0 0 4 &mpic 3 1
0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
0x2000 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 0x05 (8139) */
2800 0 0 1 &mpic 1 1
0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
/* IDSEL 0x06 (Slot 6) */
3000 0 0 1 &mpic 2 1
3000 0 0 2 &mpic 3 1
3000 0 0 3 &mpic 0 1
3000 0 0 4 &mpic 1 1
0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
0x3000 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDESL 0x07 (Slot 7) */
3800 0 0 1 &mpic 3 1
3800 0 0 2 &mpic 0 1
3800 0 0 3 &mpic 1 1
3800 0 0 4 &mpic 2 1>;
0x3800 0x0 0x0 0x1 &mpic 0x3 0x1
0x3800 0x0 0x0 0x2 &mpic 0x0 0x1
0x3800 0x0 0x0 0x3 &mpic 0x1 0x1
0x3800 0x0 0x0 0x4 &mpic 0x2 0x1>;
reg = <e000 0 0 0 0>;
reg = <0xe000 0x0 0x0 0x0 0x0>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
ranges = <02000000 0 80000000
02000000 0 80000000
0 20000000
01000000 0 00000000
01000000 0 00000000
0 00080000>;
clock-frequency = <1fca055>;
ranges = <0x2000000 0x0 0x80000000
0x2000000 0x0 0x80000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x80000>;
clock-frequency = <33333333>;
isa@4 {
device_type = "isa";
#interrupt-cells = <2>;
#size-cells = <1>;
#address-cells = <2>;
reg = <2000 0 0 0 0>;
ranges = <1 0 01000000 0 0 00001000>;
reg = <0x2000 0x0 0x0 0x0 0x0>;
ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>;
interrupt-parent = <&i8259>;
i8259: interrupt-controller@20 {
interrupt-controller;
device_type = "interrupt-controller";
reg = <1 20 2
1 a0 2
1 4d0 2>;
reg = <0x1 0x20 0x2
0x1 0xa0 0x2
0x1 0x4d0 0x2>;
#address-cells = <0>;
#interrupt-cells = <2>;
compatible = "chrp,iic";
@ -362,7 +363,7 @@ i8259: interrupt-controller@20 {
rtc@70 {
compatible = "pnpPNP,b00";
reg = <1 70 2>;
reg = <0x1 0x70 0x2>;
};
};
};
@ -370,64 +371,64 @@ rtc@70 {
pci1: pci@e0009000 {
cell-index = <1>;
interrupt-map-mask = <f800 0 0 7>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x15 */
a800 0 0 1 &mpic b 1
a800 0 0 2 &mpic 1 1
a800 0 0 3 &mpic 2 1
a800 0 0 4 &mpic 3 1>;
0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
0xa800 0x0 0x0 0x2 &mpic 0x1 0x1
0xa800 0x0 0x0 0x3 &mpic 0x2 0x1
0xa800 0x0 0x0 0x4 &mpic 0x3 0x1>;
interrupt-parent = <&mpic>;
interrupts = <19 2>;
interrupts = <25 2>;
bus-range = <0 0>;
ranges = <02000000 0 90000000 90000000 0 10000000
01000000 0 00000000 e2800000 0 00800000>;
clock-frequency = <3f940aa>;
ranges = <0x2000000 0x0 0x90000000 0x90000000 0x0 0x10000000
0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
clock-frequency = <66666666>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <e0009000 1000>;
reg = <0xe0009000 0x1000>;
compatible = "fsl,mpc8540-pci";
device_type = "pci";
};
pci2: pcie@e000a000 {
cell-index = <2>;
interrupt-map-mask = <f800 0 0 7>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x0 (PEX) */
00000 0 0 1 &mpic 0 1
00000 0 0 2 &mpic 1 1
00000 0 0 3 &mpic 2 1
00000 0 0 4 &mpic 3 1>;
00000 0x0 0x0 0x1 &mpic 0x0 0x1
00000 0x0 0x0 0x2 &mpic 0x1 0x1
00000 0x0 0x0 0x3 &mpic 0x2 0x1
00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
interrupt-parent = <&mpic>;
interrupts = <1a 2>;
bus-range = <0 ff>;
ranges = <02000000 0 a0000000 a0000000 0 20000000
01000000 0 00000000 e3000000 0 08000000>;
clock-frequency = <1fca055>;
interrupts = <26 2>;
bus-range = <0 255>;
ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
0x1000000 0x0 0x0 0xe3000000 0x0 0x8000000>;
clock-frequency = <33333333>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <e000a000 1000>;
reg = <0xe000a000 0x1000>;
compatible = "fsl,mpc8548-pcie";
device_type = "pci";
pcie@0 {
reg = <0 0 0 0 0>;
reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <02000000 0 a0000000
02000000 0 a0000000
0 20000000
ranges = <0x2000000 0x0 0xa0000000
0x2000000 0x0 0xa0000000
0x0 0x20000000
01000000 0 00000000
01000000 0 00000000
0 08000000>;
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x8000000>;
};
};
};

161
arch/powerpc/boot/dts/mpc8555cds.dts
View File

@ -1,7 +1,7 @@
/*
* MPC8555 CDS Device Tree Source
*
* Copyright 2006 Freescale Semiconductor Inc.
* Copyright 2006, 2008 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@ -9,6 +9,7 @@
* option) any later version.
*/
/dts-v1/;
/ {
model = "MPC8555CDS";
@ -31,11 +32,11 @@ cpus {
PowerPC,8555@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <20>; // 32 bytes
i-cache-line-size = <20>; // 32 bytes
d-cache-size = <8000>; // L1, 32K
i-cache-size = <8000>; // L1, 32K
reg = <0x0>;
d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <32>; // 32 bytes
d-cache-size = <0x8000>; // L1, 32K
i-cache-size = <0x8000>; // L1, 32K
timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // 166 MHz
clock-frequency = <0>; // 825 MHz, from uboot
@ -44,31 +45,31 @@ PowerPC,8555@0 {
memory {
device_type = "memory";
reg = <00000000 08000000>; // 128M at 0x0
reg = <0x0 0x8000000>; // 128M at 0x0
};
soc8555@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00001000>; // CCSRBAR 1M
ranges = <0x0 0xe0000000 0x100000>;
reg = <0xe0000000 0x1000>; // CCSRBAR 1M
bus-frequency = <0>;
memory-controller@2000 {
compatible = "fsl,8555-memory-controller";
reg = <2000 1000>;
reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <12 2>;
interrupts = <18 2>;
};
l2-cache-controller@20000 {
compatible = "fsl,8555-l2-cache-controller";
reg = <20000 1000>;
cache-line-size = <20>; // 32 bytes
cache-size = <40000>; // L2, 256K
reg = <0x20000 0x1000>;
cache-line-size = <32>; // 32 bytes
cache-size = <0x40000>; // L2, 256K
interrupt-parent = <&mpic>;
interrupts = <10 2>;
interrupts = <16 2>;
};
i2c@3000 {
@ -76,8 +77,8 @@ i2c@3000 {
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
reg = <3000 100>;
interrupts = <2b 2>;
reg = <0x3000 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
};
@ -86,18 +87,18 @@ mdio@24520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
reg = <24520 20>;
reg = <0x24520 0x20>;
phy0: ethernet-phy@0 {
interrupt-parent = <&mpic>;
interrupts = <5 1>;
reg = <0>;
reg = <0x0>;
device_type = "ethernet-phy";
};
phy1: ethernet-phy@1 {
interrupt-parent = <&mpic>;
interrupts = <5 1>;
reg = <1>;
reg = <0x1>;
device_type = "ethernet-phy";
};
};
@ -107,9 +108,9 @@ enet0: ethernet@24000 {
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <24000 1000>;
reg = <0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <1d 2 1e 2 22 2>;
interrupts = <29 2 30 2 34 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy0>;
};
@ -119,9 +120,9 @@ enet1: ethernet@25000 {
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <25000 1000>;
reg = <0x25000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <23 2 24 2 28 2>;
interrupts = <35 2 36 2 40 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy1>;
};
@ -130,9 +131,9 @@ serial0: serial@4500 {
cell-index = <0>;
device_type = "serial";
compatible = "ns16550";
reg = <4500 100>; // reg base, size
reg = <0x4500 0x100>; // reg base, size
clock-frequency = <0>; // should we fill in in uboot?
interrupts = <2a 2>;
interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
@ -140,9 +141,9 @@ serial1: serial@4600 {
cell-index = <1>;
device_type = "serial";
compatible = "ns16550";
reg = <4600 100>; // reg base, size
reg = <0x4600 0x100>; // reg base, size
clock-frequency = <0>; // should we fill in in uboot?
interrupts = <2a 2>;
interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
@ -151,7 +152,7 @@ mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <40000 40000>;
reg = <0x40000 0x40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
@ -161,17 +162,17 @@ cpm@919c0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8555-cpm", "fsl,cpm2";
reg = <919c0 30>;
reg = <0x919c0 0x30>;
ranges;
muram@80000 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 80000 10000>;
ranges = <0x0 0x80000 0x10000>;
data@0 {
compatible = "fsl,cpm-muram-data";
reg = <0 2000 9000 1000>;
reg = <0x0 0x2000 0x9000 0x1000>;
};
};
@ -179,16 +180,16 @@ brg@919f0 {
compatible = "fsl,mpc8555-brg",
"fsl,cpm2-brg",
"fsl,cpm-brg";
reg = <919f0 10 915f0 10>;
reg = <0x919f0 0x10 0x915f0 0x10>;
};
cpmpic: pic@90c00 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
interrupts = <2e 2>;
interrupts = <46 2>;
interrupt-parent = <&mpic>;
reg = <90c00 80>;
reg = <0x90c00 0x80>;
compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic";
};
};
@ -196,68 +197,68 @@ cpmpic: pic@90c00 {
pci0: pci@e0008000 {
cell-index = <0>;
interrupt-map-mask = <1f800 0 0 7>;
interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x10 */
08000 0 0 1 &mpic 0 1
08000 0 0 2 &mpic 1 1
08000 0 0 3 &mpic 2 1
08000 0 0 4 &mpic 3 1
0x8000 0x0 0x0 0x1 &mpic 0x0 0x1
0x8000 0x0 0x0 0x2 &mpic 0x1 0x1
0x8000 0x0 0x0 0x3 &mpic 0x2 0x1
0x8000 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 0x11 */
08800 0 0 1 &mpic 0 1
08800 0 0 2 &mpic 1 1
08800 0 0 3 &mpic 2 1
08800 0 0 4 &mpic 3 1
0x8800 0x0 0x0 0x1 &mpic 0x0 0x1
0x8800 0x0 0x0 0x2 &mpic 0x1 0x1
0x8800 0x0 0x0 0x3 &mpic 0x2 0x1
0x8800 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 0x12 (Slot 1) */
09000 0 0 1 &mpic 0 1
09000 0 0 2 &mpic 1 1
09000 0 0 3 &mpic 2 1
09000 0 0 4 &mpic 3 1
0x9000 0x0 0x0 0x1 &mpic 0x0 0x1
0x9000 0x0 0x0 0x2 &mpic 0x1 0x1
0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
0x9000 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 0x13 (Slot 2) */
09800 0 0 1 &mpic 1 1
09800 0 0 2 &mpic 2 1
09800 0 0 3 &mpic 3 1
09800 0 0 4 &mpic 0 1
0x9800 0x0 0x0 0x1 &mpic 0x1 0x1
0x9800 0x0 0x0 0x2 &mpic 0x2 0x1
0x9800 0x0 0x0 0x3 &mpic 0x3 0x1
0x9800 0x0 0x0 0x4 &mpic 0x0 0x1
/* IDSEL 0x14 (Slot 3) */
0a000 0 0 1 &mpic 2 1
0a000 0 0 2 &mpic 3 1
0a000 0 0 3 &mpic 0 1
0a000 0 0 4 &mpic 1 1
0xa000 0x0 0x0 0x1 &mpic 0x2 0x1
0xa000 0x0 0x0 0x2 &mpic 0x3 0x1
0xa000 0x0 0x0 0x3 &mpic 0x0 0x1
0xa000 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x15 (Slot 4) */
0a800 0 0 1 &mpic 3 1
0a800 0 0 2 &mpic 0 1
0a800 0 0 3 &mpic 1 1
0a800 0 0 4 &mpic 2 1
0xa800 0x0 0x0 0x1 &mpic 0x3 0x1
0xa800 0x0 0x0 0x2 &mpic 0x0 0x1
0xa800 0x0 0x0 0x3 &mpic 0x1 0x1
0xa800 0x0 0x0 0x4 &mpic 0x2 0x1
/* Bus 1 (Tundra Bridge) */
/* IDSEL 0x12 (ISA bridge) */
19000 0 0 1 &mpic 0 1
19000 0 0 2 &mpic 1 1
19000 0 0 3 &mpic 2 1
19000 0 0 4 &mpic 3 1>;
0x19000 0x0 0x0 0x1 &mpic 0x0 0x1
0x19000 0x0 0x0 0x2 &mpic 0x1 0x1
0x19000 0x0 0x0 0x3 &mpic 0x2 0x1
0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
interrupts = <24 2>;
bus-range = <0 0>;
ranges = <02000000 0 80000000 80000000 0 20000000
01000000 0 00000000 e2000000 0 00100000>;
clock-frequency = <3f940aa>;
ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
clock-frequency = <66666666>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <e0008000 1000>;
reg = <0xe0008000 0x1000>;
compatible = "fsl,mpc8540-pci";
device_type = "pci";
i8259@19000 {
interrupt-controller;
device_type = "interrupt-controller";
reg = <19000 0 0 0 1>;
reg = <0x19000 0x0 0x0 0x0 0x1>;
#address-cells = <0>;
#interrupt-cells = <2>;
compatible = "chrp,iic";
@ -268,24 +269,24 @@ i8259@19000 {
pci1: pci@e0009000 {
cell-index = <1>;
interrupt-map-mask = <f800 0 0 7>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x15 */
a800 0 0 1 &mpic b 1
a800 0 0 2 &mpic b 1
a800 0 0 3 &mpic b 1
a800 0 0 4 &mpic b 1>;
0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
0xa800 0x0 0x0 0x2 &mpic 0xb 0x1
0xa800 0x0 0x0 0x3 &mpic 0xb 0x1
0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>;
interrupt-parent = <&mpic>;
interrupts = <19 2>;
interrupts = <25 2>;
bus-range = <0 0>;
ranges = <02000000 0 a0000000 a0000000 0 20000000
01000000 0 00000000 e3000000 0 00100000>;
clock-frequency = <3f940aa>;
ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
clock-frequency = <66666666>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <e0009000 1000>;
reg = <0xe0009000 0x1000>;
compatible = "fsl,mpc8540-pci";
device_type = "pci";
};

209
arch/powerpc/boot/dts/mpc8560ads.dts
View File

@ -1,7 +1,7 @@
/*
* MPC8560 ADS Device Tree Source
*
* Copyright 2006 Freescale Semiconductor Inc.
* Copyright 2006, 2008 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@ -9,6 +9,7 @@
* option) any later version.
*/
/dts-v1/;
/ {
model = "MPC8560ADS";
@ -32,74 +33,74 @@ cpus {
PowerPC,8560@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <20>; // 32 bytes
i-cache-line-size = <20>; // 32 bytes
d-cache-size = <8000>; // L1, 32K
i-cache-size = <8000>; // L1, 32K
timebase-frequency = <04ead9a0>;
bus-frequency = <13ab6680>;
clock-frequency = <312c8040>;
reg = <0x0>;
d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <32>; // 32 bytes
d-cache-size = <0x8000>; // L1, 32K
i-cache-size = <0x8000>; // L1, 32K
timebase-frequency = <82500000>;
bus-frequency = <330000000>;
clock-frequency = <825000000>;
};
};
memory {
device_type = "memory";
reg = <00000000 10000000>;
reg = <0x0 0x10000000>;
};
soc8560@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
bus-frequency = <13ab6680>;
ranges = <0x0 0xe0000000 0x100000>;
reg = <0xe0000000 0x200>;
bus-frequency = <330000000>;
memory-controller@2000 {
compatible = "fsl,8540-memory-controller";
reg = <2000 1000>;
reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <12 2>;
interrupts = <18 2>;
};
l2-cache-controller@20000 {
compatible = "fsl,8540-l2-cache-controller";
reg = <20000 1000>;
cache-line-size = <20>; // 32 bytes
cache-size = <40000>; // L2, 256K
reg = <0x20000 0x1000>;
cache-line-size = <32>; // 32 bytes
cache-size = <0x40000>; // L2, 256K
interrupt-parent = <&mpic>;
interrupts = <10 2>;
interrupts = <16 2>;
};
mdio@24520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
reg = <24520 20>;
reg = <0x24520 0x20>;
phy0: ethernet-phy@0 {
interrupt-parent = <&mpic>;
interrupts = <5 1>;
reg = <0>;
reg = <0x0>;
device_type = "ethernet-phy";
};
phy1: ethernet-phy@1 {
interrupt-parent = <&mpic>;
interrupts = <5 1>;
reg = <1>;
reg = <0x1>;
device_type = "ethernet-phy";
};
phy2: ethernet-phy@2 {
interrupt-parent = <&mpic>;
interrupts = <7 1>;
reg = <2>;
reg = <0x2>;
device_type = "ethernet-phy";
};
phy3: ethernet-phy@3 {
interrupt-parent = <&mpic>;
interrupts = <7 1>;
reg = <3>;
reg = <0x3>;
device_type = "ethernet-phy";
};
};
@ -109,9 +110,9 @@ enet0: ethernet@24000 {
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <24000 1000>;
reg = <0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <1d 2 1e 2 22 2>;
interrupts = <29 2 30 2 34 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy0>;
};
@ -121,9 +122,9 @@ enet1: ethernet@25000 {
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <25000 1000>;
reg = <0x25000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <23 2 24 2 28 2>;
interrupts = <35 2 36 2 40 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy1>;
};
@ -132,7 +133,7 @@ mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <40000 40000>;
reg = <0x40000 0x40000>;
device_type = "open-pic";
};
@ -140,17 +141,17 @@ cpm@919c0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8560-cpm", "fsl,cpm2";
reg = <919c0 30>;
reg = <0x919c0 0x30>;
ranges;
muram@80000 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 80000 10000>;
ranges = <0x0 0x80000 0x10000>;
data@0 {
compatible = "fsl,cpm-muram-data";
reg = <0 4000 9000 2000>;
reg = <0x0 0x4000 0x9000 0x2000>;
};
};
@ -158,17 +159,17 @@ brg@919f0 {
compatible = "fsl,mpc8560-brg",
"fsl,cpm2-brg",
"fsl,cpm-brg";
reg = <919f0 10 915f0 10>;
clock-frequency = <d#165000000>;
reg = <0x919f0 0x10 0x915f0 0x10>;
clock-frequency = <165000000>;
};
cpmpic: pic@90c00 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
interrupts = <2e 2>;
interrupts = <46 2>;
interrupt-parent = <&mpic>;
reg = <90c00 80>;
reg = <0x90c00 0x80>;
compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
};
@ -176,11 +177,11 @@ serial0: serial@91a00 {
device_type = "serial";
compatible = "fsl,mpc8560-scc-uart",
"fsl,cpm2-scc-uart";
reg = <91a00 20 88000 100>;
reg = <0x91a00 0x20 0x88000 0x100>;
fsl,cpm-brg = <1>;
fsl,cpm-command = <00800000>;
current-speed = <1c200>;
interrupts = <28 8>;
fsl,cpm-command = <0x800000>;
current-speed = <115200>;
interrupts = <40 8>;
interrupt-parent = <&cpmpic>;
};
@ -188,11 +189,11 @@ serial1: serial@91a20 {
device_type = "serial";
compatible = "fsl,mpc8560-scc-uart",
"fsl,cpm2-scc-uart";
reg = <91a20 20 88100 100>;
reg = <0x91a20 0x20 0x88100 0x100>;
fsl,cpm-brg = <2>;
fsl,cpm-command = <04a00000>;
current-speed = <1c200>;
interrupts = <29 8>;
fsl,cpm-command = <0x4a00000>;
current-speed = <115200>;
interrupts = <41 8>;
interrupt-parent = <&cpmpic>;
};
@ -200,10 +201,10 @@ enet2: ethernet@91320 {
device_type = "network";
compatible = "fsl,mpc8560-fcc-enet",
"fsl,cpm2-fcc-enet";
reg = <91320 20 88500 100 913b0 1>;
reg = <0x91320 0x20 0x88500 0x100 0x913b0 0x1>;
local-mac-address = [ 00 00 00 00 00 00 ];
fsl,cpm-command = <16200300>;
interrupts = <21 8>;
fsl,cpm-command = <0x16200300>;
interrupts = <33 8>;
interrupt-parent = <&cpmpic>;
phy-handle = <&phy2>;
};
@ -212,10 +213,10 @@ enet3: ethernet@91340 {
device_type = "network";
compatible = "fsl,mpc8560-fcc-enet",
"fsl,cpm2-fcc-enet";
reg = <91340 20 88600 100 913d0 1>;
reg = <0x91340 0x20 0x88600 0x100 0x913d0 0x1>;
local-mac-address = [ 00 00 00 00 00 00 ];
fsl,cpm-command = <1a400300>;
interrupts = <22 8>;
fsl,cpm-command = <0x1a400300>;
interrupts = <34 8>;
interrupt-parent = <&cpmpic>;
phy-handle = <&phy3>;
};
@ -229,87 +230,87 @@ pci0: pci@e0008000 {
#address-cells = <3>;
compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
device_type = "pci";
reg = <e0008000 1000>;
clock-frequency = <3f940aa>;
interrupt-map-mask = <f800 0 0 7>;
reg = <0xe0008000 0x1000>;
clock-frequency = <66666666>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x2 */
1000 0 0 1 &mpic 1 1
1000 0 0 2 &mpic 2 1
1000 0 0 3 &mpic 3 1
1000 0 0 4 &mpic 4 1
0x1000 0x0 0x0 0x1 &mpic 0x1 0x1
0x1000 0x0 0x0 0x2 &mpic 0x2 0x1
0x1000 0x0 0x0 0x3 &mpic 0x3 0x1
0x1000 0x0 0x0 0x4 &mpic 0x4 0x1
/* IDSEL 0x3 */
1800 0 0 1 &mpic 4 1
1800 0 0 2 &mpic 1 1
1800 0 0 3 &mpic 2 1
1800 0 0 4 &mpic 3 1
0x1800 0x0 0x0 0x1 &mpic 0x4 0x1
0x1800 0x0 0x0 0x2 &mpic 0x1 0x1
0x1800 0x0 0x0 0x3 &mpic 0x2 0x1
0x1800 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 0x4 */
2000 0 0 1 &mpic 3 1
2000 0 0 2 &mpic 4 1
2000 0 0 3 &mpic 1 1
2000 0 0 4 &mpic 2 1
0x2000 0x0 0x0 0x1 &mpic 0x3 0x1
0x2000 0x0 0x0 0x2 &mpic 0x4 0x1
0x2000 0x0 0x0 0x3 &mpic 0x1 0x1
0x2000 0x0 0x0 0x4 &mpic 0x2 0x1
/* IDSEL 0x5 */
2800 0 0 1 &mpic 2 1
2800 0 0 2 &mpic 3 1
2800 0 0 3 &mpic 4 1
2800 0 0 4 &mpic 1 1
0x2800 0x0 0x0 0x1 &mpic 0x2 0x1
0x2800 0x0 0x0 0x2 &mpic 0x3 0x1
0x2800 0x0 0x0 0x3 &mpic 0x4 0x1
0x2800 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 12 */
6000 0 0 1 &mpic 1 1
6000 0 0 2 &mpic 2 1
6000 0 0 3 &mpic 3 1
6000 0 0 4 &mpic 4 1
0x6000 0x0 0x0 0x1 &mpic 0x1 0x1
0x6000 0x0 0x0 0x2 &mpic 0x2 0x1
0x6000 0x0 0x0 0x3 &mpic 0x3 0x1
0x6000 0x0 0x0 0x4 &mpic 0x4 0x1
/* IDSEL 13 */
6800 0 0 1 &mpic 4 1
6800 0 0 2 &mpic 1 1
6800 0 0 3 &mpic 2 1
6800 0 0 4 &mpic 3 1
0x6800 0x0 0x0 0x1 &mpic 0x4 0x1
0x6800 0x0 0x0 0x2 &mpic 0x1 0x1
0x6800 0x0 0x0 0x3 &mpic 0x2 0x1
0x6800 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 14*/
7000 0 0 1 &mpic 3 1
7000 0 0 2 &mpic 4 1
7000 0 0 3 &mpic 1 1
7000 0 0 4 &mpic 2 1
0x7000 0x0 0x0 0x1 &mpic 0x3 0x1
0x7000 0x0 0x0 0x2 &mpic 0x4 0x1
0x7000 0x0 0x0 0x3 &mpic 0x1 0x1
0x7000 0x0 0x0 0x4 &mpic 0x2 0x1
/* IDSEL 15 */
7800 0 0 1 &mpic 2 1
7800 0 0 2 &mpic 3 1
7800 0 0 3 &mpic 4 1
7800 0 0 4 &mpic 1 1
0x7800 0x0 0x0 0x1 &mpic 0x2 0x1
0x7800 0x0 0x0 0x2 &mpic 0x3 0x1
0x7800 0x0 0x0 0x3 &mpic 0x4 0x1
0x7800 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 18 */
9000 0 0 1 &mpic 1 1
9000 0 0 2 &mpic 2 1
9000 0 0 3 &mpic 3 1
9000 0 0 4 &mpic 4 1
0x9000 0x0 0x0 0x1 &mpic 0x1 0x1
0x9000 0x0 0x0 0x2 &mpic 0x2 0x1
0x9000 0x0 0x0 0x3 &mpic 0x3 0x1
0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
/* IDSEL 19 */
9800 0 0 1 &mpic 4 1
9800 0 0 2 &mpic 1 1
9800 0 0 3 &mpic 2 1
9800 0 0 4 &mpic 3 1
0x9800 0x0 0x0 0x1 &mpic 0x4 0x1
0x9800 0x0 0x0 0x2 &mpic 0x1 0x1
0x9800 0x0 0x0 0x3 &mpic 0x2 0x1
0x9800 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 20 */
a000 0 0 1 &mpic 3 1
a000 0 0 2 &mpic 4 1
a000 0 0 3 &mpic 1 1
a000 0 0 4 &mpic 2 1
0xa000 0x0 0x0 0x1 &mpic 0x3 0x1
0xa000 0x0 0x0 0x2 &mpic 0x4 0x1
0xa000 0x0 0x0 0x3 &mpic 0x1 0x1
0xa000 0x0 0x0 0x4 &mpic 0x2 0x1
/* IDSEL 21 */
a800 0 0 1 &mpic 2 1
a800 0 0 2 &mpic 3 1
a800 0 0 3 &mpic 4 1
a800 0 0 4 &mpic 1 1>;
0xa800 0x0 0x0 0x1 &mpic 0x2 0x1
0xa800 0x0 0x0 0x2 &mpic 0x3 0x1
0xa800 0x0 0x0 0x3 &mpic 0x4 0x1
0xa800 0x0 0x0 0x4 &mpic 0x1 0x1>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
interrupts = <24 2>;
bus-range = <0 0>;
ranges = <02000000 0 80000000 80000000 0 20000000
01000000 0 00000000 e2000000 0 01000000>;
ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
0x1000000 0x0 0x0 0xe2000000 0x0 0x1000000>;
};
};

291
arch/powerpc/boot/dts/mpc8568mds.dts
View File

@ -1,7 +1,7 @@
/*
* MPC8568E MDS Device Tree Source
*
* Copyright 2007 Freescale Semiconductor Inc.
* Copyright 2007, 2008 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@ -9,10 +9,7 @@
* option) any later version.
*/
/*
/memreserve/ 00000000 1000000;
*/
/dts-v1/;
/ {
model = "MPC8568EMDS";
@ -37,11 +34,11 @@ cpus {
PowerPC,8568@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <20>; // 32 bytes
i-cache-line-size = <20>; // 32 bytes
d-cache-size = <8000>; // L1, 32K
i-cache-size = <8000>; // L1, 32K
reg = <0x0>;
d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <32>; // 32 bytes
d-cache-size = <0x8000>; // L1, 32K
i-cache-size = <0x8000>; // L1, 32K
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
@ -50,36 +47,36 @@ PowerPC,8568@0 {
memory {
device_type = "memory";
reg = <00000000 10000000>;
reg = <0x0 0x10000000>;
};
bcsr@f8000000 {
device_type = "board-control";
reg = <f8000000 8000>;
reg = <0xf8000000 0x8000>;
};
soc8568@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00001000>;
ranges = <0x0 0xe0000000 0x100000>;
reg = <0xe0000000 0x1000>;
bus-frequency = <0>;
memory-controller@2000 {
compatible = "fsl,8568-memory-controller";
reg = <2000 1000>;
reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <12 2>;
interrupts = <18 2>;
};
l2-cache-controller@20000 {
compatible = "fsl,8568-l2-cache-controller";
reg = <20000 1000>;
cache-line-size = <20>; // 32 bytes
cache-size = <80000>; // L2, 512K
reg = <0x20000 0x1000>;
cache-line-size = <32>; // 32 bytes
cache-size = <0x80000>; // L2, 512K
interrupt-parent = <&mpic>;
interrupts = <10 2>;
interrupts = <16 2>;
};
i2c@3000 {
@ -87,14 +84,14 @@ i2c@3000 {
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
reg = <3000 100>;
interrupts = <2b 2>;
reg = <0x3000 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
rtc@68 {
compatible = "dallas,ds1374";
reg = <68>;
reg = <0x68>;
};
};
@ -103,8 +100,8 @@ i2c@3100 {
#size-cells = <0>;
cell-index = <1>;
compatible = "fsl-i2c";
reg = <3100 100>;
interrupts = <2b 2>;
reg = <0x3100 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
};
@ -113,30 +110,30 @@ mdio@24520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
reg = <24520 20>;
reg = <0x24520 0x20>;
phy0: ethernet-phy@7 {
interrupt-parent = <&mpic>;
interrupts = <1 1>;
reg = <7>;
reg = <0x7>;
device_type = "ethernet-phy";
};
phy1: ethernet-phy@1 {
interrupt-parent = <&mpic>;
interrupts = <2 1>;
reg = <1>;
reg = <0x1>;
device_type = "ethernet-phy";
};
phy2: ethernet-phy@2 {
interrupt-parent = <&mpic>;
interrupts = <1 1>;
reg = <2>;
reg = <0x2>;
device_type = "ethernet-phy";
};
phy3: ethernet-phy@3 {
interrupt-parent = <&mpic>;
interrupts = <2 1>;
reg = <3>;
reg = <0x3>;
device_type = "ethernet-phy";
};
};
@ -146,9 +143,9 @@ enet0: ethernet@24000 {
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <24000 1000>;
reg = <0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <1d 2 1e 2 22 2>;
interrupts = <29 2 30 2 34 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy2>;
};
@ -158,9 +155,9 @@ enet1: ethernet@25000 {
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <25000 1000>;
reg = <0x25000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <23 2 24 2 28 2>;
interrupts = <35 2 36 2 40 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy3>;
};
@ -169,15 +166,15 @@ serial0: serial@4500 {
cell-index = <0>;
device_type = "serial";
compatible = "ns16550";
reg = <4500 100>;
reg = <0x4500 0x100>;
clock-frequency = <0>;
interrupts = <2a 2>;
interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
global-utilities@e0000 { //global utilities block
compatible = "fsl,mpc8548-guts";
reg = <e0000 1000>;
reg = <0xe0000 0x1000>;
fsl,has-rstcr;
};
@ -185,9 +182,9 @@ serial1: serial@4600 {
cell-index = <1>;
device_type = "serial";
compatible = "ns16550";
reg = <4600 100>;
reg = <0x4600 0x100>;
clock-frequency = <0>;
interrupts = <2a 2>;
interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
@ -195,13 +192,13 @@ crypto@30000 {
device_type = "crypto";
model = "SEC2";
compatible = "talitos";
reg = <30000 f000>;
interrupts = <2d 2>;
reg = <0x30000 0xf000>;
interrupts = <45 2>;
interrupt-parent = <&mpic>;
num-channels = <4>;
channel-fifo-len = <18>;
exec-units-mask = <000000fe>;
descriptor-types-mask = <012b0ebf>;
channel-fifo-len = <24>;
exec-units-mask = <0xfe>;
descriptor-types-mask = <0x12b0ebf>;
};
mpic: pic@40000 {
@ -209,73 +206,73 @@ mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <40000 40000>;
reg = <0x40000 0x40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
};
par_io@e0100 {
reg = <e0100 100>;
reg = <0xe0100 0x100>;
device_type = "par_io";
num-ports = <7>;
pio1: ucc_pin@01 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
4 0a 1 0 2 0 /* TxD0 */
4 09 1 0 2 0 /* TxD1 */
4 08 1 0 2 0 /* TxD2 */
4 07 1 0 2 0 /* TxD3 */
4 17 1 0 2 0 /* TxD4 */
4 16 1 0 2 0 /* TxD5 */
4 15 1 0 2 0 /* TxD6 */
4 14 1 0 2 0 /* TxD7 */
4 0f 2 0 2 0 /* RxD0 */
4 0e 2 0 2 0 /* RxD1 */
4 0d 2 0 2 0 /* RxD2 */
4 0c 2 0 2 0 /* RxD3 */
4 1d 2 0 2 0 /* RxD4 */
4 1c 2 0 2 0 /* RxD5 */
4 1b 2 0 2 0 /* RxD6 */
4 1a 2 0 2 0 /* RxD7 */
4 0b 1 0 2 0 /* TX_EN */
4 18 1 0 2 0 /* TX_ER */
4 10 2 0 2 0 /* RX_DV */
4 1e 2 0 2 0 /* RX_ER */
4 11 2 0 2 0 /* RX_CLK */
4 13 1 0 2 0 /* GTX_CLK */
1 1f 2 0 3 0>; /* GTX125 */
0x4 0xa 0x1 0x0 0x2 0x0 /* TxD0 */
0x4 0x9 0x1 0x0 0x2 0x0 /* TxD1 */
0x4 0x8 0x1 0x0 0x2 0x0 /* TxD2 */
0x4 0x7 0x1 0x0 0x2 0x0 /* TxD3 */
0x4 0x17 0x1 0x0 0x2 0x0 /* TxD4 */
0x4 0x16 0x1 0x0 0x2 0x0 /* TxD5 */
0x4 0x15 0x1 0x0 0x2 0x0 /* TxD6 */
0x4 0x14 0x1 0x0 0x2 0x0 /* TxD7 */
0x4 0xf 0x2 0x0 0x2 0x0 /* RxD0 */
0x4 0xe 0x2 0x0 0x2 0x0 /* RxD1 */
0x4 0xd 0x2 0x0 0x2 0x0 /* RxD2 */
0x4 0xc 0x2 0x0 0x2 0x0 /* RxD3 */
0x4 0x1d 0x2 0x0 0x2 0x0 /* RxD4 */
0x4 0x1c 0x2 0x0 0x2 0x0 /* RxD5 */
0x4 0x1b 0x2 0x0 0x2 0x0 /* RxD6 */
0x4 0x1a 0x2 0x0 0x2 0x0 /* RxD7 */
0x4 0xb 0x1 0x0 0x2 0x0 /* TX_EN */
0x4 0x18 0x1 0x0 0x2 0x0 /* TX_ER */
0x4 0x10 0x2 0x0 0x2 0x0 /* RX_DV */
0x4 0x1e 0x2 0x0 0x2 0x0 /* RX_ER */
0x4 0x11 0x2 0x0 0x2 0x0 /* RX_CLK */
0x4 0x13 0x1 0x0 0x2 0x0 /* GTX_CLK */
0x1 0x1f 0x2 0x0 0x3 0x0>; /* GTX125 */
};
pio2: ucc_pin@02 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
5 0a 1 0 2 0 /* TxD0 */
5 09 1 0 2 0 /* TxD1 */
5 08 1 0 2 0 /* TxD2 */
5 07 1 0 2 0 /* TxD3 */
5 17 1 0 2 0 /* TxD4 */
5 16 1 0 2 0 /* TxD5 */
5 15 1 0 2 0 /* TxD6 */
5 14 1 0 2 0 /* TxD7 */
5 0f 2 0 2 0 /* RxD0 */
5 0e 2 0 2 0 /* RxD1 */
5 0d 2 0 2 0 /* RxD2 */
5 0c 2 0 2 0 /* RxD3 */
5 1d 2 0 2 0 /* RxD4 */
5 1c 2 0 2 0 /* RxD5 */
5 1b 2 0 2 0 /* RxD6 */
5 1a 2 0 2 0 /* RxD7 */
5 0b 1 0 2 0 /* TX_EN */
5 18 1 0 2 0 /* TX_ER */
5 10 2 0 2 0 /* RX_DV */
5 1e 2 0 2 0 /* RX_ER */
5 11 2 0 2 0 /* RX_CLK */
5 13 1 0 2 0 /* GTX_CLK */
1 1f 2 0 3 0 /* GTX125 */
4 06 3 0 2 0 /* MDIO */
4 05 1 0 2 0>; /* MDC */
0x5 0xa 0x1 0x0 0x2 0x0 /* TxD0 */
0x5 0x9 0x1 0x0 0x2 0x0 /* TxD1 */
0x5 0x8 0x1 0x0 0x2 0x0 /* TxD2 */
0x5 0x7 0x1 0x0 0x2 0x0 /* TxD3 */
0x5 0x17 0x1 0x0 0x2 0x0 /* TxD4 */
0x5 0x16 0x1 0x0 0x2 0x0 /* TxD5 */
0x5 0x15 0x1 0x0 0x2 0x0 /* TxD6 */
0x5 0x14 0x1 0x0 0x2 0x0 /* TxD7 */
0x5 0xf 0x2 0x0 0x2 0x0 /* RxD0 */
0x5 0xe 0x2 0x0 0x2 0x0 /* RxD1 */
0x5 0xd 0x2 0x0 0x2 0x0 /* RxD2 */
0x5 0xc 0x2 0x0 0x2 0x0 /* RxD3 */
0x5 0x1d 0x2 0x0 0x2 0x0 /* RxD4 */
0x5 0x1c 0x2 0x0 0x2 0x0 /* RxD5 */
0x5 0x1b 0x2 0x0 0x2 0x0 /* RxD6 */
0x5 0x1a 0x2 0x0 0x2 0x0 /* RxD7 */
0x5 0xb 0x1 0x0 0x2 0x0 /* TX_EN */
0x5 0x18 0x1 0x0 0x2 0x0 /* TX_ER */
0x5 0x10 0x2 0x0 0x2 0x0 /* RX_DV */
0x5 0x1e 0x2 0x0 0x2 0x0 /* RX_ER */
0x5 0x11 0x2 0x0 0x2 0x0 /* RX_CLK */
0x5 0x13 0x1 0x0 0x2 0x0 /* GTX_CLK */
0x1 0x1f 0x2 0x0 0x3 0x0 /* GTX125 */
0x4 0x6 0x3 0x0 0x2 0x0 /* MDIO */
0x4 0x5 0x1 0x0 0x2 0x0>; /* MDC */
};
};
};
@ -285,28 +282,28 @@ qe@e0080000 {
#size-cells = <1>;
device_type = "qe";
compatible = "fsl,qe";
ranges = <0 e0080000 00040000>;
reg = <e0080000 480>;
ranges = <0x0 0xe0080000 0x40000>;
reg = <0xe0080000 0x480>;
brg-frequency = <0>;
bus-frequency = <179A7B00>;
bus-frequency = <396000000>;
muram@10000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,qe-muram", "fsl,cpm-muram";
ranges = <0 00010000 0000c000>;
ranges = <0x0 0x10000 0x10000>;
data-only@0 {
compatible = "fsl,qe-muram-data",
"fsl,cpm-muram-data";
reg = <0 c000>;
reg = <0x0 0x10000>;
};
};
spi@4c0 {
cell-index = <0>;
compatible = "fsl,spi";
reg = <4c0 40>;
reg = <0x4c0 0x40>;
interrupts = <2>;
interrupt-parent = <&qeic>;
mode = "cpu";
@ -315,7 +312,7 @@ spi@4c0 {
spi@500 {
cell-index = <1>;
compatible = "fsl,spi";
reg = <500 40>;
reg = <0x500 0x40>;
interrupts = <1>;
interrupt-parent = <&qeic>;
mode = "cpu";
@ -324,11 +321,9 @@ spi@500 {
enet2: ucc@2000 {
device_type = "network";
compatible = "ucc_geth";
model = "UCC";
cell-index = <1>;
device-id = <1>;
reg = <2000 200>;
interrupts = <20>;
reg = <0x2000 0x200>;
interrupts = <32>;
interrupt-parent = <&qeic>;
local-mac-address = [ 00 00 00 00 00 00 ];
rx-clock-name = "none";
@ -341,11 +336,9 @@ enet2: ucc@2000 {
enet3: ucc@3000 {
device_type = "network";
compatible = "ucc_geth";
model = "UCC";
cell-index = <2>;
device-id = <2>;
reg = <3000 200>;
interrupts = <21>;
reg = <0x3000 0x200>;
interrupts = <33>;
interrupt-parent = <&qeic>;
local-mac-address = [ 00 00 00 00 00 00 ];
rx-clock-name = "none";
@ -358,7 +351,7 @@ enet3: ucc@3000 {
mdio@2120 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2120 18>;
reg = <0x2120 0x18>;
compatible = "fsl,ucc-mdio";
/* These are the same PHYs as on
@ -366,25 +359,25 @@ mdio@2120 {
qe_phy0: ethernet-phy@07 {
interrupt-parent = <&mpic>;
interrupts = <1 1>;
reg = <7>;
reg = <0x7>;
device_type = "ethernet-phy";
};
qe_phy1: ethernet-phy@01 {
interrupt-parent = <&mpic>;
interrupts = <2 1>;
reg = <1>;
reg = <0x1>;
device_type = "ethernet-phy";
};
qe_phy2: ethernet-phy@02 {
interrupt-parent = <&mpic>;
interrupts = <1 1>;
reg = <2>;
reg = <0x2>;
device_type = "ethernet-phy";
};
qe_phy3: ethernet-phy@03 {
interrupt-parent = <&mpic>;
interrupts = <2 1>;
reg = <3>;
reg = <0x3>;
device_type = "ethernet-phy";
};
};
@ -394,9 +387,9 @@ qeic: interrupt-controller@80 {
compatible = "fsl,qe-ic";
#address-cells = <0>;
#interrupt-cells = <1>;
reg = <80 80>;
reg = <0x80 0x80>;
big-endian;
interrupts = <2e 2 2e 2>; //high:30 low:30
interrupts = <46 2 46 2>; //high:30 low:30
interrupt-parent = <&mpic>;
};
@ -404,30 +397,30 @@ qeic: interrupt-controller@80 {
pci0: pci@e0008000 {
cell-index = <0>;
interrupt-map-mask = <f800 0 0 7>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x12 AD18 */
9000 0 0 1 &mpic 5 1
9000 0 0 2 &mpic 6 1
9000 0 0 3 &mpic 7 1
9000 0 0 4 &mpic 4 1
0x9000 0x0 0x0 0x1 &mpic 0x5 0x1
0x9000 0x0 0x0 0x2 &mpic 0x6 0x1
0x9000 0x0 0x0 0x3 &mpic 0x7 0x1
0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
/* IDSEL 0x13 AD19 */
9800 0 0 1 &mpic 6 1
9800 0 0 2 &mpic 7 1
9800 0 0 3 &mpic 4 1
9800 0 0 4 &mpic 5 1>;
0x9800 0x0 0x0 0x1 &mpic 0x6 0x1
0x9800 0x0 0x0 0x2 &mpic 0x7 0x1
0x9800 0x0 0x0 0x3 &mpic 0x4 0x1
0x9800 0x0 0x0 0x4 &mpic 0x5 0x1>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
bus-range = <0 ff>;
ranges = <02000000 0 80000000 80000000 0 20000000
01000000 0 00000000 e2000000 0 00800000>;
clock-frequency = <3f940aa>;
interrupts = <24 2>;
bus-range = <0 255>;
ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
clock-frequency = <66666666>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <e0008000 1000>;
reg = <0xe0008000 0x1000>;
compatible = "fsl,mpc8540-pci";
device_type = "pci";
};
@ -435,39 +428,39 @@ pci0: pci@e0008000 {
/* PCI Express */
pci1: pcie@e000a000 {
cell-index = <2>;
interrupt-map-mask = <f800 0 0 7>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x0 (PEX) */
00000 0 0 1 &mpic 0 1
00000 0 0 2 &mpic 1 1
00000 0 0 3 &mpic 2 1
00000 0 0 4 &mpic 3 1>;
00000 0x0 0x0 0x1 &mpic 0x0 0x1
00000 0x0 0x0 0x2 &mpic 0x1 0x1
00000 0x0 0x0 0x3 &mpic 0x2 0x1
00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
interrupt-parent = <&mpic>;
interrupts = <1a 2>;
bus-range = <0 ff>;
ranges = <02000000 0 a0000000 a0000000 0 10000000
01000000 0 00000000 e2800000 0 00800000>;
clock-frequency = <1fca055>;
interrupts = <26 2>;
bus-range = <0 255>;
ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
clock-frequency = <33333333>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <e000a000 1000>;
reg = <0xe000a000 0x1000>;
compatible = "fsl,mpc8548-pcie";
device_type = "pci";
pcie@0 {
reg = <0 0 0 0 0>;
reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <02000000 0 a0000000
02000000 0 a0000000
0 10000000
ranges = <0x2000000 0x0 0xa0000000
0x2000000 0x0 0xa0000000
0x0 0x10000000
01000000 0 00000000
01000000 0 00000000
0 00800000>;
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x800000>;
};
};
};

383
arch/powerpc/boot/dts/mpc8572ds.dts
View File

@ -1,7 +1,7 @@
/*
* MPC8572 DS Device Tree Source
*
* Copyright 2007 Freescale Semiconductor Inc.
* Copyright 2007, 2008 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@ -9,6 +9,7 @@
* option) any later version.
*/
/dts-v1/;
/ {
model = "fsl,MPC8572DS";
compatible = "fsl,MPC8572DS";
@ -33,11 +34,11 @@ cpus {
PowerPC,8572@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <20>; // 32 bytes
i-cache-line-size = <20>; // 32 bytes
d-cache-size = <8000>; // L1, 32K
i-cache-size = <8000>; // L1, 32K
reg = <0x0>;
d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <32>; // 32 bytes
d-cache-size = <0x8000>; // L1, 32K
i-cache-size = <0x8000>; // L1, 32K
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
@ -45,11 +46,11 @@ PowerPC,8572@0 {
PowerPC,8572@1 {
device_type = "cpu";
reg = <1>;
d-cache-line-size = <20>; // 32 bytes
i-cache-line-size = <20>; // 32 bytes
d-cache-size = <8000>; // L1, 32K
i-cache-size = <8000>; // L1, 32K
reg = <0x1>;
d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <32>; // 32 bytes
d-cache-size = <0x8000>; // L1, 32K
i-cache-size = <0x8000>; // L1, 32K
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
@ -58,38 +59,38 @@ PowerPC,8572@1 {
memory {
device_type = "memory";
reg = <00000000 00000000>; // Filled by U-Boot
reg = <0x0 0x0>; // Filled by U-Boot
};
soc8572@ffe00000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
ranges = <00000000 ffe00000 00100000>;
reg = <ffe00000 00001000>; // CCSRBAR & soc regs, remove once parse code for immrbase fixed
ranges = <0x0 0xffe00000 0x100000>;
reg = <0xffe00000 0x1000>; // CCSRBAR & soc regs, remove once parse code for immrbase fixed
bus-frequency = <0>; // Filled out by uboot.
memory-controller@2000 {
compatible = "fsl,mpc8572-memory-controller";
reg = <2000 1000>;
reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <12 2>;
interrupts = <18 2>;
};
memory-controller@6000 {
compatible = "fsl,mpc8572-memory-controller";
reg = <6000 1000>;
reg = <0x6000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <12 2>;
interrupts = <18 2>;
};
l2-cache-controller@20000 {
compatible = "fsl,mpc8572-l2-cache-controller";
reg = <20000 1000>;
cache-line-size = <20>; // 32 bytes
cache-size = <80000>; // L2, 512K
reg = <0x20000 0x1000>;
cache-line-size = <32>; // 32 bytes
cache-size = <0x80000>; // L2, 512K
interrupt-parent = <&mpic>;
interrupts = <10 2>;
interrupts = <16 2>;
};
i2c@3000 {
@ -97,8 +98,8 @@ i2c@3000 {
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
reg = <3000 100>;
interrupts = <2b 2>;
reg = <0x3000 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
};
@ -108,8 +109,8 @@ i2c@3100 {
#size-cells = <0>;
cell-index = <1>;
compatible = "fsl-i2c";
reg = <3100 100>;
interrupts = <2b 2>;
reg = <0x3100 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
};
@ -118,27 +119,27 @@ mdio@24520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
reg = <24520 20>;
reg = <0x24520 0x20>;
phy0: ethernet-phy@0 {
interrupt-parent = <&mpic>;
interrupts = <a 1>;
reg = <0>;
interrupts = <10 1>;
reg = <0x0>;
};
phy1: ethernet-phy@1 {
interrupt-parent = <&mpic>;
interrupts = <a 1>;
reg = <1>;
interrupts = <10 1>;
reg = <0x1>;
};
phy2: ethernet-phy@2 {
interrupt-parent = <&mpic>;
interrupts = <a 1>;
reg = <2>;
interrupts = <10 1>;
reg = <0x2>;
};
phy3: ethernet-phy@3 {
interrupt-parent = <&mpic>;
interrupts = <a 1>;
reg = <3>;
interrupts = <10 1>;
reg = <0x3>;
};
};
@ -147,9 +148,9 @@ enet0: ethernet@24000 {
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <24000 1000>;
reg = <0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <1d 2 1e 2 22 2>;
interrupts = <29 2 30 2 34 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy0>;
phy-connection-type = "rgmii-id";
@ -160,9 +161,9 @@ enet1: ethernet@25000 {
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <25000 1000>;
reg = <0x25000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <23 2 24 2 28 2>;
interrupts = <35 2 36 2 40 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy1>;
phy-connection-type = "rgmii-id";
@ -173,9 +174,9 @@ enet2: ethernet@26000 {
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <26000 1000>;
reg = <0x26000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <1f 2 20 2 21 2>;
interrupts = <31 2 32 2 33 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy2>;
phy-connection-type = "rgmii-id";
@ -186,9 +187,9 @@ enet3: ethernet@27000 {
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <27000 1000>;
reg = <0x27000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <25 2 26 2 27 2>;
interrupts = <37 2 38 2 39 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy3>;
phy-connection-type = "rgmii-id";
@ -198,9 +199,9 @@ serial0: serial@4500 {
cell-index = <0>;
device_type = "serial";
compatible = "ns16550";
reg = <4500 100>;
reg = <0x4500 0x100>;
clock-frequency = <0>;
interrupts = <2a 2>;
interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
@ -208,15 +209,15 @@ serial1: serial@4600 {
cell-index = <1>;
device_type = "serial";
compatible = "ns16550";
reg = <4600 100>;
reg = <0x4600 0x100>;
clock-frequency = <0>;
interrupts = <2a 2>;
interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
global-utilities@e0000 { //global utilities block
compatible = "fsl,mpc8572-guts";
reg = <e0000 1000>;
reg = <0xe0000 0x1000>;
fsl,has-rstcr;
};
@ -225,7 +226,7 @@ mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <40000 40000>;
reg = <0x40000 0x40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
@ -239,167 +240,167 @@ pci0: pcie@ffe08000 {
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <ffe08000 1000>;
bus-range = <0 ff>;
ranges = <02000000 0 80000000 80000000 0 20000000
01000000 0 00000000 ffc00000 0 00010000>;
clock-frequency = <1fca055>;
reg = <0xffe08000 0x1000>;
bus-range = <0 255>;
ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
0x1000000 0x0 0x0 0xffc00000 0x0 0x10000>;
clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
interrupt-map-mask = <ff00 0 0 7>;
interrupts = <24 2>;
interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x11 func 0 - PCI slot 1 */
8800 0 0 1 &mpic 2 1
8800 0 0 2 &mpic 3 1
8800 0 0 3 &mpic 4 1
8800 0 0 4 &mpic 1 1
0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x11 func 1 - PCI slot 1 */
8900 0 0 1 &mpic 2 1
8900 0 0 2 &mpic 3 1
8900 0 0 3 &mpic 4 1
8900 0 0 4 &mpic 1 1
0x8900 0x0 0x0 0x1 &mpic 0x2 0x1
0x8900 0x0 0x0 0x2 &mpic 0x3 0x1
0x8900 0x0 0x0 0x3 &mpic 0x4 0x1
0x8900 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x11 func 2 - PCI slot 1 */
8a00 0 0 1 &mpic 2 1
8a00 0 0 2 &mpic 3 1
8a00 0 0 3 &mpic 4 1
8a00 0 0 4 &mpic 1 1
0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1
0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1
0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1
0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x11 func 3 - PCI slot 1 */
8b00 0 0 1 &mpic 2 1
8b00 0 0 2 &mpic 3 1
8b00 0 0 3 &mpic 4 1
8b00 0 0 4 &mpic 1 1
0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1
0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1
0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1
0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x11 func 4 - PCI slot 1 */
8c00 0 0 1 &mpic 2 1
8c00 0 0 2 &mpic 3 1
8c00 0 0 3 &mpic 4 1
8c00 0 0 4 &mpic 1 1
0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1
0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1
0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1
0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x11 func 5 - PCI slot 1 */
8d00 0 0 1 &mpic 2 1
8d00 0 0 2 &mpic 3 1
8d00 0 0 3 &mpic 4 1
8d00 0 0 4 &mpic 1 1
0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1
0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1
0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1
0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x11 func 6 - PCI slot 1 */
8e00 0 0 1 &mpic 2 1
8e00 0 0 2 &mpic 3 1
8e00 0 0 3 &mpic 4 1
8e00 0 0 4 &mpic 1 1
0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1
0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1
0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1
0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x11 func 7 - PCI slot 1 */
8f00 0 0 1 &mpic 2 1
8f00 0 0 2 &mpic 3 1
8f00 0 0 3 &mpic 4 1
8f00 0 0 4 &mpic 1 1
0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1
0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1
0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1
0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x12 func 0 - PCI slot 2 */
9000 0 0 1 &mpic 3 1
9000 0 0 2 &mpic 4 1
9000 0 0 3 &mpic 1 1
9000 0 0 4 &mpic 2 1
0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
0x9000 0x0 0x0 0x3 &mpic 0x1 0x1
0x9000 0x0 0x0 0x4 &mpic 0x2 0x1
/* IDSEL 0x12 func 1 - PCI slot 2 */
9100 0 0 1 &mpic 3 1
9100 0 0 2 &mpic 4 1
9100 0 0 3 &mpic 1 1
9100 0 0 4 &mpic 2 1
0x9100 0x0 0x0 0x1 &mpic 0x3 0x1
0x9100 0x0 0x0 0x2 &mpic 0x4 0x1
0x9100 0x0 0x0 0x3 &mpic 0x1 0x1
0x9100 0x0 0x0 0x4 &mpic 0x2 0x1
/* IDSEL 0x12 func 2 - PCI slot 2 */
9200 0 0 1 &mpic 3 1
9200 0 0 2 &mpic 4 1
9200 0 0 3 &mpic 1 1
9200 0 0 4 &mpic 2 1
0x9200 0x0 0x0 0x1 &mpic 0x3 0x1
0x9200 0x0 0x0 0x2 &mpic 0x4 0x1
0x9200 0x0 0x0 0x3 &mpic 0x1 0x1
0x9200 0x0 0x0 0x4 &mpic 0x2 0x1
/* IDSEL 0x12 func 3 - PCI slot 2 */
9300 0 0 1 &mpic 3 1
9300 0 0 2 &mpic 4 1
9300 0 0 3 &mpic 1 1
9300 0 0 4 &mpic 2 1
0x9300 0x0 0x0 0x1 &mpic 0x3 0x1
0x9300 0x0 0x0 0x2 &mpic 0x4 0x1
0x9300 0x0 0x0 0x3 &mpic 0x1 0x1
0x9300 0x0 0x0 0x4 &mpic 0x2 0x1
/* IDSEL 0x12 func 4 - PCI slot 2 */
9400 0 0 1 &mpic 3 1
9400 0 0 2 &mpic 4 1
9400 0 0 3 &mpic 1 1
9400 0 0 4 &mpic 2 1
0x9400 0x0 0x0 0x1 &mpic 0x3 0x1
0x9400 0x0 0x0 0x2 &mpic 0x4 0x1
0x9400 0x0 0x0 0x3 &mpic 0x1 0x1
0x9400 0x0 0x0 0x4 &mpic 0x2 0x1
/* IDSEL 0x12 func 5 - PCI slot 2 */
9500 0 0 1 &mpic 3 1
9500 0 0 2 &mpic 4 1
9500 0 0 3 &mpic 1 1
9500 0 0 4 &mpic 2 1
0x9500 0x0 0x0 0x1 &mpic 0x3 0x1
0x9500 0x0 0x0 0x2 &mpic 0x4 0x1
0x9500 0x0 0x0 0x3 &mpic 0x1 0x1
0x9500 0x0 0x0 0x4 &mpic 0x2 0x1
/* IDSEL 0x12 func 6 - PCI slot 2 */
9600 0 0 1 &mpic 3 1
9600 0 0 2 &mpic 4 1
9600 0 0 3 &mpic 1 1
9600 0 0 4 &mpic 2 1
0x9600 0x0 0x0 0x1 &mpic 0x3 0x1
0x9600 0x0 0x0 0x2 &mpic 0x4 0x1
0x9600 0x0 0x0 0x3 &mpic 0x1 0x1
0x9600 0x0 0x0 0x4 &mpic 0x2 0x1
/* IDSEL 0x12 func 7 - PCI slot 2 */
9700 0 0 1 &mpic 3 1
9700 0 0 2 &mpic 4 1
9700 0 0 3 &mpic 1 1
9700 0 0 4 &mpic 2 1
0x9700 0x0 0x0 0x1 &mpic 0x3 0x1
0x9700 0x0 0x0 0x2 &mpic 0x4 0x1
0x9700 0x0 0x0 0x3 &mpic 0x1 0x1
0x9700 0x0 0x0 0x4 &mpic 0x2 0x1
// IDSEL 0x1c USB
e000 0 0 1 &i8259 c 2
e100 0 0 2 &i8259 9 2
e200 0 0 3 &i8259 a 2
e300 0 0 4 &i8259 b 2
0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
// IDSEL 0x1d Audio
e800 0 0 1 &i8259 6 2
0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
// IDSEL 0x1e Legacy
f000 0 0 1 &i8259 7 2
f100 0 0 1 &i8259 7 2
0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
// IDSEL 0x1f IDE/SATA
f800 0 0 1 &i8259 e 2
f900 0 0 1 &i8259 5 2
0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
>;
pcie@0 {
reg = <0 0 0 0 0>;
reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <02000000 0 80000000
02000000 0 80000000
0 20000000
ranges = <0x2000000 0x0 0x80000000
0x2000000 0x0 0x80000000
0x0 0x20000000
01000000 0 00000000
01000000 0 00000000
0 00100000>;
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
uli1575@0 {
reg = <0 0 0 0 0>;
reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
#address-cells = <3>;
ranges = <02000000 0 80000000
02000000 0 80000000
0 20000000
ranges = <0x2000000 0x0 0x80000000
0x2000000 0x0 0x80000000
0x0 0x20000000
01000000 0 00000000
01000000 0 00000000
0 00100000>;
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
isa@1e {
device_type = "isa";
#interrupt-cells = <2>;
#size-cells = <1>;
#address-cells = <2>;
reg = <f000 0 0 0 0>;
ranges = <1 0 01000000 0 0
00001000>;
reg = <0xf000 0x0 0x0 0x0 0x0>;
ranges = <0x1 0x0 0x1000000 0x0 0x0
0x1000>;
interrupt-parent = <&i8259>;
i8259: interrupt-controller@20 {
reg = <1 20 2
1 a0 2
1 4d0 2>;
reg = <0x1 0x20 0x2
0x1 0xa0 0x2
0x1 0x4d0 0x2>;
interrupt-controller;
device_type = "interrupt-controller";
#address-cells = <0>;
@ -412,29 +413,29 @@ i8259: interrupt-controller@20 {
i8042@60 {
#size-cells = <0>;
#address-cells = <1>;
reg = <1 60 1 1 64 1>;
interrupts = <1 3 c 3>;
reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
interrupts = <1 3 12 3>;
interrupt-parent =
<&i8259>;
keyboard@0 {
reg = <0>;
reg = <0x0>;
compatible = "pnpPNP,303";
};
mouse@1 {
reg = <1>;
reg = <0x1>;
compatible = "pnpPNP,f03";
};
};
rtc@70 {
compatible = "pnpPNP,b00";
reg = <1 70 2>;
reg = <0x1 0x70 0x2>;
};
gpio@400 {
reg = <1 400 80>;
reg = <0x1 0x400 0x80>;
};
};
};
@ -449,33 +450,33 @@ pci1: pcie@ffe09000 {
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <ffe09000 1000>;
bus-range = <0 ff>;
ranges = <02000000 0 a0000000 a0000000 0 20000000
01000000 0 00000000 ffc10000 0 00010000>;
clock-frequency = <1fca055>;
reg = <0xffe09000 0x1000>;
bus-range = <0 255>;
ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
0x1000000 0x0 0x0 0xffc10000 0x0 0x10000>;
clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
interrupts = <1a 2>;
interrupt-map-mask = <f800 0 0 7>;
interrupts = <26 2>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x0 */
0000 0 0 1 &mpic 4 1
0000 0 0 2 &mpic 5 1
0000 0 0 3 &mpic 6 1
0000 0 0 4 &mpic 7 1
0000 0x0 0x0 0x1 &mpic 0x4 0x1
0000 0x0 0x0 0x2 &mpic 0x5 0x1
0000 0x0 0x0 0x3 &mpic 0x6 0x1
0000 0x0 0x0 0x4 &mpic 0x7 0x1
>;
pcie@0 {
reg = <0 0 0 0 0>;
reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <02000000 0 a0000000
02000000 0 a0000000
0 20000000
ranges = <0x2000000 0x0 0xa0000000
0x2000000 0x0 0xa0000000
0x0 0x20000000
01000000 0 00000000
01000000 0 00000000
0 00100000>;
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
@ -486,33 +487,33 @@ pci2: pcie@ffe0a000 {
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <ffe0a000 1000>;
bus-range = <0 ff>;
ranges = <02000000 0 c0000000 c0000000 0 20000000
01000000 0 00000000 ffc20000 0 00010000>;
clock-frequency = <1fca055>;
reg = <0xffe0a000 0x1000>;
bus-range = <0 255>;
ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
0x1000000 0x0 0x0 0xffc20000 0x0 0x10000>;
clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
interrupts = <1b 2>;
interrupt-map-mask = <f800 0 0 7>;
interrupts = <27 2>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x0 */
0000 0 0 1 &mpic 0 1
0000 0 0 2 &mpic 1 1
0000 0 0 3 &mpic 2 1
0000 0 0 4 &mpic 3 1
0000 0x0 0x0 0x1 &mpic 0x0 0x1
0000 0x0 0x0 0x2 &mpic 0x1 0x1
0000 0x0 0x0 0x3 &mpic 0x2 0x1
0000 0x0 0x0 0x4 &mpic 0x3 0x1
>;
pcie@0 {
reg = <0 0 0 0 0>;
reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <02000000 0 c0000000
02000000 0 c0000000
0 20000000
ranges = <0x2000000 0x0 0xc0000000
0x2000000 0x0 0xc0000000
0x0 0x20000000
01000000 0 00000000
01000000 0 00000000
0 00100000>;
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
};

2
arch/powerpc/boot/dts/mpc8641_hpcn.dts
View File

@ -13,7 +13,7 @@
/ {
model = "MPC8641HPCN";
compatible = "mpc86xx";
compatible = "fsl,mpc8641hpcn";
#address-cells = <1>;
#size-cells = <1>;

58
arch/powerpc/boot/dts/mpc866ads.dts
View File

@ -2,6 +2,7 @@
* MPC866 ADS Device Tree Source
*
* Copyright 2006 MontaVista Software, Inc.
* Copyright 2008 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@ -9,6 +10,7 @@
* option) any later version.
*/
/dts-v1/;
/ {
model = "MPC866ADS";
@ -22,37 +24,37 @@ cpus {
PowerPC,866@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <10>; // 16 bytes
i-cache-line-size = <10>; // 16 bytes
d-cache-size = <2000>; // L1, 8K
i-cache-size = <4000>; // L1, 16K
reg = <0x0>;
d-cache-line-size = <16>; // 16 bytes
i-cache-line-size = <16>; // 16 bytes
d-cache-size = <0x2000>; // L1, 8K
i-cache-size = <0x4000>; // L1, 16K
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
interrupts = <f 2>; // decrementer interrupt
interrupts = <15 2>; // decrementer interrupt
interrupt-parent = <&PIC>;
};
};
memory {
device_type = "memory";
reg = <00000000 800000>;
reg = <0x0 0x800000>;
};
localbus@ff000100 {
compatible = "fsl,mpc866-localbus", "fsl,pq1-localbus";
#address-cells = <2>;
#size-cells = <1>;
reg = <ff000100 40>;
reg = <0xff000100 0x40>;
ranges = <
1 0 ff080000 00008000
5 0 ff0a0000 00008000
0x1 0x0 0xff080000 0x8000
0x5 0x0 0xff0a0000 0x8000
>;
board-control@1,0 {
reg = <1 0 20 5 300 4>;
reg = <0x1 0x0 0x20 0x5 0x300 0x4>;
compatible = "fsl,mpc866ads-bcsr";
};
};
@ -61,17 +63,17 @@ soc@ff000000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
ranges = <0 ff000000 00100000>;
reg = <ff000000 00000200>;
ranges = <0x0 0xff000000 0x100000>;
reg = <0xff000000 0x200>;
bus-frequency = <0>;
mdio@e00 {
compatible = "fsl,mpc866-fec-mdio", "fsl,pq1-fec-mdio";
reg = <e00 188>;
reg = <0xe00 0x188>;
#address-cells = <1>;
#size-cells = <0>;
PHY: ethernet-phy@f {
reg = <f>;
reg = <0xf>;
device_type = "ethernet-phy";
};
};
@ -80,7 +82,7 @@ ethernet@e00 {
device_type = "network";
compatible = "fsl,mpc866-fec-enet",
"fsl,pq1-fec-enet";
reg = <e00 188>;
reg = <0xe00 0x188>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <3 1>;
interrupt-parent = <&PIC>;
@ -91,7 +93,7 @@ ethernet@e00 {
PIC: pic@0 {
interrupt-controller;
#interrupt-cells = <2>;
reg = <0 24>;
reg = <0x0 0x24>;
compatible = "fsl,mpc866-pic", "fsl,pq1-pic";
};
@ -100,7 +102,7 @@ cpm@9c0 {
#size-cells = <1>;
compatible = "fsl,mpc866-cpm", "fsl,cpm1";
ranges;
reg = <9c0 40>;
reg = <0x9c0 0x40>;
brg-frequency = <0>;
interrupts = <0 2>; // cpm error interrupt
interrupt-parent = <&CPM_PIC>;
@ -108,11 +110,11 @@ cpm@9c0 {
muram@2000 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 2000 2000>;
ranges = <0x0 0x2000 0x2000>;
data@0 {
compatible = "fsl,cpm-muram-data";
reg = <0 1c00>;
reg = <0x0 0x1c00>;
};
};
@ -120,7 +122,7 @@ brg@9f0 {
compatible = "fsl,mpc866-brg",
"fsl,cpm1-brg",
"fsl,cpm-brg";
reg = <9f0 10>;
reg = <0x9f0 0x10>;
clock-frequency = <0>;
};
@ -130,7 +132,7 @@ CPM_PIC: pic@930 {
#interrupt-cells = <1>;
interrupts = <5 2 0 2>;
interrupt-parent = <&PIC>;
reg = <930 20>;
reg = <0x930 0x20>;
compatible = "fsl,mpc866-cpm-pic",
"fsl,cpm1-pic";
};
@ -140,31 +142,31 @@ serial@a80 {
device_type = "serial";
compatible = "fsl,mpc866-smc-uart",
"fsl,cpm1-smc-uart";
reg = <a80 10 3e80 40>;
reg = <0xa80 0x10 0x3e80 0x40>;
interrupts = <4>;
interrupt-parent = <&CPM_PIC>;
fsl,cpm-brg = <1>;
fsl,cpm-command = <0090>;
fsl,cpm-command = <0x90>;
};
serial@a90 {
device_type = "serial";
compatible = "fsl,mpc866-smc-uart",
"fsl,cpm1-smc-uart";
reg = <a90 10 3f80 40>;
reg = <0xa90 0x10 0x3f80 0x40>;
interrupts = <3>;
interrupt-parent = <&CPM_PIC>;
fsl,cpm-brg = <2>;
fsl,cpm-command = <00d0>;
fsl,cpm-command = <0xd0>;
};
ethernet@a00 {
device_type = "network";
compatible = "fsl,mpc866-scc-enet",
"fsl,cpm1-scc-enet";
reg = <a00 18 3c00 100>;
reg = <0xa00 0x18 0x3c00 0x100>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <1e>;
interrupts = <30>;
interrupt-parent = <&CPM_PIC>;
fsl,cpm-command = <0000>;
linux,network-index = <1>;

77
arch/powerpc/boot/dts/mpc885ads.dts
View File

@ -2,7 +2,7 @@
* MPC885 ADS Device Tree Source
*
* Copyright 2006 MontaVista Software, Inc.
* Copyright 2007 Freescale Semiconductor, Inc.
* Copyright 2007,2008 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@ -10,6 +10,7 @@
* option) any later version.
*/
/dts-v1/;
/ {
model = "MPC885ADS";
@ -23,45 +24,45 @@ cpus {
PowerPC,885@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <d#16>;
i-cache-line-size = <d#16>;
d-cache-size = <d#8192>;
i-cache-size = <d#8192>;
reg = <0x0>;
d-cache-line-size = <16>;
i-cache-line-size = <16>;
d-cache-size = <8192>;
i-cache-size = <8192>;
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
interrupts = <f 2>; // decrementer interrupt
interrupts = <15 2>; // decrementer interrupt
interrupt-parent = <&PIC>;
};
};
memory {
device_type = "memory";
reg = <0 0>;
reg = <0x0 0x0>;
};
localbus@ff000100 {
compatible = "fsl,mpc885-localbus", "fsl,pq1-localbus";
#address-cells = <2>;
#size-cells = <1>;
reg = <ff000100 40>;
reg = <0xff000100 0x40>;
ranges = <
0 0 fe000000 00800000
1 0 ff080000 00008000
5 0 ff0a0000 00008000
0x0 0x0 0xfe000000 0x800000
0x1 0x0 0xff080000 0x8000
0x5 0x0 0xff0a0000 0x8000
>;
flash@0,0 {
compatible = "jedec-flash";
reg = <0 0 800000>;
reg = <0x0 0x0 0x800000>;
bank-width = <4>;
device-width = <1>;
};
board-control@1,0 {
reg = <1 0 20 5 300 4>;
reg = <0x1 0x0 0x20 0x5 0x300 0x4>;
compatible = "fsl,mpc885ads-bcsr";
};
};
@ -71,30 +72,30 @@ soc@ff000000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
ranges = <0 ff000000 00004000>;
ranges = <0x0 0xff000000 0x4000>;
bus-frequency = <0>;
// Temporary -- will go away once kernel uses ranges for get_immrbase().
reg = <ff000000 4000>;
reg = <0xff000000 0x4000>;
mdio@e00 {
compatible = "fsl,mpc885-fec-mdio", "fsl,pq1-fec-mdio";
reg = <e00 188>;
reg = <0xe00 0x188>;
#address-cells = <1>;
#size-cells = <0>;
PHY0: ethernet-phy@0 {
reg = <0>;
reg = <0x0>;
device_type = "ethernet-phy";
};
PHY1: ethernet-phy@1 {
reg = <1>;
reg = <0x1>;
device_type = "ethernet-phy";
};
PHY2: ethernet-phy@2 {
reg = <2>;
reg = <0x2>;
device_type = "ethernet-phy";
};
};
@ -103,7 +104,7 @@ ethernet@e00 {
device_type = "network";
compatible = "fsl,mpc885-fec-enet",
"fsl,pq1-fec-enet";
reg = <e00 188>;
reg = <0xe00 0x188>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <3 1>;
interrupt-parent = <&PIC>;
@ -115,7 +116,7 @@ ethernet@1e00 {
device_type = "network";
compatible = "fsl,mpc885-fec-enet",
"fsl,pq1-fec-enet";
reg = <1e00 188>;
reg = <0x1e00 0x188>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <7 1>;
interrupt-parent = <&PIC>;
@ -126,7 +127,7 @@ ethernet@1e00 {
PIC: interrupt-controller@0 {
interrupt-controller;
#interrupt-cells = <2>;
reg = <0 24>;
reg = <0x0 0x24>;
compatible = "fsl,mpc885-pic", "fsl,pq1-pic";
};
@ -136,29 +137,29 @@ pcmcia@80 {
#size-cells = <2>;
compatible = "fsl,pq-pcmcia";
device_type = "pcmcia";
reg = <80 80>;
reg = <0x80 0x80>;
interrupt-parent = <&PIC>;
interrupts = <d 1>;
interrupts = <13 1>;
};
cpm@9c0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc885-cpm", "fsl,cpm1";
command-proc = <9c0>;
command-proc = <0x9c0>;
interrupts = <0>; // cpm error interrupt
interrupt-parent = <&CPM_PIC>;
reg = <9c0 40>;
reg = <0x9c0 0x40>;
ranges;
muram@2000 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 2000 2000>;
ranges = <0x0 0x2000 0x2000>;
data@0 {
compatible = "fsl,cpm-muram-data";
reg = <0 1c00>;
reg = <0x0 0x1c00>;
};
};
@ -167,7 +168,7 @@ brg@9f0 {
"fsl,cpm1-brg",
"fsl,cpm-brg";
clock-frequency = <0>;
reg = <9f0 10>;
reg = <0x9f0 0x10>;
};
CPM_PIC: interrupt-controller@930 {
@ -175,7 +176,7 @@ CPM_PIC: interrupt-controller@930 {
#interrupt-cells = <1>;
interrupts = <5 2 0 2>;
interrupt-parent = <&PIC>;
reg = <930 20>;
reg = <0x930 0x20>;
compatible = "fsl,mpc885-cpm-pic",
"fsl,cpm1-pic";
};
@ -184,34 +185,34 @@ serial@a80 {
device_type = "serial";
compatible = "fsl,mpc885-smc-uart",
"fsl,cpm1-smc-uart";
reg = <a80 10 3e80 40>;
reg = <0xa80 0x10 0x3e80 0x40>;
interrupts = <4>;
interrupt-parent = <&CPM_PIC>;
fsl,cpm-brg = <1>;
fsl,cpm-command = <0090>;
fsl,cpm-command = <0x90>;
};
serial@a90 {
device_type = "serial";
compatible = "fsl,mpc885-smc-uart",
"fsl,cpm1-smc-uart";
reg = <a90 10 3f80 40>;
reg = <0xa90 0x10 0x3f80 0x40>;
interrupts = <3>;
interrupt-parent = <&CPM_PIC>;
fsl,cpm-brg = <2>;
fsl,cpm-command = <00d0>;
fsl,cpm-command = <0xd0>;
};
ethernet@a40 {
device_type = "network";
compatible = "fsl,mpc885-scc-enet",
"fsl,cpm1-scc-enet";
reg = <a40 18 3e00 100>;
reg = <0xa40 0x18 0x3e00 0x100>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <1c>;
interrupts = <28>;
interrupt-parent = <&CPM_PIC>;
phy-handle = <&PHY2>;
fsl,cpm-command = <0080>;
fsl,cpm-command = <0x80>;
linux,network-index = <2>;
};
};

126
arch/powerpc/boot/dts/pq2fads.dts
View File

@ -1,7 +1,7 @@
/*
* Device Tree for the PQ2FADS-ZU board with an MPC8280 chip.
*
* Copyright 2007 Freescale Semiconductor Inc.
* Copyright 2007,2008 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@ -9,6 +9,8 @@
* option) any later version.
*/
/dts-v1/;
/ {
model = "pq2fads";
compatible = "fsl,pq2fads";
@ -21,11 +23,11 @@ cpus {
cpu@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <d#32>;
i-cache-line-size = <d#32>;
d-cache-size = <d#16384>;
i-cache-size = <d#16384>;
reg = <0x0>;
d-cache-line-size = <32>;
i-cache-line-size = <32>;
d-cache-size = <16384>;
i-cache-size = <16384>;
timebase-frequency = <0>;
clock-frequency = <0>;
};
@ -33,7 +35,7 @@ cpu@0 {
memory {
device_type = "memory";
reg = <0 0>;
reg = <0x0 0x0>;
};
localbus@f0010100 {
@ -41,67 +43,67 @@ localbus@f0010100 {
"fsl,pq2-localbus";
#address-cells = <2>;
#size-cells = <1>;
reg = <f0010100 60>;
reg = <0xf0010100 0x60>;
ranges = <0 0 fe000000 00800000
1 0 f4500000 00008000
8 0 f8200000 00008000>;
ranges = <0x0 0x0 0xfe000000 0x800000
0x1 0x0 0xf4500000 0x8000
0x8 0x0 0xf8200000 0x8000>;
flash@0,0 {
compatible = "jedec-flash";
reg = <0 0 800000>;
reg = <0x0 0x0 0x800000>;
bank-width = <4>;
device-width = <1>;
};
bcsr@1,0 {
reg = <1 0 20>;
reg = <0x1 0x0 0x20>;
compatible = "fsl,pq2fads-bcsr";
};
PCI_PIC: pic@8,0 {
#interrupt-cells = <1>;
interrupt-controller;
reg = <8 0 8>;
reg = <0x8 0x0 0x8>;
compatible = "fsl,pq2ads-pci-pic";
interrupt-parent = <&PIC>;
interrupts = <18 8>;
interrupts = <24 8>;
};
};
pci@f0010800 {
device_type = "pci";
reg = <f0010800 10c f00101ac 8 f00101c4 8>;
reg = <0xf0010800 0x10c 0xf00101ac 0x8 0xf00101c4 0x8>;
compatible = "fsl,mpc8280-pci", "fsl,pq2-pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
clock-frequency = <d#66000000>;
interrupt-map-mask = <f800 0 0 7>;
clock-frequency = <66000000>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x16 */
b000 0 0 1 &PCI_PIC 0
b000 0 0 2 &PCI_PIC 1
b000 0 0 3 &PCI_PIC 2
b000 0 0 4 &PCI_PIC 3
0xb000 0x0 0x0 0x1 &PCI_PIC 0
0xb000 0x0 0x0 0x2 &PCI_PIC 1
0xb000 0x0 0x0 0x3 &PCI_PIC 2
0xb000 0x0 0x0 0x4 &PCI_PIC 3
/* IDSEL 0x17 */
b800 0 0 1 &PCI_PIC 4
b800 0 0 2 &PCI_PIC 5
b800 0 0 3 &PCI_PIC 6
b800 0 0 4 &PCI_PIC 7
0xb800 0x0 0x0 0x1 &PCI_PIC 4
0xb800 0x0 0x0 0x2 &PCI_PIC 5
0xb800 0x0 0x0 0x3 &PCI_PIC 6
0xb800 0x0 0x0 0x4 &PCI_PIC 7
/* IDSEL 0x18 */
c000 0 0 1 &PCI_PIC 8
c000 0 0 2 &PCI_PIC 9
c000 0 0 3 &PCI_PIC a
c000 0 0 4 &PCI_PIC b>;
0xc000 0x0 0x0 0x1 &PCI_PIC 8
0xc000 0x0 0x0 0x2 &PCI_PIC 9
0xc000 0x0 0x0 0x3 &PCI_PIC 10
0xc000 0x0 0x0 0x4 &PCI_PIC 11>;
interrupt-parent = <&PIC>;
interrupts = <12 8>;
ranges = <42000000 0 80000000 80000000 0 20000000
02000000 0 a0000000 a0000000 0 20000000
01000000 0 00000000 f6000000 0 02000000>;
interrupts = <18 8>;
ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x20000000
0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
0x1000000 0x0 0x0 0xf6000000 0x0 0x2000000>;
};
soc@f0000000 {
@ -109,27 +111,27 @@ soc@f0000000 {
#size-cells = <1>;
device_type = "soc";
compatible = "fsl,mpc8280", "fsl,pq2-soc";
ranges = <00000000 f0000000 00053000>;
ranges = <0x0 0xf0000000 0x53000>;
// Temporary -- will go away once kernel uses ranges for get_immrbase().
reg = <f0000000 00053000>;
reg = <0xf0000000 0x53000>;
cpm@119c0 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
compatible = "fsl,mpc8280-cpm", "fsl,cpm2";
reg = <119c0 30>;
reg = <0x119c0 0x30>;
ranges;
muram@0 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 10000>;
ranges = <0x0 0x0 0x10000>;
data@0 {
compatible = "fsl,cpm-muram-data";
reg = <0 2000 9800 800>;
reg = <0x0 0x2000 0x9800 0x800>;
};
};
@ -137,53 +139,53 @@ brg@119f0 {
compatible = "fsl,mpc8280-brg",
"fsl,cpm2-brg",
"fsl,cpm-brg";
reg = <119f0 10 115f0 10>;
reg = <0x119f0 0x10 0x115f0 0x10>;
};
serial@11a00 {
device_type = "serial";
compatible = "fsl,mpc8280-scc-uart",
"fsl,cpm2-scc-uart";
reg = <11a00 20 8000 100>;
interrupts = <28 8>;
reg = <0x11a00 0x20 0x8000 0x100>;
interrupts = <40 8>;
interrupt-parent = <&PIC>;
fsl,cpm-brg = <1>;
fsl,cpm-command = <00800000>;
fsl,cpm-command = <0x800000>;
};
serial@11a20 {
device_type = "serial";
compatible = "fsl,mpc8280-scc-uart",
"fsl,cpm2-scc-uart";
reg = <11a20 20 8100 100>;
interrupts = <29 8>;
reg = <0x11a20 0x20 0x8100 0x100>;
interrupts = <41 8>;
interrupt-parent = <&PIC>;
fsl,cpm-brg = <2>;
fsl,cpm-command = <04a00000>;
fsl,cpm-command = <0x4a00000>;
};
ethernet@11320 {
device_type = "network";
compatible = "fsl,mpc8280-fcc-enet",
"fsl,cpm2-fcc-enet";
reg = <11320 20 8500 100 113b0 1>;
interrupts = <21 8>;
reg = <0x11320 0x20 0x8500 0x100 0x113b0 0x1>;
interrupts = <33 8>;
interrupt-parent = <&PIC>;
phy-handle = <&PHY0>;
linux,network-index = <0>;
fsl,cpm-command = <16200300>;
fsl,cpm-command = <0x16200300>;
};
ethernet@11340 {
device_type = "network";
compatible = "fsl,mpc8280-fcc-enet",
"fsl,cpm2-fcc-enet";
reg = <11340 20 8600 100 113d0 1>;
interrupts = <22 8>;
reg = <0x11340 0x20 0x8600 0x100 0x113d0 0x1>;
interrupts = <34 8>;
interrupt-parent = <&PIC>;
phy-handle = <&PHY1>;
linux,network-index = <1>;
fsl,cpm-command = <1a400300>;
fsl,cpm-command = <0x1a400300>;
local-mac-address = [00 e0 0c 00 79 01];
};
@ -194,21 +196,21 @@ mdio@10d40 {
"fsl,cpm2-mdio-bitbang";
#address-cells = <1>;
#size-cells = <0>;
reg = <10d40 14>;
reg = <0x10d40 0x14>;
fsl,mdio-pin = <9>;
fsl,mdc-pin = <a>;
fsl,mdc-pin = <10>;
PHY0: ethernet-phy@0 {
interrupt-parent = <&PIC>;
interrupts = <19 2>;
reg = <0>;
interrupts = <25 2>;
reg = <0x0>;
device_type = "ethernet-phy";
};
PHY1: ethernet-phy@1 {
interrupt-parent = <&PIC>;
interrupts = <19 2>;
reg = <3>;
interrupts = <25 2>;
reg = <0x3>;
device_type = "ethernet-phy";
};
};
@ -218,17 +220,17 @@ usb@11b60 {
#size-cells = <0>;
compatible = "fsl,mpc8280-usb",
"fsl,cpm2-usb";
reg = <11b60 18 8b00 100>;
reg = <0x11b60 0x18 0x8b00 0x100>;
interrupt-parent = <&PIC>;
interrupts = <b 8>;
fsl,cpm-command = <2e600000>;
interrupts = <11 8>;
fsl,cpm-command = <0x2e600000>;
};
};
PIC: interrupt-controller@10c00 {
#interrupt-cells = <2>;
interrupt-controller;
reg = <10c00 80>;
reg = <0x10c00 0x80>;
compatible = "fsl,mpc8280-pic", "fsl,cpm2-pic";
};

352
arch/powerpc/boot/dts/sbc8641d.dts Normal file
View File

@ -0,0 +1,352 @@
/*
* SBC8641D Device Tree Source
*
* Copyright 2008 Wind River Systems Inc.
*
* Paul Gortmaker (see MAINTAINERS for contact information)
*
* Based largely on the mpc8641_hpcn.dts by Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/dts-v1/;
/ {
model = "SBC8641D";
compatible = "wind,sbc8641";
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &enet0;
ethernet1 = &enet1;
ethernet2 = &enet2;
ethernet3 = &enet3;
serial0 = &serial0;
serial1 = &serial1;
pci0 = &pci0;
pci1 = &pci1;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8641@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <32>;
i-cache-line-size = <32>;
d-cache-size = <32768>; // L1
i-cache-size = <32768>; // L1
timebase-frequency = <0>; // From uboot
bus-frequency = <0>; // From uboot
clock-frequency = <0>; // From uboot
};
PowerPC,8641@1 {
device_type = "cpu";
reg = <1>;
d-cache-line-size = <32>;
i-cache-line-size = <32>;
d-cache-size = <32768>;
i-cache-size = <32768>;
timebase-frequency = <0>; // From uboot
bus-frequency = <0>; // From uboot
clock-frequency = <0>; // From uboot
};
};
memory {
device_type = "memory";
reg = <0x00000000 0x20000000>; // 512M at 0x0
};
localbus@f8005000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,mpc8641-localbus", "simple-bus";
reg = <0xf8005000 0x1000>;
interrupts = <19 2>;
interrupt-parent = <&mpic>;
ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
1 0 0xf0000000 0x00010000 // 64KB EEPROM
2 0 0xf1000000 0x00100000 // EPLD (1MB)
3 0 0xe0000000 0x04000000 // 64MB LB SDRAM (CS3)
4 0 0xe4000000 0x04000000 // 64MB LB SDRAM (CS4)
6 0 0xf4000000 0x00100000 // LCD display (1MB)
7 0 0xe8000000 0x04000000>; // 64MB OneNAND
flash@0,0 {
compatible = "cfi-flash";
reg = <0 0 0x01000000>;
bank-width = <2>;
device-width = <2>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "dtb";
reg = <0x00000000 0x00100000>;
read-only;
};
partition@300000 {
label = "kernel";
reg = <0x00100000 0x00400000>;
read-only;
};
partition@400000 {
label = "fs";
reg = <0x00500000 0x00a00000>;
};
partition@700000 {
label = "firmware";
reg = <0x00f00000 0x00100000>;
read-only;
};
};
epld@2,0 {
compatible = "wrs,epld-localbus";
#address-cells = <2>;
#size-cells = <1>;
reg = <2 0 0x100000>;
ranges = <0 0 5 0 1 // User switches
1 0 5 1 1 // Board ID/Rev
3 0 5 3 1>; // LEDs
};
};
soc@f8000000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "simple-bus";
ranges = <0x00000000 0xf8000000 0x00100000>;
reg = <0xf8000000 0x00001000>; // CCSRBAR
bus-frequency = <0>;
i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
reg = <0x3000 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
};
i2c@3100 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
compatible = "fsl-i2c";
reg = <0x3100 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
};
mdio@24520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
reg = <0x24520 0x20>;
phy0: ethernet-phy@1f {
interrupt-parent = <&mpic>;
interrupts = <10 1>;
reg = <0x1f>;
device_type = "ethernet-phy";
};
phy1: ethernet-phy@0 {
interrupt-parent = <&mpic>;
interrupts = <10 1>;
reg = <0>;
device_type = "ethernet-phy";
};
phy2: ethernet-phy@1 {
interrupt-parent = <&mpic>;
interrupts = <10 1>;
reg = <1>;
device_type = "ethernet-phy";
};
phy3: ethernet-phy@2 {
interrupt-parent = <&mpic>;
interrupts = <10 1>;
reg = <2>;
device_type = "ethernet-phy";
};
};
enet0: ethernet@24000 {
cell-index = <0>;
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <29 2 30 2 34 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy0>;
phy-connection-type = "rgmii-id";
};
enet1: ethernet@25000 {
cell-index = <1>;
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <0x25000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <35 2 36 2 40 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy1>;
phy-connection-type = "rgmii-id";
};
enet2: ethernet@26000 {
cell-index = <2>;
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <0x26000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <31 2 32 2 33 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy2>;
phy-connection-type = "rgmii-id";
};
enet3: ethernet@27000 {
cell-index = <3>;
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <0x27000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <37 2 38 2 39 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy3>;
phy-connection-type = "rgmii-id";
};
serial0: serial@4500 {
cell-index = <0>;
device_type = "serial";
compatible = "ns16550";
reg = <0x4500 0x100>;
clock-frequency = <0>;
interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
serial1: serial@4600 {
cell-index = <1>;
device_type = "serial";
compatible = "ns16550";
reg = <0x4600 0x100>;
clock-frequency = <0>;
interrupts = <28 2>;
interrupt-parent = <&mpic>;
};
mpic: pic@40000 {
clock-frequency = <0>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0x40000 0x40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
};
global-utilities@e0000 {
compatible = "fsl,mpc8641-guts";
reg = <0xe0000 0x1000>;
fsl,has-rstcr;
};
};
pci0: pcie@f8008000 {
cell-index = <0>;
compatible = "fsl,mpc8641-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0xf8008000 0x1000>;
bus-range = <0x0 0xff>;
ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
interrupts = <24 2>;
interrupt-map-mask = <0xff00 0 0 7>;
interrupt-map = <
/* IDSEL 0x0 */
0x0000 0 0 1 &mpic 0 1
0x0000 0 0 2 &mpic 1 1
0x0000 0 0 3 &mpic 2 1
0x0000 0 0 4 &mpic 3 1
>;
pcie@0 {
reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <0x02000000 0x0 0x80000000
0x02000000 0x0 0x80000000
0x0 0x20000000
0x01000000 0x0 0x00000000
0x01000000 0x0 0x00000000
0x0 0x00100000>;
};
};
pci1: pcie@f8009000 {
cell-index = <1>;
compatible = "fsl,mpc8641-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0xf8009000 0x1000>;
bus-range = <0 0xff>;
ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
interrupts = <25 2>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0 */
0x0000 0 0 1 &mpic 4 1
0x0000 0 0 2 &mpic 5 1
0x0000 0 0 3 &mpic 6 1
0x0000 0 0 4 &mpic 7 1
>;
pcie@0 {
reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <0x02000000 0x0 0xa0000000
0x02000000 0x0 0xa0000000
0x0 0x20000000
0x01000000 0x0 0x00000000
0x01000000 0x0 0x00000000
0x0 0x00100000>;
};
};
};

9
arch/powerpc/boot/mpc52xx-psc.c
View File

@ -51,14 +51,9 @@ static unsigned char psc_getc(void)
int mpc5200_psc_console_init(void *devp, struct serial_console_data *scdp)
{
int n;
/* Get the base address of the psc registers */
n = getprop(devp, "virtual-reg", &psc, sizeof(psc));
if (n != sizeof(psc)) {
if (!dt_xlate_reg(devp, 0, (void *)&psc, NULL))
return -1;
}
if (dt_get_virtual_reg(devp, &psc, 1) < 1)
return -1;
scdp->open = psc_open;
scdp->putc = psc_putc;

10
arch/powerpc/boot/ns16550.c
View File

@ -55,15 +55,9 @@ static u8 ns16550_tstc(void)
int ns16550_console_init(void *devp, struct serial_console_data *scdp)
{
int n;
unsigned long reg_phys;
n = getprop(devp, "virtual-reg", &reg_base, sizeof(reg_base));
if (n != sizeof(reg_base)) {
if (!dt_xlate_reg(devp, 0, &reg_phys, NULL))
return -1;
reg_base = (void *)reg_phys;
}
if (dt_get_virtual_reg(devp, (void **)&reg_base, 1) < 1)
return -1;
n = getprop(devp, "reg-shift", &reg_shift, sizeof(reg_shift));
if (n != sizeof(reg_shift))

1
arch/powerpc/boot/ops.h
View File

@ -95,6 +95,7 @@ int dt_xlate_reg(void *node, int res, unsigned long *addr, unsigned long *size);
int dt_xlate_addr(void *node, u32 *buf, int buflen, unsigned long *xlated_addr);
int dt_is_compatible(void *node, const char *compat);
void dt_get_reg_format(void *node, u32 *naddr, u32 *nsize);
int dt_get_virtual_reg(void *node, void **addr, int nres);
static inline void *finddevice(const char *name)
{

8
arch/powerpc/configs/mpc8313_rdb_defconfig → arch/powerpc/configs/83xx/mpc8313_rdb_defconfig
View File

@ -1,7 +1,7 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.25-rc6
# Mon Mar 24 08:48:14 2008
# Fri Apr 11 11:10:09 2008
#
# CONFIG_PPC64 is not set
@ -196,6 +196,7 @@ CONFIG_PREEMPT_NONE=y
# CONFIG_PREEMPT is not set
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_MISC is not set
CONFIG_FORCE_MAX_ZONEORDER=11
# CONFIG_IOMMU_HELPER is not set
CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
CONFIG_ARCH_HAS_WALK_MEMORY=y
@ -360,7 +361,7 @@ CONFIG_MTD=y
CONFIG_MTD_PARTITIONS=y
# CONFIG_MTD_REDBOOT_PARTS is not set
# CONFIG_MTD_CMDLINE_PARTS is not set
# CONFIG_MTD_OF_PARTS is not set
CONFIG_MTD_OF_PARTS=y
#
# User Modules And Translation Layers
@ -436,7 +437,7 @@ CONFIG_MTD_NAND_IDS=y
# CONFIG_MTD_NAND_NANDSIM is not set
# CONFIG_MTD_NAND_PLATFORM is not set
# CONFIG_MTD_ALAUDA is not set
# CONFIG_MTD_NAND_FSL_ELBC is not set
CONFIG_MTD_NAND_FSL_ELBC=y
# CONFIG_MTD_ONENAND is not set
#
@ -1293,6 +1294,7 @@ CONFIG_PLIST=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_DMA=y
CONFIG_HAVE_LMB=y
#
# Kernel hacking

0
arch/powerpc/configs/mpc8315_rdb_defconfig → arch/powerpc/configs/83xx/mpc8315_rdb_defconfig
View File

0
arch/powerpc/configs/mpc832x_mds_defconfig → arch/powerpc/configs/83xx/mpc832x_mds_defconfig
View File

0
arch/powerpc/configs/mpc832x_rdb_defconfig → arch/powerpc/configs/83xx/mpc832x_rdb_defconfig
View File

0
arch/powerpc/configs/mpc834x_itx_defconfig → arch/powerpc/configs/83xx/mpc834x_itx_defconfig
View File

0
arch/powerpc/configs/mpc834x_itxgp_defconfig → arch/powerpc/configs/83xx/mpc834x_itxgp_defconfig
View File

0
arch/powerpc/configs/mpc834x_mds_defconfig → arch/powerpc/configs/83xx/mpc834x_mds_defconfig
View File

0
arch/powerpc/configs/mpc836x_mds_defconfig → arch/powerpc/configs/83xx/mpc836x_mds_defconfig
View File

0
arch/powerpc/configs/mpc837x_mds_defconfig → arch/powerpc/configs/83xx/mpc837x_mds_defconfig
View File

0
arch/powerpc/configs/mpc837x_rdb_defconfig → arch/powerpc/configs/83xx/mpc837x_rdb_defconfig
View File

0
arch/powerpc/configs/sbc834x_defconfig → arch/powerpc/configs/83xx/sbc834x_defconfig
View File

0
arch/powerpc/configs/ksi8560_defconfig → arch/powerpc/configs/85xx/ksi8560_defconfig
View File

0
arch/powerpc/configs/mpc8540_ads_defconfig → arch/powerpc/configs/85xx/mpc8540_ads_defconfig
View File

17
arch/powerpc/configs/mpc8544_ds_defconfig → arch/powerpc/configs/85xx/mpc8544_ds_defconfig
View File

@ -162,6 +162,7 @@ CONFIG_MPC85xx=y
# CONFIG_MPC85xx_CDS is not set
# CONFIG_MPC85xx_MDS is not set
CONFIG_MPC85xx_DS=y
# CONFIG_KSI8560 is not set
# CONFIG_STX_GP3 is not set
# CONFIG_TQM8540 is not set
# CONFIG_TQM8541 is not set
@ -202,6 +203,7 @@ CONFIG_PREEMPT_NONE=y
# CONFIG_PREEMPT is not set
CONFIG_BINFMT_ELF=y
CONFIG_BINFMT_MISC=m
CONFIG_FORCE_MAX_ZONEORDER=11
CONFIG_MATH_EMULATION=y
# CONFIG_IOMMU_HELPER is not set
CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
@ -1255,7 +1257,19 @@ CONFIG_RTC_DRV_CMOS=y
#
# on-CPU RTC drivers
#
# CONFIG_DMADEVICES is not set
CONFIG_DMADEVICES=y
#
# DMA Devices
#
CONFIG_FSL_DMA=y
# CONFIG_FSL_DMA_SELFTEST is not set
CONFIG_DMA_ENGINE=y
#
# DMA Clients
#
# CONFIG_NET_DMA is not set
#
# Userspace I/O
@ -1447,6 +1461,7 @@ CONFIG_PLIST=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_DMA=y
CONFIG_HAVE_LMB=y
#
# Kernel hacking

0
arch/powerpc/configs/mpc8560_ads_defconfig → arch/powerpc/configs/85xx/mpc8560_ads_defconfig
View File

0
arch/powerpc/configs/mpc8568mds_defconfig → arch/powerpc/configs/85xx/mpc8568mds_defconfig
View File

0
arch/powerpc/configs/mpc8572_ds_defconfig → arch/powerpc/configs/85xx/mpc8572_ds_defconfig
View File

0
arch/powerpc/configs/mpc85xx_cds_defconfig → arch/powerpc/configs/85xx/mpc85xx_cds_defconfig
View File

0
arch/powerpc/configs/sbc8548_defconfig → arch/powerpc/configs/85xx/sbc8548_defconfig
View File

0
arch/powerpc/configs/sbc8560_defconfig → arch/powerpc/configs/85xx/sbc8560_defconfig
View File

0
arch/powerpc/configs/stx_gp3_defconfig → arch/powerpc/configs/85xx/stx_gp3_defconfig
View File

0
arch/powerpc/configs/tqm8540_defconfig → arch/powerpc/configs/85xx/tqm8540_defconfig
View File

0
arch/powerpc/configs/tqm8541_defconfig → arch/powerpc/configs/85xx/tqm8541_defconfig
View File

0
arch/powerpc/configs/tqm8555_defconfig → arch/powerpc/configs/85xx/tqm8555_defconfig
View File

0
arch/powerpc/configs/tqm8560_defconfig → arch/powerpc/configs/85xx/tqm8560_defconfig
View File

164
arch/powerpc/configs/mpc83xx_defconfig
View File

@ -1,7 +1,7 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.25-rc6
# Mon Mar 24 08:48:25 2008
# Linux kernel version: 2.6.25-rc9
# Tue Apr 15 18:07:36 2008
#
# CONFIG_PPC64 is not set
@ -201,6 +201,7 @@ CONFIG_PREEMPT_NONE=y
# CONFIG_PREEMPT is not set
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_MISC is not set
CONFIG_FORCE_MAX_ZONEORDER=11
CONFIG_MATH_EMULATION=y
# CONFIG_IOMMU_HELPER is not set
CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
@ -353,7 +354,90 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
# CONFIG_FW_LOADER is not set
# CONFIG_SYS_HYPERVISOR is not set
# CONFIG_CONNECTOR is not set
# CONFIG_MTD is not set
CONFIG_MTD=y
# CONFIG_MTD_DEBUG is not set
# CONFIG_MTD_CONCAT is not set
CONFIG_MTD_PARTITIONS=y
# CONFIG_MTD_REDBOOT_PARTS is not set
# CONFIG_MTD_CMDLINE_PARTS is not set
CONFIG_MTD_OF_PARTS=y
#
# User Modules And Translation Layers
#
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLKDEVS=y
CONFIG_MTD_BLOCK=y
# CONFIG_FTL is not set
# CONFIG_NFTL is not set
# CONFIG_INFTL is not set
# CONFIG_RFD_FTL is not set
# CONFIG_SSFDC is not set
# CONFIG_MTD_OOPS is not set
#
# RAM/ROM/Flash chip drivers
#
CONFIG_MTD_CFI=y
# CONFIG_MTD_JEDECPROBE is not set
CONFIG_MTD_GEN_PROBE=y
# CONFIG_MTD_CFI_ADV_OPTIONS is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y
CONFIG_MTD_MAP_BANK_WIDTH_2=y
CONFIG_MTD_MAP_BANK_WIDTH_4=y
# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
# CONFIG_MTD_CFI_I4 is not set
# CONFIG_MTD_CFI_I8 is not set
# CONFIG_MTD_CFI_INTELEXT is not set
CONFIG_MTD_CFI_AMDSTD=y
# CONFIG_MTD_CFI_STAA is not set
CONFIG_MTD_CFI_UTIL=y
# CONFIG_MTD_RAM is not set
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_ABSENT is not set
#
# Mapping drivers for chip access
#
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
# CONFIG_MTD_PHYSMAP is not set
CONFIG_MTD_PHYSMAP_OF=y
# CONFIG_MTD_PLATRAM is not set
#
# Self-contained MTD device drivers
#
# CONFIG_MTD_SLRAM is not set
# CONFIG_MTD_PHRAM is not set
# CONFIG_MTD_MTDRAM is not set
# CONFIG_MTD_BLOCK2MTD is not set
#
# Disk-On-Chip Device Drivers
#
# CONFIG_MTD_DOC2000 is not set
# CONFIG_MTD_DOC2001 is not set
# CONFIG_MTD_DOC2001PLUS is not set
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_VERIFY_WRITE=y
# CONFIG_MTD_NAND_ECC_SMC is not set
# CONFIG_MTD_NAND_MUSEUM_IDS is not set
CONFIG_MTD_NAND_IDS=y
# CONFIG_MTD_NAND_DISKONCHIP is not set
# CONFIG_MTD_NAND_NANDSIM is not set
# CONFIG_MTD_NAND_PLATFORM is not set
# CONFIG_MTD_ALAUDA is not set
CONFIG_MTD_NAND_FSL_ELBC=y
# CONFIG_MTD_ONENAND is not set
#
# UBI - Unsorted block images
#
# CONFIG_MTD_UBI is not set
CONFIG_OF_DEVICE=y
# CONFIG_PARPORT is not set
CONFIG_BLK_DEV=y
@ -362,6 +446,7 @@ CONFIG_BLK_DEV=y
CONFIG_BLK_DEV_LOOP=y
# CONFIG_BLK_DEV_CRYPTOLOOP is not set
# CONFIG_BLK_DEV_NBD is not set
# CONFIG_BLK_DEV_UB is not set
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=32768
@ -469,6 +554,15 @@ CONFIG_NETDEV_10000=y
#
# CONFIG_WLAN_PRE80211 is not set
# CONFIG_WLAN_80211 is not set
#
# USB Network Adapters
#
# CONFIG_USB_CATC is not set
# CONFIG_USB_KAWETH is not set
# CONFIG_USB_PEGASUS is not set
# CONFIG_USB_RTL8150 is not set
# CONFIG_USB_USBNET is not set
# CONFIG_WAN is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
@ -563,6 +657,7 @@ CONFIG_I2C_MPC=y
# CONFIG_I2C_SIMTEC is not set
# CONFIG_I2C_TAOS_EVM is not set
# CONFIG_I2C_STUB is not set
# CONFIG_I2C_TINY_USB is not set
#
# Miscellaneous I2C Chip support
@ -647,6 +742,11 @@ CONFIG_WATCHDOG=y
# CONFIG_SOFT_WATCHDOG is not set
CONFIG_83xx_WDT=y
#
# USB-based Watchdog Cards
#
# CONFIG_USBPCWATCHDOG is not set
#
# Sonics Silicon Backplane
#
@ -664,6 +764,7 @@ CONFIG_SSB_POSSIBLE=y
# CONFIG_VIDEO_DEV is not set
# CONFIG_DVB_CORE is not set
CONFIG_DAB=y
# CONFIG_USB_DABUSB is not set
#
# Graphics support
@ -686,6 +787,14 @@ CONFIG_HID_SUPPORT=y
CONFIG_HID=y
# CONFIG_HID_DEBUG is not set
# CONFIG_HIDRAW is not set
#
# USB Input Devices
#
CONFIG_USB_HID=y
# CONFIG_USB_HIDINPUT_POWERBOOK is not set
# CONFIG_HID_FF is not set
# CONFIG_USB_HIDDEV is not set
CONFIG_USB_SUPPORT=y
CONFIG_USB_ARCH_HAS_HCD=y
# CONFIG_USB_ARCH_HAS_OHCI is not set
@ -714,9 +823,56 @@ CONFIG_USB_EHCI_HCD_PPC_OF=y
# CONFIG_USB_SL811_HCD is not set
# CONFIG_USB_R8A66597_HCD is not set
#
# USB Device Class drivers
#
# CONFIG_USB_ACM is not set
# CONFIG_USB_PRINTER is not set
#
# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
#
#
# may also be needed; see USB_STORAGE Help for more information
#
# CONFIG_USB_STORAGE is not set
# CONFIG_USB_LIBUSUAL is not set
#
# USB Imaging devices
#
# CONFIG_USB_MDC800 is not set
# CONFIG_USB_MICROTEK is not set
CONFIG_USB_MON=y
#
# USB port drivers
#
# CONFIG_USB_SERIAL is not set
#
# USB Miscellaneous drivers
#
# CONFIG_USB_EMI62 is not set
# CONFIG_USB_EMI26 is not set
# CONFIG_USB_ADUTUX is not set
# CONFIG_USB_AUERSWALD is not set
# CONFIG_USB_RIO500 is not set
# CONFIG_USB_LEGOTOWER is not set
# CONFIG_USB_LCD is not set
# CONFIG_USB_BERRY_CHARGE is not set
# CONFIG_USB_LED is not set
# CONFIG_USB_CYPRESS_CY7C63 is not set
# CONFIG_USB_CYTHERM is not set
# CONFIG_USB_PHIDGET is not set
# CONFIG_USB_IDMOUSE is not set
# CONFIG_USB_FTDI_ELAN is not set
# CONFIG_USB_APPLEDISPLAY is not set
# CONFIG_USB_SISUSBVGA is not set
# CONFIG_USB_LD is not set
# CONFIG_USB_TRANCEVIBRATOR is not set
# CONFIG_USB_IOWARRIOR is not set
# CONFIG_USB_GADGET is not set
# CONFIG_MMC is not set
# CONFIG_MEMSTICK is not set
@ -792,6 +948,7 @@ CONFIG_TMPFS=y
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
# CONFIG_JFFS2_FS is not set
# CONFIG_CRAMFS is not set
# CONFIG_VXFS_FS is not set
# CONFIG_MINIX_FS is not set
@ -862,6 +1019,7 @@ CONFIG_PLIST=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_DMA=y
CONFIG_HAVE_LMB=y
#
# Kernel hacking

1342
arch/powerpc/configs/sbc8641d_defconfig Normal file
View File

File diff suppressed because it is too large Load Diff

30
arch/powerpc/kernel/entry_32.S
View File

@ -110,9 +110,9 @@ transfer_to_handler:
stw r11,PT_REGS(r12)
#if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
/* Check to see if the dbcr0 register is set up to debug. Use the
single-step bit to do this. */
internal debug mode bit to do this. */
lwz r12,THREAD_DBCR0(r12)
andis. r12,r12,DBCR0_IC@h
andis. r12,r12,DBCR0_IDM@h
beq+ 3f
/* From user and task is ptraced - load up global dbcr0 */
li r12,-1 /* clear all pending debug events */
@ -120,6 +120,12 @@ transfer_to_handler:
lis r11,global_dbcr0@ha
tophys(r11,r11)
addi r11,r11,global_dbcr0@l
#ifdef CONFIG_SMP
rlwinm r9,r1,0,0,(31-THREAD_SHIFT)
lwz r9,TI_CPU(r9)
slwi r9,r9,3
add r11,r11,r9
#endif
lwz r12,0(r11)
mtspr SPRN_DBCR0,r12
lwz r12,4(r11)
@ -238,10 +244,10 @@ ret_from_syscall:
stw r11,_CCR(r1)
syscall_exit_cont:
#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
/* If the process has its own DBCR0 value, load it up. The single
step bit tells us that dbcr0 should be loaded. */
/* If the process has its own DBCR0 value, load it up. The internal
debug mode bit tells us that dbcr0 should be loaded. */
lwz r0,THREAD+THREAD_DBCR0(r2)
andis. r10,r0,DBCR0_IC@h
andis. r10,r0,DBCR0_IDM@h
bnel- load_dbcr0
#endif
#ifdef CONFIG_44x
@ -666,10 +672,10 @@ user_exc_return: /* r10 contains MSR_KERNEL here */
restore_user:
#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
/* Check whether this process has its own DBCR0 value. The single
step bit tells us that dbcr0 should be loaded. */
/* Check whether this process has its own DBCR0 value. The internal
debug mode bit tells us that dbcr0 should be loaded. */
lwz r0,THREAD+THREAD_DBCR0(r2)
andis. r10,r0,DBCR0_IC@h
andis. r10,r0,DBCR0_IDM@h
bnel- load_dbcr0
#endif
@ -879,6 +885,12 @@ load_dbcr0:
mfspr r10,SPRN_DBCR0
lis r11,global_dbcr0@ha
addi r11,r11,global_dbcr0@l
#ifdef CONFIG_SMP
rlwinm r9,r1,0,0,(31-THREAD_SHIFT)
lwz r9,TI_CPU(r9)
slwi r9,r9,3
add r11,r11,r9
#endif
stw r10,0(r11)
mtspr SPRN_DBCR0,r0
lwz r10,4(r11)
@ -891,7 +903,7 @@ load_dbcr0:
.section .bss
.align 4
global_dbcr0:
.space 8
.space 8*NR_CPUS
.previous
#endif /* !(CONFIG_4xx || CONFIG_BOOKE) */

4
arch/powerpc/kernel/head_44x.S
View File

@ -211,7 +211,7 @@ skpinv: addi r4,r4,1 /* Increment */
SET_IVOR(12, WatchdogTimer);
SET_IVOR(13, DataTLBError);
SET_IVOR(14, InstructionTLBError);
SET_IVOR(15, Debug);
SET_IVOR(15, DebugCrit);
/* Establish the interrupt vector base */
lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */
@ -578,7 +578,7 @@ interrupt_base:
b InstructionStorage
/* Debug Interrupt */
DEBUG_EXCEPTION
DEBUG_CRIT_EXCEPTION
/*
* Local functions

33
arch/powerpc/kernel/head_booke.h
View File

@ -56,8 +56,17 @@
* is necessary since the MMU is always on, for Book-E parts, and the stacks
* are offset from KERNELBASE.
*
* There is some space optimization to be had here if desired. However
* to allow for a common kernel with support for debug exceptions either
* going to critical or their own debug level we aren't currently
* providing configurations that micro-optimize space usage.
*/
#define BOOKE_EXCEPTION_STACK_SIZE (8192)
#ifdef CONFIG_44x
#define NUM_EXCEPTION_LVLS 2
#else
#define NUM_EXCEPTION_LVLS 3
#endif
#define BOOKE_EXCEPTION_STACK_SIZE (4096 * NUM_EXCEPTION_LVLS)
/* CRIT_SPRG only used in critical exception handling */
#define CRIT_SPRG SPRN_SPRG2
@ -68,7 +77,7 @@
#define CRIT_STACK_TOP (exception_stack_top)
/* only on e200 for now */
#define DEBUG_STACK_TOP (exception_stack_top - 4096)
#define DEBUG_STACK_TOP (exception_stack_top - 8192)
#define DEBUG_SPRG SPRN_SPRG6W
#ifdef CONFIG_SMP
@ -212,9 +221,8 @@
* save (and later restore) the MSR via SPRN_CSRR1, which will still have
* the MSR_DE bit set.
*/
#ifdef CONFIG_E200
#define DEBUG_EXCEPTION \
START_EXCEPTION(Debug); \
#define DEBUG_DEBUG_EXCEPTION \
START_EXCEPTION(DebugDebug); \
DEBUG_EXCEPTION_PROLOG; \
\
/* \
@ -234,8 +242,8 @@
cmplw r12,r10; \
blt+ 2f; /* addr below exception vectors */ \
\
lis r10,Debug@h; \
ori r10,r10,Debug@l; \
lis r10,DebugDebug@h; \
ori r10,r10,DebugDebug@l; \
cmplw r12,r10; \
bgt+ 2f; /* addr above exception vectors */ \
\
@ -265,9 +273,9 @@
2: mfspr r4,SPRN_DBSR; \
addi r3,r1,STACK_FRAME_OVERHEAD; \
EXC_XFER_TEMPLATE(DebugException, 0x2002, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), NOCOPY, debug_transfer_to_handler, ret_from_debug_exc)
#else
#define DEBUG_EXCEPTION \
START_EXCEPTION(Debug); \
#define DEBUG_CRIT_EXCEPTION \
START_EXCEPTION(DebugCrit); \
CRITICAL_EXCEPTION_PROLOG; \
\
/* \
@ -287,8 +295,8 @@
cmplw r12,r10; \
blt+ 2f; /* addr below exception vectors */ \
\
lis r10,Debug@h; \
ori r10,r10,Debug@l; \
lis r10,DebugCrit@h; \
ori r10,r10,DebugCrit@l; \
cmplw r12,r10; \
bgt+ 2f; /* addr above exception vectors */ \
\
@ -318,7 +326,6 @@
2: mfspr r4,SPRN_DBSR; \
addi r3,r1,STACK_FRAME_OVERHEAD; \
EXC_XFER_TEMPLATE(DebugException, 0x2002, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), NOCOPY, crit_transfer_to_handler, ret_from_crit_exc)
#endif
#define INSTRUCTION_STORAGE_EXCEPTION \
START_EXCEPTION(InstructionStorage) \

10
arch/powerpc/kernel/head_fsl_booke.S
View File

@ -303,7 +303,10 @@ skpinv: addi r6,r6,1 /* Increment */
SET_IVOR(12, WatchdogTimer);
SET_IVOR(13, DataTLBError);
SET_IVOR(14, InstructionTLBError);
SET_IVOR(15, Debug);
SET_IVOR(15, DebugDebug);
#if defined(CONFIG_E500)
SET_IVOR(15, DebugCrit);
#endif
SET_IVOR(32, SPEUnavailable);
SET_IVOR(33, SPEFloatingPointData);
SET_IVOR(34, SPEFloatingPointRound);
@ -738,7 +741,10 @@ interrupt_base:
/* Debug Interrupt */
DEBUG_EXCEPTION
DEBUG_DEBUG_EXCEPTION
#if defined(CONFIG_E500)
DEBUG_CRIT_EXCEPTION
#endif
/*
* Local functions

4
arch/powerpc/lib/rheap.c
View File

@ -54,7 +54,7 @@ static int grow(rh_info_t * info, int max_blocks)
new_blocks = max_blocks - info->max_blocks;
block = kmalloc(sizeof(rh_block_t) * max_blocks, GFP_KERNEL);
block = kmalloc(sizeof(rh_block_t) * max_blocks, GFP_ATOMIC);
if (block == NULL)
return -ENOMEM;
@ -258,7 +258,7 @@ rh_info_t *rh_create(unsigned int alignment)
if ((alignment & (alignment - 1)) != 0)
return ERR_PTR(-EINVAL);
info = kmalloc(sizeof(*info), GFP_KERNEL);
info = kmalloc(sizeof(*info), GFP_ATOMIC);
if (info == NULL)
return ERR_PTR(-ENOMEM);

3
arch/powerpc/platforms/82xx/Kconfig
View File

@ -11,7 +11,6 @@ config MPC8272_ADS
select 8260
select FSL_SOC
select PQ2_ADS_PCI_PIC if PCI
select PPC_CPM_NEW_BINDING
help
This option enables support for the MPC8272 ADS board
@ -22,7 +21,6 @@ config PQ2FADS
select 8260
select FSL_SOC
select PQ2_ADS_PCI_PIC if PCI
select PPC_CPM_NEW_BINDING
help
This option enables support for the PQ2FADS board
@ -31,7 +29,6 @@ config EP8248E
select 8272
select 8260
select FSL_SOC
select PPC_CPM_NEW_BINDING
select MDIO_BITBANG
help
This enables support for the Embedded Planet EP8248E board.

1
arch/powerpc/platforms/83xx/mpc837x_rdb.c
View File

@ -46,6 +46,7 @@ static void __init mpc837x_rdb_setup_arch(void)
static struct of_device_id mpc837x_ids[] = {
{ .type = "soc", },
{ .compatible = "soc", },
{ .compatible = "simple-bus", },
{},
};

2
arch/powerpc/platforms/83xx/mpc83xx.h
View File

@ -16,6 +16,7 @@
#define MPC83XX_SCCR_USB_DRCM_10 0x00200000
#define MPC8315_SCCR_USB_MASK 0x00c00000
#define MPC8315_SCCR_USB_DRCM_11 0x00c00000
#define MPC8315_SCCR_USB_DRCM_01 0x00400000
#define MPC837X_SCCR_USB_DRCM_11 0x00c00000
/* system i/o configuration register low */
@ -37,6 +38,7 @@
/* USB Control Register */
#define FSL_USB2_CONTROL_OFFS 0x500
#define CONTROL_UTMI_PHY_EN 0x00000200
#define CONTROL_REFSEL_24MHZ 0x00000040
#define CONTROL_REFSEL_48MHZ 0x00000080
#define CONTROL_PHY_CLK_SEL_ULPI 0x00000400
#define CONTROL_OTG_PORT 0x00000020

12
arch/powerpc/platforms/83xx/usb.c
View File

@ -129,7 +129,7 @@ int mpc831x_usb_cfg(void)
if (immr_node && of_device_is_compatible(immr_node, "fsl,mpc8315-immr"))
clrsetbits_be32(immap + MPC83XX_SCCR_OFFS,
MPC8315_SCCR_USB_MASK,
MPC8315_SCCR_USB_DRCM_11);
MPC8315_SCCR_USB_DRCM_01);
else
clrsetbits_be32(immap + MPC83XX_SCCR_OFFS,
MPC83XX_SCCR_USB_MASK,
@ -164,9 +164,15 @@ int mpc831x_usb_cfg(void)
/* Using on-chip PHY */
if (prop && (!strcmp(prop, "utmi_wide") ||
!strcmp(prop, "utmi"))) {
/* Set UTMI_PHY_EN, REFSEL to 48MHZ */
u32 refsel;
if (of_device_is_compatible(immr_node, "fsl,mpc8315-immr"))
refsel = CONTROL_REFSEL_24MHZ;
else
refsel = CONTROL_REFSEL_48MHZ;
/* Set UTMI_PHY_EN and REFSEL */
out_be32(usb_regs + FSL_USB2_CONTROL_OFFS,
CONTROL_UTMI_PHY_EN | CONTROL_REFSEL_48MHZ);
CONTROL_UTMI_PHY_EN | refsel);
/* Using external UPLI PHY */
} else if (prop && !strcmp(prop, "ulpi")) {
/* Set PHY_CLK_SEL to ULPI */

8
arch/powerpc/platforms/85xx/Kconfig
View File

@ -19,7 +19,6 @@ config MPC8540_ADS
config MPC8560_ADS
bool "Freescale MPC8560 ADS"
select DEFAULT_UIMAGE
select PPC_CPM_NEW_BINDING
select CPM2
help
This option enables support for the MPC 8560 ADS board
@ -48,7 +47,6 @@ config MPC85xx_DS
config KSI8560
bool "Emerson KSI8560"
select PPC_CPM_NEW_BINDING
select DEFAULT_UIMAGE
help
This option enables support for the Emerson KSI8560 board
@ -60,14 +58,12 @@ config STX_GP3
board.
select CPM2
select DEFAULT_UIMAGE
select PPC_CPM_NEW_BINDING
config TQM8540
bool "TQ Components TQM8540"
help
This option enables support for the TQ Components TQM8540 board.
select DEFAULT_UIMAGE
select PPC_CPM_NEW_BINDING
select TQM85xx
config TQM8541
@ -75,7 +71,6 @@ config TQM8541
help
This option enables support for the TQ Components TQM8541 board.
select DEFAULT_UIMAGE
select PPC_CPM_NEW_BINDING
select TQM85xx
select CPM2
@ -84,7 +79,6 @@ config TQM8555
help
This option enables support for the TQ Components TQM8555 board.
select DEFAULT_UIMAGE
select PPC_CPM_NEW_BINDING
select TQM85xx
select CPM2
@ -93,7 +87,6 @@ config TQM8560
help
This option enables support for the TQ Components TQM8560 board.
select DEFAULT_UIMAGE
select PPC_CPM_NEW_BINDING
select TQM85xx
select CPM2
@ -106,7 +99,6 @@ config SBC8548
config SBC8560
bool "Wind River SBC8560"
select DEFAULT_UIMAGE
select PPC_CPM_NEW_BINDING if CPM2
help
This option enables support for the Wind River SBC8560 board

2
arch/powerpc/platforms/85xx/mpc85xx_ads.c
View File

@ -165,7 +165,7 @@ static void __init init_ioports(void)
int i;
for (i = 0; i < ARRAY_SIZE(mpc8560_ads_pins); i++) {
struct cpm_pin *pin = &mpc8560_ads_pins[i];
const struct cpm_pin *pin = &mpc8560_ads_pins[i];
cpm2_set_pin(pin->port, pin->pin, pin->flags);
}

13
arch/powerpc/platforms/85xx/mpc85xx_ds.c
View File

@ -19,6 +19,7 @@
#include <linux/delay.h>
#include <linux/seq_file.h>
#include <linux/interrupt.h>
#include <linux/of_platform.h>
#include <asm/system.h>
#include <asm/time.h>
@ -183,6 +184,18 @@ static int __init mpc8544_ds_probe(void)
}
}
static struct of_device_id mpc85xxds_ids[] = {
{ .type = "soc", },
{ .compatible = "soc", },
{},
};
static int __init mpc85xxds_publish_devices(void)
{
return of_platform_bus_probe(NULL, mpc85xxds_ids, NULL);
}
machine_device_initcall(mpc8544_ds, mpc85xxds_publish_devices);
/*
* Called very early, device-tree isn't unflattened
*/

8
arch/powerpc/platforms/86xx/Kconfig
View File

@ -11,6 +11,12 @@ config MPC8641_HPCN
help
This option enables support for the MPC8641 HPCN board.
config SBC8641D
bool "Wind River SBC8641D"
select DEFAULT_UIMAGE
help
This option enables support for the WRS SBC8641D board.
config MPC8610_HPCD
bool "Freescale MPC8610 HPCD"
select DEFAULT_UIMAGE
@ -24,7 +30,7 @@ config MPC8641
select FSL_PCI if PCI
select PPC_UDBG_16550
select MPIC
default y if MPC8641_HPCN
default y if MPC8641_HPCN || SBC8641D
config MPC8610
bool

1
arch/powerpc/platforms/86xx/Makefile
View File

@ -4,4 +4,5 @@
obj-$(CONFIG_SMP) += mpc86xx_smp.o
obj-$(CONFIG_MPC8641_HPCN) += mpc86xx_hpcn.o
obj-$(CONFIG_SBC8641D) += sbc8641d.o
obj-$(CONFIG_MPC8610_HPCD) += mpc8610_hpcd.o

4
arch/powerpc/platforms/86xx/mpc8610_hpcd.c
View File

@ -52,7 +52,7 @@ static int __init mpc8610_declare_of_platform_devices(void)
}
machine_device_initcall(mpc86xx_hpcd, mpc8610_declare_of_platform_devices);
void __init
static void __init
mpc86xx_hpcd_init_irq(void)
{
struct mpic *mpic1;
@ -200,7 +200,7 @@ static int __init mpc86xx_hpcd_probe(void)
return 0;
}
long __init
static long __init
mpc86xx_time_init(void)
{
unsigned int temp;

14
arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
View File

@ -55,7 +55,7 @@ static void mpc86xx_8259_cascade(unsigned int irq, struct irq_desc *desc)
}
#endif /* CONFIG_PCI */
void __init
static void __init
mpc86xx_hpcn_init_irq(void)
{
struct mpic *mpic1;
@ -162,7 +162,7 @@ mpc86xx_hpcn_setup_arch(void)
}
void
static void
mpc86xx_hpcn_show_cpuinfo(struct seq_file *m)
{
struct device_node *root;
@ -190,13 +190,19 @@ static int __init mpc86xx_hpcn_probe(void)
{
unsigned long root = of_get_flat_dt_root();
if (of_flat_dt_is_compatible(root, "mpc86xx"))
if (of_flat_dt_is_compatible(root, "fsl,mpc8641hpcn"))
return 1; /* Looks good */
/* Be nice and don't give silent boot death. Delete this in 2.6.27 */
if (of_flat_dt_is_compatible(root, "mpc86xx")) {
pr_warning("WARNING: your dts/dtb is old. You must update before the next kernel release\n");
return 1;
}
return 0;
}
long __init
static long __init
mpc86xx_time_init(void)
{
unsigned int temp;

164
arch/powerpc/platforms/86xx/sbc8641d.c Normal file
View File

@ -0,0 +1,164 @@
/*
* SBC8641D board specific routines
*
* Copyright 2008 Wind River Systems Inc.
*
* By Paul Gortmaker (see MAINTAINERS for contact information)
*
* Based largely on the 8641 HPCN support by Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/stddef.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/kdev_t.h>
#include <linux/delay.h>
#include <linux/seq_file.h>
#include <linux/of_platform.h>
#include <asm/system.h>
#include <asm/time.h>
#include <asm/machdep.h>
#include <asm/pci-bridge.h>
#include <asm/mpc86xx.h>
#include <asm/prom.h>
#include <mm/mmu_decl.h>
#include <asm/udbg.h>
#include <asm/mpic.h>
#include <sysdev/fsl_pci.h>
#include <sysdev/fsl_soc.h>
#include "mpc86xx.h"
static void __init
sbc8641_init_irq(void)
{
struct mpic *mpic1;
struct device_node *np;
struct resource res;
/* Determine PIC address. */
np = of_find_node_by_type(NULL, "open-pic");
if (np == NULL)
return;
of_address_to_resource(np, 0, &res);
/* Alloc mpic structure and per isu has 16 INT entries. */
mpic1 = mpic_alloc(np, res.start,
MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
0, 256, " MPIC ");
of_node_put(np);
BUG_ON(mpic1 == NULL);
mpic_init(mpic1);
}
static void __init
sbc8641_setup_arch(void)
{
#ifdef CONFIG_PCI
struct device_node *np;
#endif
if (ppc_md.progress)
ppc_md.progress("sbc8641_setup_arch()", 0);
#ifdef CONFIG_PCI
for_each_compatible_node(np, "pci", "fsl,mpc8641-pcie")
fsl_add_bridge(np, 0);
#endif
printk("SBC8641 board from Wind River\n");
#ifdef CONFIG_SMP
mpc86xx_smp_init();
#endif
}
static void
sbc8641_show_cpuinfo(struct seq_file *m)
{
struct device_node *root;
uint memsize = total_memory;
const char *model = "";
uint svid = mfspr(SPRN_SVR);
seq_printf(m, "Vendor\t\t: Wind River Systems\n");
root = of_find_node_by_path("/");
if (root)
model = of_get_property(root, "model", NULL);
seq_printf(m, "Machine\t\t: %s\n", model);
of_node_put(root);
seq_printf(m, "SVR\t\t: 0x%x\n", svid);
seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
}
/*
* Called very early, device-tree isn't unflattened
*/
static int __init sbc8641_probe(void)
{
unsigned long root = of_get_flat_dt_root();
if (of_flat_dt_is_compatible(root, "wind,sbc8641"))
return 1; /* Looks good */
return 0;
}
static long __init
mpc86xx_time_init(void)
{
unsigned int temp;
/* Set the time base to zero */
mtspr(SPRN_TBWL, 0);
mtspr(SPRN_TBWU, 0);
temp = mfspr(SPRN_HID0);
temp |= HID0_TBEN;
mtspr(SPRN_HID0, temp);
asm volatile("isync");
return 0;
}
static __initdata struct of_device_id of_bus_ids[] = {
{ .compatible = "simple-bus", },
{},
};
static int __init declare_of_platform_devices(void)
{
of_platform_bus_probe(NULL, of_bus_ids, NULL);
return 0;
}
machine_device_initcall(sbc8641, declare_of_platform_devices);
define_machine(sbc8641) {
.name = "SBC8641D",
.probe = sbc8641_probe,
.setup_arch = sbc8641_setup_arch,
.init_IRQ = sbc8641_init_irq,
.show_cpuinfo = sbc8641_show_cpuinfo,
.get_irq = mpic_get_irq,
.restart = fsl_rstcr_restart,
.time_init = mpc86xx_time_init,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
#ifdef CONFIG_PCI
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
#endif
};

4
arch/powerpc/platforms/8xx/Kconfig
View File

@ -18,7 +18,6 @@ config MPC8XXFADS
config MPC86XADS
bool "MPC86XADS"
select CPM1
select PPC_CPM_NEW_BINDING
help
MPC86x Application Development System by Freescale Semiconductor.
The MPC86xADS is meant to serve as a platform for s/w and h/w
@ -27,7 +26,6 @@ config MPC86XADS
config MPC885ADS
bool "MPC885ADS"
select CPM1
select PPC_CPM_NEW_BINDING
help
Freescale Semiconductor MPC885 Application Development System (ADS).
Also known as DUET.
@ -37,7 +35,6 @@ config MPC885ADS
config PPC_EP88XC
bool "Embedded Planet EP88xC (a.k.a. CWH-PPC-885XN-VE)"
select CPM1
select PPC_CPM_NEW_BINDING
help
This enables support for the Embedded Planet EP88xC board.
@ -47,7 +44,6 @@ config PPC_EP88XC
config PPC_ADDER875
bool "Analogue & Micro Adder 875"
select CPM1
select PPC_CPM_NEW_BINDING
select REDBOOT
help
This enables support for the Analogue & Micro Adder 875

8
arch/powerpc/platforms/Kconfig
View File

@ -290,13 +290,7 @@ config CPM2
config PPC_CPM_NEW_BINDING
bool
depends on CPM1 || CPM2
help
Select this if your board has been converted to use the new
device tree bindings for CPM, and no longer needs the
ioport callbacks or the platform device glue code.
The fs_enet and cpm_uart drivers will be built as
of_platform devices.
default y
config AXON_RAM
tristate "Axon DDR2 memory device driver"

1
arch/powerpc/sysdev/Makefile
View File

@ -12,6 +12,7 @@ obj-$(CONFIG_U3_DART) += dart_iommu.o
obj-$(CONFIG_MMIO_NVRAM) += mmio_nvram.o
obj-$(CONFIG_FSL_SOC) += fsl_soc.o
obj-$(CONFIG_FSL_PCI) += fsl_pci.o
obj-$(CONFIG_FSL_LBC) += fsl_lbc.o
obj-$(CONFIG_RAPIDIO) += fsl_rio.o
obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o
obj-$(CONFIG_QUICC_ENGINE) += qe_lib/

112
arch/powerpc/sysdev/cpm1.c
View File

@ -44,9 +44,6 @@
#define CPM_MAP_SIZE (0x4000)
#ifndef CONFIG_PPC_CPM_NEW_BINDING
static void m8xx_cpm_dpinit(void);
#endif
cpm8xx_t __iomem *cpmp; /* Pointer to comm processor space */
immap_t __iomem *mpc8xx_immr;
static cpic8xx_t __iomem *cpic_reg;
@ -229,12 +226,7 @@ void __init cpm_reset(void)
out_be32(&siu_conf->sc_sdcr, 1);
immr_unmap(siu_conf);
#ifdef CONFIG_PPC_CPM_NEW_BINDING
cpm_muram_init();
#else
/* Reclaim the DP memory for our use. */
m8xx_cpm_dpinit();
#endif
}
static DEFINE_SPINLOCK(cmd_lock);
@ -293,110 +285,6 @@ cpm_setbrg(uint brg, uint rate)
CPM_BRG_EN | CPM_BRG_DIV16);
}
#ifndef CONFIG_PPC_CPM_NEW_BINDING
/*
* dpalloc / dpfree bits.
*/
static spinlock_t cpm_dpmem_lock;
/*
* 16 blocks should be enough to satisfy all requests
* until the memory subsystem goes up...
*/
static rh_block_t cpm_boot_dpmem_rh_block[16];
static rh_info_t cpm_dpmem_info;
#define CPM_DPMEM_ALIGNMENT 8
static u8 __iomem *dpram_vbase;
static phys_addr_t dpram_pbase;
static void m8xx_cpm_dpinit(void)
{
spin_lock_init(&cpm_dpmem_lock);
dpram_vbase = cpmp->cp_dpmem;
dpram_pbase = get_immrbase() + offsetof(immap_t, im_cpm.cp_dpmem);
/* Initialize the info header */
rh_init(&cpm_dpmem_info, CPM_DPMEM_ALIGNMENT,
sizeof(cpm_boot_dpmem_rh_block) /
sizeof(cpm_boot_dpmem_rh_block[0]),
cpm_boot_dpmem_rh_block);
/*
* Attach the usable dpmem area.
* XXX: This is actually crap. CPM_DATAONLY_BASE and
* CPM_DATAONLY_SIZE are a subset of the available dparm. It varies
* with the processor and the microcode patches applied / activated.
* But the following should be at least safe.
*/
rh_attach_region(&cpm_dpmem_info, CPM_DATAONLY_BASE, CPM_DATAONLY_SIZE);
}
/*
* Allocate the requested size worth of DP memory.
* This function returns an offset into the DPRAM area.
* Use cpm_dpram_addr() to get the virtual address of the area.
*/
unsigned long cpm_dpalloc(uint size, uint align)
{
unsigned long start;
unsigned long flags;
spin_lock_irqsave(&cpm_dpmem_lock, flags);
cpm_dpmem_info.alignment = align;
start = rh_alloc(&cpm_dpmem_info, size, "commproc");
spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
return (uint)start;
}
EXPORT_SYMBOL(cpm_dpalloc);
int cpm_dpfree(unsigned long offset)
{
int ret;
unsigned long flags;
spin_lock_irqsave(&cpm_dpmem_lock, flags);
ret = rh_free(&cpm_dpmem_info, offset);
spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
return ret;
}
EXPORT_SYMBOL(cpm_dpfree);
unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align)
{
unsigned long start;
unsigned long flags;
spin_lock_irqsave(&cpm_dpmem_lock, flags);
cpm_dpmem_info.alignment = align;
start = rh_alloc_fixed(&cpm_dpmem_info, offset, size, "commproc");
spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
return start;
}
EXPORT_SYMBOL(cpm_dpalloc_fixed);
void cpm_dpdump(void)
{
rh_dump(&cpm_dpmem_info);
}
EXPORT_SYMBOL(cpm_dpdump);
void *cpm_dpram_addr(unsigned long offset)
{
return (void *)(dpram_vbase + offset);
}
EXPORT_SYMBOL(cpm_dpram_addr);
uint cpm_dpram_phys(u8 *addr)
{
return (dpram_pbase + (uint)(addr - dpram_vbase));
}
EXPORT_SYMBOL(cpm_dpram_phys);
#endif /* !CONFIG_PPC_CPM_NEW_BINDING */
struct cpm_ioport16 {
__be16 dir, par, odr_sor, dat, intr;
__be16 res[3];

103
arch/powerpc/sysdev/cpm2.c
View File

@ -46,10 +46,6 @@
#include <sysdev/fsl_soc.h>
#ifndef CONFIG_PPC_CPM_NEW_BINDING
static void cpm2_dpinit(void);
#endif
cpm_cpm2_t __iomem *cpmp; /* Pointer to comm processor space */
/* We allocate this here because it is used almost exclusively for
@ -71,15 +67,17 @@ void __init cpm2_reset(void)
/* Reclaim the DP memory for our use.
*/
#ifdef CONFIG_PPC_CPM_NEW_BINDING
cpm_muram_init();
#else
cpm2_dpinit();
#endif
/* Tell everyone where the comm processor resides.
*/
cpmp = &cpm2_immr->im_cpm;
#ifndef CONFIG_PPC_EARLY_DEBUG_CPM
/* Reset the CPM.
*/
cpm_command(CPM_CR_RST, 0);
#endif
}
static DEFINE_SPINLOCK(cmd_lock);
@ -347,95 +345,6 @@ int cpm2_smc_clk_setup(enum cpm_clk_target target, int clock)
return ret;
}
#ifndef CONFIG_PPC_CPM_NEW_BINDING
/*
* dpalloc / dpfree bits.
*/
static spinlock_t cpm_dpmem_lock;
/* 16 blocks should be enough to satisfy all requests
* until the memory subsystem goes up... */
static rh_block_t cpm_boot_dpmem_rh_block[16];
static rh_info_t cpm_dpmem_info;
static u8 __iomem *im_dprambase;
static void cpm2_dpinit(void)
{
spin_lock_init(&cpm_dpmem_lock);
/* initialize the info header */
rh_init(&cpm_dpmem_info, 1,
sizeof(cpm_boot_dpmem_rh_block) /
sizeof(cpm_boot_dpmem_rh_block[0]),
cpm_boot_dpmem_rh_block);
im_dprambase = cpm2_immr;
/* Attach the usable dpmem area */
/* XXX: This is actually crap. CPM_DATAONLY_BASE and
* CPM_DATAONLY_SIZE is only a subset of the available dpram. It
* varies with the processor and the microcode patches activated.
* But the following should be at least safe.
*/
rh_attach_region(&cpm_dpmem_info, CPM_DATAONLY_BASE, CPM_DATAONLY_SIZE);
}
/* This function returns an index into the DPRAM area.
*/
unsigned long cpm_dpalloc(uint size, uint align)
{
unsigned long start;
unsigned long flags;
spin_lock_irqsave(&cpm_dpmem_lock, flags);
cpm_dpmem_info.alignment = align;
start = rh_alloc(&cpm_dpmem_info, size, "commproc");
spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
return (uint)start;
}
EXPORT_SYMBOL(cpm_dpalloc);
int cpm_dpfree(unsigned long offset)
{
int ret;
unsigned long flags;
spin_lock_irqsave(&cpm_dpmem_lock, flags);
ret = rh_free(&cpm_dpmem_info, offset);
spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
return ret;
}
EXPORT_SYMBOL(cpm_dpfree);
/* not sure if this is ever needed */
unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align)
{
unsigned long start;
unsigned long flags;
spin_lock_irqsave(&cpm_dpmem_lock, flags);
cpm_dpmem_info.alignment = align;
start = rh_alloc_fixed(&cpm_dpmem_info, offset, size, "commproc");
spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
return start;
}
EXPORT_SYMBOL(cpm_dpalloc_fixed);
void cpm_dpdump(void)
{
rh_dump(&cpm_dpmem_info);
}
EXPORT_SYMBOL(cpm_dpdump);
void *cpm_dpram_addr(unsigned long offset)
{
return (void *)(im_dprambase + offset);
}
EXPORT_SYMBOL(cpm_dpram_addr);
#endif /* !CONFIG_PPC_CPM_NEW_BINDING */
struct cpm2_ioports {
u32 dir, par, sor, odr, dat;
u32 res[3];

3
arch/powerpc/sysdev/cpm_common.c
View File

@ -58,7 +58,6 @@ void __init udbg_init_cpm(void)
}
#endif
#ifdef CONFIG_PPC_CPM_NEW_BINDING
static spinlock_t cpm_muram_lock;
static rh_block_t cpm_boot_muram_rh_block[16];
static rh_info_t cpm_muram_info;
@ -199,5 +198,3 @@ dma_addr_t cpm_muram_dma(void __iomem *addr)
return muram_pbase + ((u8 __iomem *)addr - muram_vbase);
}
EXPORT_SYMBOL(cpm_muram_dma);
#endif /* CONFIG_PPC_CPM_NEW_BINDING */

129
arch/powerpc/sysdev/fsl_lbc.c Normal file
View File

@ -0,0 +1,129 @@
/*
* Freescale LBC and UPM routines.
*
* Copyright (c) 2007-2008 MontaVista Software, Inc.
*
* Author: Anton Vorontsov <avorontsov@ru.mvista.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/kernel.h>
#include <linux/of.h>
#include <asm/fsl_lbc.h>
spinlock_t fsl_lbc_lock = __SPIN_LOCK_UNLOCKED(fsl_lbc_lock);
struct fsl_lbc_regs __iomem *fsl_lbc_regs;
EXPORT_SYMBOL(fsl_lbc_regs);
static char __initdata *compat_lbc[] = {
"fsl,pq2-localbus",
"fsl,pq2pro-localbus",
"fsl,pq3-localbus",
"fsl,elbc",
};
static int __init fsl_lbc_init(void)
{
struct device_node *lbus;
int i;
for (i = 0; i < ARRAY_SIZE(compat_lbc); i++) {
lbus = of_find_compatible_node(NULL, NULL, compat_lbc[i]);
if (lbus)
goto found;
}
return -ENODEV;
found:
fsl_lbc_regs = of_iomap(lbus, 0);
of_node_put(lbus);
if (!fsl_lbc_regs)
return -ENOMEM;
return 0;
}
arch_initcall(fsl_lbc_init);
/**
* fsl_lbc_find - find Localbus bank
* @addr_base: base address of the memory bank
*
* This function walks LBC banks comparing "Base address" field of the BR
* registers with the supplied addr_base argument. When bases match this
* function returns bank number (starting with 0), otherwise it returns
* appropriate errno value.
*/
int fsl_lbc_find(phys_addr_t addr_base)
{
int i;
if (!fsl_lbc_regs)
return -ENODEV;
for (i = 0; i < ARRAY_SIZE(fsl_lbc_regs->bank); i++) {
__be32 br = in_be32(&fsl_lbc_regs->bank[i].br);
__be32 or = in_be32(&fsl_lbc_regs->bank[i].or);
if (br & BR_V && (br & or & BR_BA) == addr_base)
return i;
}
return -ENOENT;
}
EXPORT_SYMBOL(fsl_lbc_find);
/**
* fsl_upm_find - find pre-programmed UPM via base address
* @addr_base: base address of the memory bank controlled by the UPM
* @upm: pointer to the allocated fsl_upm structure
*
* This function fills fsl_upm structure so you can use it with the rest of
* UPM API. On success this function returns 0, otherwise it returns
* appropriate errno value.
*/
int fsl_upm_find(phys_addr_t addr_base, struct fsl_upm *upm)
{
int bank;
__be32 br;
bank = fsl_lbc_find(addr_base);
if (bank < 0)
return bank;
br = in_be32(&fsl_lbc_regs->bank[bank].br);
switch (br & BR_MSEL) {
case BR_MS_UPMA:
upm->mxmr = &fsl_lbc_regs->mamr;
break;
case BR_MS_UPMB:
upm->mxmr = &fsl_lbc_regs->mbmr;
break;
case BR_MS_UPMC:
upm->mxmr = &fsl_lbc_regs->mcmr;
break;
default:
return -EINVAL;
}
switch (br & BR_PS) {
case BR_PS_8:
upm->width = 8;
break;
case BR_PS_16:
upm->width = 16;
break;
case BR_PS_32:
upm->width = 32;
break;
default:
return -EINVAL;
}
return 0;
}
EXPORT_SYMBOL(fsl_upm_find);

611
arch/powerpc/sysdev/fsl_soc.c
View File

@ -75,6 +75,33 @@ phys_addr_t get_immrbase(void)
EXPORT_SYMBOL(get_immrbase);
static u32 sysfreq = -1;
u32 fsl_get_sys_freq(void)
{
struct device_node *soc;
const u32 *prop;
int size;
if (sysfreq != -1)
return sysfreq;
soc = of_find_node_by_type(NULL, "soc");
if (!soc)
return -1;
prop = of_get_property(soc, "clock-frequency", &size);
if (!prop || size != sizeof(*prop) || *prop == 0)
prop = of_get_property(soc, "bus-frequency", &size);
if (prop && size == sizeof(*prop))
sysfreq = *prop;
of_node_put(soc);
return sysfreq;
}
EXPORT_SYMBOL(fsl_get_sys_freq);
#if defined(CONFIG_CPM2) || defined(CONFIG_QUICC_ENGINE) || defined(CONFIG_8xx)
static u32 brgfreq = -1;
@ -516,9 +543,9 @@ arch_initcall(fsl_i2c_of_init);
static int __init mpc83xx_wdt_init(void)
{
struct resource r;
struct device_node *soc, *np;
struct device_node *np;
struct platform_device *dev;
const unsigned int *freq;
u32 freq = fsl_get_sys_freq();
int ret;
np = of_find_compatible_node(NULL, "watchdog", "mpc83xx_wdt");
@ -528,19 +555,6 @@ static int __init mpc83xx_wdt_init(void)
goto nodev;
}
soc = of_find_node_by_type(NULL, "soc");
if (!soc) {
ret = -ENODEV;
goto nosoc;
}
freq = of_get_property(soc, "bus-frequency", NULL);
if (!freq) {
ret = -ENODEV;
goto err;
}
memset(&r, 0, sizeof(r));
ret = of_address_to_resource(np, 0, &r);
@ -553,20 +567,16 @@ static int __init mpc83xx_wdt_init(void)
goto err;
}
ret = platform_device_add_data(dev, freq, sizeof(int));
ret = platform_device_add_data(dev, &freq, sizeof(freq));
if (ret)
goto unreg;
of_node_put(soc);
of_node_put(np);
return 0;
unreg:
platform_device_unregister(dev);
err:
of_node_put(soc);
nosoc:
of_node_put(np);
nodev:
return ret;
@ -735,547 +745,6 @@ static int __init fsl_usb_of_init(void)
arch_initcall(fsl_usb_of_init);
#ifndef CONFIG_PPC_CPM_NEW_BINDING
#ifdef CONFIG_CPM2
extern void init_scc_ioports(struct fs_uart_platform_info*);
static const char fcc_regs[] = "fcc_regs";
static const char fcc_regs_c[] = "fcc_regs_c";
static const char fcc_pram[] = "fcc_pram";
static char bus_id[9][BUS_ID_SIZE];
static int __init fs_enet_of_init(void)
{
struct device_node *np;
unsigned int i;
struct platform_device *fs_enet_dev;
struct resource res;
int ret;
for (np = NULL, i = 0;
(np = of_find_compatible_node(np, "network", "fs_enet")) != NULL;
i++) {
struct resource r[4];
struct device_node *phy, *mdio;
struct fs_platform_info fs_enet_data;
const unsigned int *id, *phy_addr, *phy_irq;
const void *mac_addr;
const phandle *ph;
const char *model;
memset(r, 0, sizeof(r));
memset(&fs_enet_data, 0, sizeof(fs_enet_data));
ret = of_address_to_resource(np, 0, &r[0]);
if (ret)
goto err;
r[0].name = fcc_regs;
ret = of_address_to_resource(np, 1, &r[1]);
if (ret)
goto err;
r[1].name = fcc_pram;
ret = of_address_to_resource(np, 2, &r[2]);
if (ret)
goto err;
r[2].name = fcc_regs_c;
fs_enet_data.fcc_regs_c = r[2].start;
of_irq_to_resource(np, 0, &r[3]);
fs_enet_dev =
platform_device_register_simple("fsl-cpm-fcc", i, &r[0], 4);
if (IS_ERR(fs_enet_dev)) {
ret = PTR_ERR(fs_enet_dev);
goto err;
}
model = of_get_property(np, "model", NULL);
if (model == NULL) {
ret = -ENODEV;
goto unreg;
}
mac_addr = of_get_mac_address(np);
if (mac_addr)
memcpy(fs_enet_data.macaddr, mac_addr, 6);
ph = of_get_property(np, "phy-handle", NULL);
phy = of_find_node_by_phandle(*ph);
if (phy == NULL) {
ret = -ENODEV;
goto unreg;
}
phy_addr = of_get_property(phy, "reg", NULL);
fs_enet_data.phy_addr = *phy_addr;
phy_irq = of_get_property(phy, "interrupts", NULL);
id = of_get_property(np, "device-id", NULL);
fs_enet_data.fs_no = *id;
strcpy(fs_enet_data.fs_type, model);
mdio = of_get_parent(phy);
ret = of_address_to_resource(mdio, 0, &res);
if (ret) {
of_node_put(phy);
of_node_put(mdio);
goto unreg;
}
fs_enet_data.clk_rx = *((u32 *)of_get_property(np,
"rx-clock", NULL));
fs_enet_data.clk_tx = *((u32 *)of_get_property(np,
"tx-clock", NULL));
if (strstr(model, "FCC")) {
int fcc_index = *id - 1;
const unsigned char *mdio_bb_prop;
fs_enet_data.dpram_offset = (u32)cpm_dpram_addr(0);
fs_enet_data.rx_ring = 32;
fs_enet_data.tx_ring = 32;
fs_enet_data.rx_copybreak = 240;
fs_enet_data.use_napi = 0;
fs_enet_data.napi_weight = 17;
fs_enet_data.mem_offset = FCC_MEM_OFFSET(fcc_index);
fs_enet_data.cp_page = CPM_CR_FCC_PAGE(fcc_index);
fs_enet_data.cp_block = CPM_CR_FCC_SBLOCK(fcc_index);
snprintf((char*)&bus_id[(*id)], BUS_ID_SIZE, "%x:%02x",
(u32)res.start, fs_enet_data.phy_addr);
fs_enet_data.bus_id = (char*)&bus_id[(*id)];
fs_enet_data.init_ioports = init_fcc_ioports;
mdio_bb_prop = of_get_property(phy, "bitbang", NULL);
if (mdio_bb_prop) {
struct platform_device *fs_enet_mdio_bb_dev;
struct fs_mii_bb_platform_info fs_enet_mdio_bb_data;
fs_enet_mdio_bb_dev =
platform_device_register_simple("fsl-bb-mdio",
i, NULL, 0);
memset(&fs_enet_mdio_bb_data, 0,
sizeof(struct fs_mii_bb_platform_info));
fs_enet_mdio_bb_data.mdio_dat.bit =
mdio_bb_prop[0];
fs_enet_mdio_bb_data.mdio_dir.bit =
mdio_bb_prop[1];
fs_enet_mdio_bb_data.mdc_dat.bit =
mdio_bb_prop[2];
fs_enet_mdio_bb_data.mdio_port =
mdio_bb_prop[3];
fs_enet_mdio_bb_data.mdc_port =
mdio_bb_prop[4];
fs_enet_mdio_bb_data.delay =
mdio_bb_prop[5];
fs_enet_mdio_bb_data.irq[0] = phy_irq[0];
fs_enet_mdio_bb_data.irq[1] = -1;
fs_enet_mdio_bb_data.irq[2] = -1;
fs_enet_mdio_bb_data.irq[3] = phy_irq[0];
fs_enet_mdio_bb_data.irq[31] = -1;
fs_enet_mdio_bb_data.mdio_dat.offset =
(u32)&cpm2_immr->im_ioport.iop_pdatc;
fs_enet_mdio_bb_data.mdio_dir.offset =
(u32)&cpm2_immr->im_ioport.iop_pdirc;
fs_enet_mdio_bb_data.mdc_dat.offset =
(u32)&cpm2_immr->im_ioport.iop_pdatc;
ret = platform_device_add_data(
fs_enet_mdio_bb_dev,
&fs_enet_mdio_bb_data,
sizeof(struct fs_mii_bb_platform_info));
if (ret)
goto unreg;
}
of_node_put(phy);
of_node_put(mdio);
ret = platform_device_add_data(fs_enet_dev, &fs_enet_data,
sizeof(struct
fs_platform_info));
if (ret)
goto unreg;
}
}
return 0;
unreg:
platform_device_unregister(fs_enet_dev);
err:
return ret;
}
arch_initcall(fs_enet_of_init);
static const char scc_regs[] = "regs";
static const char scc_pram[] = "pram";
static int __init cpm_uart_of_init(void)
{
struct device_node *np;
unsigned int i;
struct platform_device *cpm_uart_dev;
int ret;
for (np = NULL, i = 0;
(np = of_find_compatible_node(np, "serial", "cpm_uart")) != NULL;
i++) {
struct resource r[3];
struct fs_uart_platform_info cpm_uart_data;
const int *id;
const char *model;
memset(r, 0, sizeof(r));
memset(&cpm_uart_data, 0, sizeof(cpm_uart_data));
ret = of_address_to_resource(np, 0, &r[0]);
if (ret)
goto err;
r[0].name = scc_regs;
ret = of_address_to_resource(np, 1, &r[1]);
if (ret)
goto err;
r[1].name = scc_pram;
of_irq_to_resource(np, 0, &r[2]);
cpm_uart_dev =
platform_device_register_simple("fsl-cpm-scc:uart", i, &r[0], 3);
if (IS_ERR(cpm_uart_dev)) {
ret = PTR_ERR(cpm_uart_dev);
goto err;
}
id = of_get_property(np, "device-id", NULL);
cpm_uart_data.fs_no = *id;
model = of_get_property(np, "model", NULL);
strcpy(cpm_uart_data.fs_type, model);
cpm_uart_data.uart_clk = ppc_proc_freq;
cpm_uart_data.tx_num_fifo = 4;
cpm_uart_data.tx_buf_size = 32;
cpm_uart_data.rx_num_fifo = 4;
cpm_uart_data.rx_buf_size = 32;
cpm_uart_data.clk_rx = *((u32 *)of_get_property(np,
"rx-clock", NULL));
cpm_uart_data.clk_tx = *((u32 *)of_get_property(np,
"tx-clock", NULL));
ret =
platform_device_add_data(cpm_uart_dev, &cpm_uart_data,
sizeof(struct
fs_uart_platform_info));
if (ret)
goto unreg;
}
return 0;
unreg:
platform_device_unregister(cpm_uart_dev);
err:
return ret;
}
arch_initcall(cpm_uart_of_init);
#endif /* CONFIG_CPM2 */
#ifdef CONFIG_8xx
extern void init_scc_ioports(struct fs_platform_info*);
extern int platform_device_skip(const char *model, int id);
static int __init fs_enet_mdio_of_init(void)
{
struct device_node *np;
unsigned int i;
struct platform_device *mdio_dev;
struct resource res;
int ret;
for (np = NULL, i = 0;
(np = of_find_compatible_node(np, "mdio", "fs_enet")) != NULL;
i++) {
struct fs_mii_fec_platform_info mdio_data;
memset(&res, 0, sizeof(res));
memset(&mdio_data, 0, sizeof(mdio_data));
ret = of_address_to_resource(np, 0, &res);
if (ret)
goto err;
mdio_dev =
platform_device_register_simple("fsl-cpm-fec-mdio",
res.start, &res, 1);
if (IS_ERR(mdio_dev)) {
ret = PTR_ERR(mdio_dev);
goto err;
}
mdio_data.mii_speed = ((((ppc_proc_freq + 4999999) / 2500000) / 2) & 0x3F) << 1;
ret =
platform_device_add_data(mdio_dev, &mdio_data,
sizeof(struct fs_mii_fec_platform_info));
if (ret)
goto unreg;
}
return 0;
unreg:
platform_device_unregister(mdio_dev);
err:
return ret;
}
arch_initcall(fs_enet_mdio_of_init);
static const char *enet_regs = "regs";
static const char *enet_pram = "pram";
static const char *enet_irq = "interrupt";
static char bus_id[9][BUS_ID_SIZE];
static int __init fs_enet_of_init(void)
{
struct device_node *np;
unsigned int i;
struct platform_device *fs_enet_dev = NULL;
struct resource res;
int ret;
for (np = NULL, i = 0;
(np = of_find_compatible_node(np, "network", "fs_enet")) != NULL;
i++) {
struct resource r[4];
struct device_node *phy = NULL, *mdio = NULL;
struct fs_platform_info fs_enet_data;
const unsigned int *id;
const unsigned int *phy_addr;
const void *mac_addr;
const phandle *ph;
const char *model;
memset(r, 0, sizeof(r));
memset(&fs_enet_data, 0, sizeof(fs_enet_data));
model = of_get_property(np, "model", NULL);
if (model == NULL) {
ret = -ENODEV;
goto unreg;
}
id = of_get_property(np, "device-id", NULL);
fs_enet_data.fs_no = *id;
if (platform_device_skip(model, *id))
continue;
ret = of_address_to_resource(np, 0, &r[0]);
if (ret)
goto err;
r[0].name = enet_regs;
mac_addr = of_get_mac_address(np);
if (mac_addr)
memcpy(fs_enet_data.macaddr, mac_addr, 6);
ph = of_get_property(np, "phy-handle", NULL);
if (ph != NULL)
phy = of_find_node_by_phandle(*ph);
if (phy != NULL) {
phy_addr = of_get_property(phy, "reg", NULL);
fs_enet_data.phy_addr = *phy_addr;
fs_enet_data.has_phy = 1;
mdio = of_get_parent(phy);
ret = of_address_to_resource(mdio, 0, &res);
if (ret) {
of_node_put(phy);
of_node_put(mdio);
goto unreg;
}
}
model = of_get_property(np, "model", NULL);
strcpy(fs_enet_data.fs_type, model);
if (strstr(model, "FEC")) {
r[1].start = r[1].end = irq_of_parse_and_map(np, 0);
r[1].flags = IORESOURCE_IRQ;
r[1].name = enet_irq;
fs_enet_dev =
platform_device_register_simple("fsl-cpm-fec", i, &r[0], 2);
if (IS_ERR(fs_enet_dev)) {
ret = PTR_ERR(fs_enet_dev);
goto err;
}
fs_enet_data.rx_ring = 128;
fs_enet_data.tx_ring = 16;
fs_enet_data.rx_copybreak = 240;
fs_enet_data.use_napi = 1;
fs_enet_data.napi_weight = 17;
snprintf((char*)&bus_id[i], BUS_ID_SIZE, "%x:%02x",
(u32)res.start, fs_enet_data.phy_addr);
fs_enet_data.bus_id = (char*)&bus_id[i];
fs_enet_data.init_ioports = init_fec_ioports;
}
if (strstr(model, "SCC")) {
ret = of_address_to_resource(np, 1, &r[1]);
if (ret)
goto err;
r[1].name = enet_pram;
r[2].start = r[2].end = irq_of_parse_and_map(np, 0);
r[2].flags = IORESOURCE_IRQ;
r[2].name = enet_irq;
fs_enet_dev =
platform_device_register_simple("fsl-cpm-scc", i, &r[0], 3);
if (IS_ERR(fs_enet_dev)) {
ret = PTR_ERR(fs_enet_dev);
goto err;
}
fs_enet_data.rx_ring = 64;
fs_enet_data.tx_ring = 8;
fs_enet_data.rx_copybreak = 240;
fs_enet_data.use_napi = 1;
fs_enet_data.napi_weight = 17;
snprintf((char*)&bus_id[i], BUS_ID_SIZE, "%s", "fixed@10:1");
fs_enet_data.bus_id = (char*)&bus_id[i];
fs_enet_data.init_ioports = init_scc_ioports;
}
of_node_put(phy);
of_node_put(mdio);
ret = platform_device_add_data(fs_enet_dev, &fs_enet_data,
sizeof(struct
fs_platform_info));
if (ret)
goto unreg;
}
return 0;
unreg:
platform_device_unregister(fs_enet_dev);
err:
return ret;
}
arch_initcall(fs_enet_of_init);
static int __init fsl_pcmcia_of_init(void)
{
struct device_node *np;
/*
* Register all the devices which type is "pcmcia"
*/
for_each_compatible_node(np, "pcmcia", "fsl,pq-pcmcia")
of_platform_device_create(np, "m8xx-pcmcia", NULL);
return 0;
}
arch_initcall(fsl_pcmcia_of_init);
static const char *smc_regs = "regs";
static const char *smc_pram = "pram";
static int __init cpm_smc_uart_of_init(void)
{
struct device_node *np;
unsigned int i;
struct platform_device *cpm_uart_dev;
int ret;
for (np = NULL, i = 0;
(np = of_find_compatible_node(np, "serial", "cpm_uart")) != NULL;
i++) {
struct resource r[3];
struct fs_uart_platform_info cpm_uart_data;
const int *id;
const char *model;
memset(r, 0, sizeof(r));
memset(&cpm_uart_data, 0, sizeof(cpm_uart_data));
ret = of_address_to_resource(np, 0, &r[0]);
if (ret)
goto err;
r[0].name = smc_regs;
ret = of_address_to_resource(np, 1, &r[1]);
if (ret)
goto err;
r[1].name = smc_pram;
r[2].start = r[2].end = irq_of_parse_and_map(np, 0);
r[2].flags = IORESOURCE_IRQ;
cpm_uart_dev =
platform_device_register_simple("fsl-cpm-smc:uart", i, &r[0], 3);
if (IS_ERR(cpm_uart_dev)) {
ret = PTR_ERR(cpm_uart_dev);
goto err;
}
model = of_get_property(np, "model", NULL);
strcpy(cpm_uart_data.fs_type, model);
id = of_get_property(np, "device-id", NULL);
cpm_uart_data.fs_no = *id;
cpm_uart_data.uart_clk = ppc_proc_freq;
cpm_uart_data.tx_num_fifo = 4;
cpm_uart_data.tx_buf_size = 32;
cpm_uart_data.rx_num_fifo = 4;
cpm_uart_data.rx_buf_size = 32;
ret =
platform_device_add_data(cpm_uart_dev, &cpm_uart_data,
sizeof(struct
fs_uart_platform_info));
if (ret)
goto unreg;
}
return 0;
unreg:
platform_device_unregister(cpm_uart_dev);
err:
return ret;
}
arch_initcall(cpm_smc_uart_of_init);
#endif /* CONFIG_8xx */
#endif /* CONFIG_PPC_CPM_NEW_BINDING */
static int __init of_fsl_spi_probe(char *type, char *compatible, u32 sysclk,
struct spi_board_info *board_infos,
unsigned int num_board_infos,
@ -1371,25 +840,9 @@ int __init fsl_spi_init(struct spi_board_info *board_infos,
sysclk = get_brgfreq();
#endif
if (sysclk == -1) {
struct device_node *np;
const u32 *freq;
int size;
np = of_find_node_by_type(NULL, "soc");
if (!np)
sysclk = fsl_get_sys_freq();
if (sysclk == -1)
return -ENODEV;
freq = of_get_property(np, "clock-frequency", &size);
if (!freq || size != sizeof(*freq) || *freq == 0) {
freq = of_get_property(np, "bus-frequency", &size);
if (!freq || size != sizeof(*freq) || *freq == 0) {
of_node_put(np);
return -ENODEV;
}
}
sysclk = *freq;
of_node_put(np);
}
ret = of_fsl_spi_probe(NULL, "fsl,spi", sysclk, board_infos,

1
arch/powerpc/sysdev/fsl_soc.h
View File

@ -7,6 +7,7 @@
extern phys_addr_t get_immrbase(void);
extern u32 get_brgfreq(void);
extern u32 get_baudrate(void);
extern u32 fsl_get_sys_freq(void);
struct spi_board_info;

13
arch/powerpc/sysdev/qe_lib/qe.c
View File

@ -55,7 +55,7 @@ struct qe_snum {
/* We allocate this here because it is used almost exclusively for
* the communication processor devices.
*/
struct qe_immap *qe_immr = NULL;
struct qe_immap __iomem *qe_immr;
EXPORT_SYMBOL(qe_immr);
static struct qe_snum snums[QE_NUM_OF_SNUM]; /* Dynamically allocated SNUMs */
@ -156,7 +156,7 @@ EXPORT_SYMBOL(qe_issue_cmd);
*/
static unsigned int brg_clk = 0;
unsigned int get_brg_clk(void)
unsigned int qe_get_brg_clk(void)
{
struct device_node *qe;
unsigned int size;
@ -180,6 +180,7 @@ unsigned int get_brg_clk(void)
return brg_clk;
}
EXPORT_SYMBOL(qe_get_brg_clk);
/* Program the BRG to the given sampling rate and multiplier
*
@ -197,7 +198,7 @@ int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier)
if ((brg < QE_BRG1) || (brg > QE_BRG16))
return -EINVAL;
divisor = get_brg_clk() / (rate * multiplier);
divisor = qe_get_brg_clk() / (rate * multiplier);
if (divisor > QE_BRGC_DIVISOR_MAX + 1) {
div16 = QE_BRGC_DIV16;
@ -415,12 +416,6 @@ void qe_muram_dump(void)
}
EXPORT_SYMBOL(qe_muram_dump);
void *qe_muram_addr(unsigned long offset)
{
return (void *)&qe_immr->muram[offset];
}
EXPORT_SYMBOL(qe_muram_addr);
/* The maximum number of RISCs we support */
#define MAX_QE_RISC 2

5
arch/powerpc/sysdev/qe_lib/qe_io.c
View File

@ -22,6 +22,7 @@
#include <linux/ioport.h>
#include <asm/io.h>
#include <asm/qe.h>
#include <asm/prom.h>
#include <sysdev/fsl_soc.h>
@ -41,7 +42,7 @@ struct port_regs {
#endif
};
static struct port_regs *par_io = NULL;
static struct port_regs __iomem *par_io;
static int num_par_io_ports = 0;
int par_io_init(struct device_node *np)
@ -165,7 +166,7 @@ int par_io_of_config(struct device_node *np)
}
ph = of_get_property(np, "pio-handle", NULL);
if (ph == 0) {
if (ph == NULL) {
printk(KERN_ERR "pio-handle not available \n");
return -1;
}

219
drivers/mtd/nand/fsl_elbc_nand.c
View File

@ -36,207 +36,12 @@
#include <linux/mtd/partitions.h>
#include <asm/io.h>
#include <asm/fsl_lbc.h>
#define MAX_BANKS 8
#define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */
#define FCM_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait for FCM */
struct elbc_bank {
__be32 br; /**< Base Register */
#define BR_BA 0xFFFF8000
#define BR_BA_SHIFT 15
#define BR_PS 0x00001800
#define BR_PS_SHIFT 11
#define BR_PS_8 0x00000800 /* Port Size 8 bit */
#define BR_PS_16 0x00001000 /* Port Size 16 bit */
#define BR_PS_32 0x00001800 /* Port Size 32 bit */
#define BR_DECC 0x00000600
#define BR_DECC_SHIFT 9
#define BR_DECC_OFF 0x00000000 /* HW ECC checking and generation off */
#define BR_DECC_CHK 0x00000200 /* HW ECC checking on, generation off */
#define BR_DECC_CHK_GEN 0x00000400 /* HW ECC checking and generation on */
#define BR_WP 0x00000100
#define BR_WP_SHIFT 8
#define BR_MSEL 0x000000E0
#define BR_MSEL_SHIFT 5
#define BR_MS_GPCM 0x00000000 /* GPCM */
#define BR_MS_FCM 0x00000020 /* FCM */
#define BR_MS_SDRAM 0x00000060 /* SDRAM */
#define BR_MS_UPMA 0x00000080 /* UPMA */
#define BR_MS_UPMB 0x000000A0 /* UPMB */
#define BR_MS_UPMC 0x000000C0 /* UPMC */
#define BR_V 0x00000001
#define BR_V_SHIFT 0
#define BR_RES ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V)
__be32 or; /**< Base Register */
#define OR0 0x5004
#define OR1 0x500C
#define OR2 0x5014
#define OR3 0x501C
#define OR4 0x5024
#define OR5 0x502C
#define OR6 0x5034
#define OR7 0x503C
#define OR_FCM_AM 0xFFFF8000
#define OR_FCM_AM_SHIFT 15
#define OR_FCM_BCTLD 0x00001000
#define OR_FCM_BCTLD_SHIFT 12
#define OR_FCM_PGS 0x00000400
#define OR_FCM_PGS_SHIFT 10
#define OR_FCM_CSCT 0x00000200
#define OR_FCM_CSCT_SHIFT 9
#define OR_FCM_CST 0x00000100
#define OR_FCM_CST_SHIFT 8
#define OR_FCM_CHT 0x00000080
#define OR_FCM_CHT_SHIFT 7
#define OR_FCM_SCY 0x00000070
#define OR_FCM_SCY_SHIFT 4
#define OR_FCM_SCY_1 0x00000010
#define OR_FCM_SCY_2 0x00000020
#define OR_FCM_SCY_3 0x00000030
#define OR_FCM_SCY_4 0x00000040
#define OR_FCM_SCY_5 0x00000050
#define OR_FCM_SCY_6 0x00000060
#define OR_FCM_SCY_7 0x00000070
#define OR_FCM_RST 0x00000008
#define OR_FCM_RST_SHIFT 3
#define OR_FCM_TRLX 0x00000004
#define OR_FCM_TRLX_SHIFT 2
#define OR_FCM_EHTR 0x00000002
#define OR_FCM_EHTR_SHIFT 1
};
struct elbc_regs {
struct elbc_bank bank[8];
u8 res0[0x28];
__be32 mar; /**< UPM Address Register */
u8 res1[0x4];
__be32 mamr; /**< UPMA Mode Register */
__be32 mbmr; /**< UPMB Mode Register */
__be32 mcmr; /**< UPMC Mode Register */
u8 res2[0x8];
__be32 mrtpr; /**< Memory Refresh Timer Prescaler Register */
__be32 mdr; /**< UPM Data Register */
u8 res3[0x4];
__be32 lsor; /**< Special Operation Initiation Register */
__be32 lsdmr; /**< SDRAM Mode Register */
u8 res4[0x8];
__be32 lurt; /**< UPM Refresh Timer */
__be32 lsrt; /**< SDRAM Refresh Timer */
u8 res5[0x8];
__be32 ltesr; /**< Transfer Error Status Register */
#define LTESR_BM 0x80000000
#define LTESR_FCT 0x40000000
#define LTESR_PAR 0x20000000
#define LTESR_WP 0x04000000
#define LTESR_ATMW 0x00800000
#define LTESR_ATMR 0x00400000
#define LTESR_CS 0x00080000
#define LTESR_CC 0x00000001
#define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC)
__be32 ltedr; /**< Transfer Error Disable Register */
__be32 lteir; /**< Transfer Error Interrupt Register */
__be32 lteatr; /**< Transfer Error Attributes Register */
__be32 ltear; /**< Transfer Error Address Register */
u8 res6[0xC];
__be32 lbcr; /**< Configuration Register */
#define LBCR_LDIS 0x80000000
#define LBCR_LDIS_SHIFT 31
#define LBCR_BCTLC 0x00C00000
#define LBCR_BCTLC_SHIFT 22
#define LBCR_AHD 0x00200000
#define LBCR_LPBSE 0x00020000
#define LBCR_LPBSE_SHIFT 17
#define LBCR_EPAR 0x00010000
#define LBCR_EPAR_SHIFT 16
#define LBCR_BMT 0x0000FF00
#define LBCR_BMT_SHIFT 8
#define LBCR_INIT 0x00040000
__be32 lcrr; /**< Clock Ratio Register */
#define LCRR_DBYP 0x80000000
#define LCRR_DBYP_SHIFT 31
#define LCRR_BUFCMDC 0x30000000
#define LCRR_BUFCMDC_SHIFT 28
#define LCRR_ECL 0x03000000
#define LCRR_ECL_SHIFT 24
#define LCRR_EADC 0x00030000
#define LCRR_EADC_SHIFT 16
#define LCRR_CLKDIV 0x0000000F
#define LCRR_CLKDIV_SHIFT 0
u8 res7[0x8];
__be32 fmr; /**< Flash Mode Register */
#define FMR_CWTO 0x0000F000
#define FMR_CWTO_SHIFT 12
#define FMR_BOOT 0x00000800
#define FMR_ECCM 0x00000100
#define FMR_AL 0x00000030
#define FMR_AL_SHIFT 4
#define FMR_OP 0x00000003
#define FMR_OP_SHIFT 0
__be32 fir; /**< Flash Instruction Register */
#define FIR_OP0 0xF0000000
#define FIR_OP0_SHIFT 28
#define FIR_OP1 0x0F000000
#define FIR_OP1_SHIFT 24
#define FIR_OP2 0x00F00000
#define FIR_OP2_SHIFT 20
#define FIR_OP3 0x000F0000
#define FIR_OP3_SHIFT 16
#define FIR_OP4 0x0000F000
#define FIR_OP4_SHIFT 12
#define FIR_OP5 0x00000F00
#define FIR_OP5_SHIFT 8
#define FIR_OP6 0x000000F0
#define FIR_OP6_SHIFT 4
#define FIR_OP7 0x0000000F
#define FIR_OP7_SHIFT 0
#define FIR_OP_NOP 0x0 /* No operation and end of sequence */
#define FIR_OP_CA 0x1 /* Issue current column address */
#define FIR_OP_PA 0x2 /* Issue current block+page address */
#define FIR_OP_UA 0x3 /* Issue user defined address */
#define FIR_OP_CM0 0x4 /* Issue command from FCR[CMD0] */
#define FIR_OP_CM1 0x5 /* Issue command from FCR[CMD1] */
#define FIR_OP_CM2 0x6 /* Issue command from FCR[CMD2] */
#define FIR_OP_CM3 0x7 /* Issue command from FCR[CMD3] */
#define FIR_OP_WB 0x8 /* Write FBCR bytes from FCM buffer */
#define FIR_OP_WS 0x9 /* Write 1 or 2 bytes from MDR[AS] */
#define FIR_OP_RB 0xA /* Read FBCR bytes to FCM buffer */
#define FIR_OP_RS 0xB /* Read 1 or 2 bytes to MDR[AS] */
#define FIR_OP_CW0 0xC /* Wait then issue FCR[CMD0] */
#define FIR_OP_CW1 0xD /* Wait then issue FCR[CMD1] */
#define FIR_OP_RBW 0xE /* Wait then read FBCR bytes */
#define FIR_OP_RSW 0xE /* Wait then read 1 or 2 bytes */
__be32 fcr; /**< Flash Command Register */
#define FCR_CMD0 0xFF000000
#define FCR_CMD0_SHIFT 24
#define FCR_CMD1 0x00FF0000
#define FCR_CMD1_SHIFT 16
#define FCR_CMD2 0x0000FF00
#define FCR_CMD2_SHIFT 8
#define FCR_CMD3 0x000000FF
#define FCR_CMD3_SHIFT 0
__be32 fbar; /**< Flash Block Address Register */
#define FBAR_BLK 0x00FFFFFF
__be32 fpar; /**< Flash Page Address Register */
#define FPAR_SP_PI 0x00007C00
#define FPAR_SP_PI_SHIFT 10
#define FPAR_SP_MS 0x00000200
#define FPAR_SP_CI 0x000001FF
#define FPAR_SP_CI_SHIFT 0
#define FPAR_LP_PI 0x0003F000
#define FPAR_LP_PI_SHIFT 12
#define FPAR_LP_MS 0x00000800
#define FPAR_LP_CI 0x000007FF
#define FPAR_LP_CI_SHIFT 0
__be32 fbcr; /**< Flash Byte Count Register */
#define FBCR_BC 0x00000FFF
u8 res11[0x8];
u8 res8[0xF00];
};
struct fsl_elbc_ctrl;
/* mtd information per set */
@ -261,7 +66,7 @@ struct fsl_elbc_ctrl {
/* device info */
struct device *dev;
struct elbc_regs __iomem *regs;
struct fsl_lbc_regs __iomem *regs;
int irq;
wait_queue_head_t irq_wait;
unsigned int irq_status; /* status read from LTESR by irq handler */
@ -322,7 +127,7 @@ static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
struct nand_chip *chip = mtd->priv;
struct fsl_elbc_mtd *priv = chip->priv;
struct fsl_elbc_ctrl *ctrl = priv->ctrl;
struct elbc_regs __iomem *lbc = ctrl->regs;
struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
int buf_num;
ctrl->page = page_addr;
@ -363,7 +168,7 @@ static int fsl_elbc_run_command(struct mtd_info *mtd)
struct nand_chip *chip = mtd->priv;
struct fsl_elbc_mtd *priv = chip->priv;
struct fsl_elbc_ctrl *ctrl = priv->ctrl;
struct elbc_regs __iomem *lbc = ctrl->regs;
struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
/* Setup the FMR[OP] to execute without write protection */
out_be32(&lbc->fmr, priv->fmr | 3);
@ -406,7 +211,7 @@ static void fsl_elbc_do_read(struct nand_chip *chip, int oob)
{
struct fsl_elbc_mtd *priv = chip->priv;
struct fsl_elbc_ctrl *ctrl = priv->ctrl;
struct elbc_regs __iomem *lbc = ctrl->regs;
struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
if (priv->page_size) {
out_be32(&lbc->fir,
@ -439,7 +244,7 @@ static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
struct nand_chip *chip = mtd->priv;
struct fsl_elbc_mtd *priv = chip->priv;
struct fsl_elbc_ctrl *ctrl = priv->ctrl;
struct elbc_regs __iomem *lbc = ctrl->regs;
struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
ctrl->use_mdr = 0;
@ -775,7 +580,7 @@ static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip)
{
struct fsl_elbc_mtd *priv = chip->priv;
struct fsl_elbc_ctrl *ctrl = priv->ctrl;
struct elbc_regs __iomem *lbc = ctrl->regs;
struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
if (ctrl->status != LTESR_CC)
return NAND_STATUS_FAIL;
@ -807,7 +612,7 @@ static int fsl_elbc_chip_init_tail(struct mtd_info *mtd)
struct nand_chip *chip = mtd->priv;
struct fsl_elbc_mtd *priv = chip->priv;
struct fsl_elbc_ctrl *ctrl = priv->ctrl;
struct elbc_regs __iomem *lbc = ctrl->regs;
struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
unsigned int al;
/* calculate FMR Address Length field */
@ -922,7 +727,7 @@ static void fsl_elbc_write_page(struct mtd_info *mtd,
static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv)
{
struct fsl_elbc_ctrl *ctrl = priv->ctrl;
struct elbc_regs __iomem *lbc = ctrl->regs;
struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
struct nand_chip *chip = &priv->chip;
dev_dbg(priv->dev, "eLBC Set Information for bank %d\n", priv->bank);
@ -986,7 +791,7 @@ static int fsl_elbc_chip_remove(struct fsl_elbc_mtd *priv)
static int fsl_elbc_chip_probe(struct fsl_elbc_ctrl *ctrl,
struct device_node *node)
{
struct elbc_regs __iomem *lbc = ctrl->regs;
struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
struct fsl_elbc_mtd *priv;
struct resource res;
#ifdef CONFIG_MTD_PARTITIONS
@ -1083,7 +888,7 @@ static int fsl_elbc_chip_probe(struct fsl_elbc_ctrl *ctrl,
static int __devinit fsl_elbc_ctrl_init(struct fsl_elbc_ctrl *ctrl)
{
struct elbc_regs __iomem *lbc = ctrl->regs;
struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
/* clear event registers */
setbits32(&lbc->ltesr, LTESR_NAND_MASK);
@ -1128,7 +933,7 @@ static int __devexit fsl_elbc_ctrl_remove(struct of_device *ofdev)
static irqreturn_t fsl_elbc_ctrl_irq(int irqno, void *data)
{
struct fsl_elbc_ctrl *ctrl = data;
struct elbc_regs __iomem *lbc = ctrl->regs;
struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
__be32 status = in_be32(&lbc->ltesr) & LTESR_NAND_MASK;
if (status) {

8
drivers/net/ucc_geth.c
View File

@ -3852,7 +3852,13 @@ static int ucc_geth_probe(struct of_device* ofdev, const struct of_device_id *ma
ugeth_vdbg("%s: IN", __FUNCTION__);
prop = of_get_property(np, "device-id", NULL);
prop = of_get_property(np, "cell-index", NULL);
if (!prop) {
prop = of_get_property(np, "device-id", NULL);
if (!prop)
return -ENODEV;
}
ucc_num = *prop - 1;
if ((ucc_num < 0) || (ucc_num > 7))
return -ENODEV;

11
drivers/net/ucc_geth_mii.c
View File

@ -203,9 +203,14 @@ static int uec_mdio_probe(struct of_device *ofdev, const struct of_device_id *ma
if ((res.start >= tempres.start) &&
(res.end <= tempres.end)) {
/* set this UCC to be the MII master */
const u32 *id = of_get_property(tempnp, "device-id", NULL);
if (id == NULL)
goto bus_register_fail;
const u32 *id;
id = of_get_property(tempnp, "cell-index", NULL);
if (!id) {
id = of_get_property(tempnp, "device-id", NULL);
if (!id)
goto bus_register_fail;
}
ucc_set_qe_mux_mii_mng(*id - 1);

3
drivers/serial/cpm_uart/cpm_uart.h
View File

@ -92,6 +92,9 @@ extern struct uart_cpm_port cpm_uart_ports[UART_NR];
/* these are located in their respective files */
void cpm_line_cr_cmd(struct uart_cpm_port *port, int cmd);
void __iomem *cpm_uart_map_pram(struct uart_cpm_port *port,
struct device_node *np);
void cpm_uart_unmap_pram(struct uart_cpm_port *port, void __iomem *pram);
int cpm_uart_init_portdesc(void);
int cpm_uart_allocbuf(struct uart_cpm_port *pinfo, unsigned int is_con);
void cpm_uart_freebuf(struct uart_cpm_port *pinfo);

19
drivers/serial/cpm_uart/cpm_uart_core.c
View File

@ -966,24 +966,23 @@ static int cpm_uart_init_port(struct device_node *np,
if (!mem)
return -ENOMEM;
pram = of_iomap(np, 1);
if (!pram) {
ret = -ENOMEM;
goto out_mem;
}
if (of_device_is_compatible(np, "fsl,cpm1-scc-uart") ||
of_device_is_compatible(np, "fsl,cpm2-scc-uart")) {
pinfo->sccp = mem;
pinfo->sccup = pram;
pinfo->sccup = pram = cpm_uart_map_pram(pinfo, np);
} else if (of_device_is_compatible(np, "fsl,cpm1-smc-uart") ||
of_device_is_compatible(np, "fsl,cpm2-smc-uart")) {
pinfo->flags |= FLAG_SMC;
pinfo->smcp = mem;
pinfo->smcup = pram;
pinfo->smcup = pram = cpm_uart_map_pram(pinfo, np);
} else {
ret = -ENODEV;
goto out_pram;
goto out_mem;
}
if (!pram) {
ret = -ENOMEM;
goto out_mem;
}
pinfo->tx_nrfifos = TX_NUM_FIFO;
@ -1007,7 +1006,7 @@ static int cpm_uart_init_port(struct device_node *np,
return cpm_uart_request_port(&pinfo->port);
out_pram:
iounmap(pram);
cpm_uart_unmap_pram(pinfo, pram);
out_mem:
iounmap(mem);
return ret;

14
drivers/serial/cpm_uart/cpm_uart_cpm1.c
View File

@ -45,6 +45,8 @@
#include <linux/serial_core.h>
#include <linux/kernel.h>
#include <linux/of.h>
#include "cpm_uart.h"
/**************************************************************/
@ -54,6 +56,18 @@ void cpm_line_cr_cmd(struct uart_cpm_port *port, int cmd)
{
cpm_command(port->command, cmd);
}
void __iomem *cpm_uart_map_pram(struct uart_cpm_port *port,
struct device_node *np)
{
return of_iomap(np, 1);
}
void cpm_uart_unmap_pram(struct uart_cpm_port *port, void __iomem *pram)
{
iounmap(pram);
}
#else
void cpm_line_cr_cmd(struct uart_cpm_port *port, int cmd)
{

52
drivers/serial/cpm_uart/cpm_uart_cpm2.c
View File

@ -41,6 +41,9 @@
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/fs_pd.h>
#ifdef CONFIG_PPC_CPM_NEW_BINDING
#include <asm/prom.h>
#endif
#include <linux/serial_core.h>
#include <linux/kernel.h>
@ -54,6 +57,55 @@ void cpm_line_cr_cmd(struct uart_cpm_port *port, int cmd)
{
cpm_command(port->command, cmd);
}
void __iomem *cpm_uart_map_pram(struct uart_cpm_port *port,
struct device_node *np)
{
void __iomem *pram;
unsigned long offset;
struct resource res;
unsigned long len;
/* Don't remap parameter RAM if it has already been initialized
* during console setup.
*/
if (IS_SMC(port) && port->smcup)
return port->smcup;
else if (!IS_SMC(port) && port->sccup)
return port->sccup;
if (of_address_to_resource(np, 1, &res))
return NULL;
len = 1 + res.end - res.start;
pram = ioremap(res.start, len);
if (!pram)
return NULL;
if (!IS_SMC(port))
return pram;
if (len != 2) {
printk(KERN_WARNING "cpm_uart[%d]: device tree references "
"SMC pram, using boot loader/wrapper pram mapping. "
"Please fix your device tree to reference the pram "
"base register instead.\n",
port->port.line);
return pram;
}
offset = cpm_dpalloc(PROFF_SMC_SIZE, 64);
out_be16(pram, offset);
iounmap(pram);
return cpm_muram_addr(offset);
}
void cpm_uart_unmap_pram(struct uart_cpm_port *port, void __iomem *pram)
{
if (!IS_SMC(port))
iounmap(pram);
}
#else
void cpm_line_cr_cmd(struct uart_cpm_port *port, int cmd)
{

16
drivers/serial/ucc_uart.c
View File

@ -1270,10 +1270,18 @@ static int ucc_uart_probe(struct of_device *ofdev,
/* Get the UCC number (device ID) */
/* UCCs are numbered 1-7 */
iprop = of_get_property(np, "device-id", NULL);
if (!iprop || (*iprop < 1) || (*iprop > UCC_MAX_NUM)) {
dev_err(&ofdev->dev,
"missing or invalid UCC specified in device tree\n");
iprop = of_get_property(np, "cell-index", NULL);
if (!iprop) {
iprop = of_get_property(np, "device-id", NULL);
if (!iprop) {
dev_err(&ofdev->dev, "UCC is unspecified in "
"device tree\n");
return -EINVAL;
}
}
if ((*iprop < 1) || (*iprop > UCC_MAX_NUM)) {
dev_err(&ofdev->dev, "no support for UCC%u\n", *iprop);
kfree(qe_port);
return -ENODEV;
}

14
include/asm-powerpc/cpm.h
View File

@ -4,6 +4,20 @@
#include <linux/compiler.h>
#include <linux/types.h>
/* Opcodes common to CPM1 and CPM2
*/
#define CPM_CR_INIT_TRX ((ushort)0x0000)
#define CPM_CR_INIT_RX ((ushort)0x0001)
#define CPM_CR_INIT_TX ((ushort)0x0002)
#define CPM_CR_HUNT_MODE ((ushort)0x0003)
#define CPM_CR_STOP_TX ((ushort)0x0004)
#define CPM_CR_GRA_STOP_TX ((ushort)0x0005)
#define CPM_CR_RESTART_TX ((ushort)0x0006)
#define CPM_CR_CLOSE_RX_BD ((ushort)0x0007)
#define CPM_CR_SET_GADDR ((ushort)0x0008)
#define CPM_CR_SET_TIMER ((ushort)0x0008)
#define CPM_CR_STOP_IDMA ((ushort)0x000b)
/* Buffer descriptors used by many of the CPM protocols. */
typedef struct cpm_buf_desc {
ushort cbd_sc; /* Status and Control */

13
include/asm-powerpc/cpm1.h
View File

@ -28,19 +28,6 @@
#define CPM_CR_CHAN ((ushort)0x00f0)
#define CPM_CR_FLG ((ushort)0x0001)
/* Some commands (there are more...later)
*/
#define CPM_CR_INIT_TRX ((ushort)0x0000)
#define CPM_CR_INIT_RX ((ushort)0x0001)
#define CPM_CR_INIT_TX ((ushort)0x0002)
#define CPM_CR_HUNT_MODE ((ushort)0x0003)
#define CPM_CR_STOP_TX ((ushort)0x0004)
#define CPM_CR_GRA_STOP_TX ((ushort)0x0005)
#define CPM_CR_RESTART_TX ((ushort)0x0006)
#define CPM_CR_CLOSE_RX_BD ((ushort)0x0007)
#define CPM_CR_SET_GADDR ((ushort)0x0008)
#define CPM_CR_SET_TIMER CPM_CR_SET_GADDR
/* Channel numbers.
*/
#define CPM_CR_CH_SCC1 ((ushort)0x0000)

11
include/asm-powerpc/cpm2.h
View File

@ -71,18 +71,9 @@
#define CPM_CR_FCC_PAGE(x) (x + 0x04)
/* Some opcodes (there are more...later)
/* CPM2-specific opcodes (see cpm.h for common opcodes)
*/
#define CPM_CR_INIT_TRX ((ushort)0x0000)
#define CPM_CR_INIT_RX ((ushort)0x0001)
#define CPM_CR_INIT_TX ((ushort)0x0002)
#define CPM_CR_HUNT_MODE ((ushort)0x0003)
#define CPM_CR_STOP_TX ((ushort)0x0004)
#define CPM_CR_GRA_STOP_TX ((ushort)0x0005)
#define CPM_CR_RESTART_TX ((ushort)0x0006)
#define CPM_CR_SET_GADDR ((ushort)0x0008)
#define CPM_CR_START_IDMA ((ushort)0x0009)
#define CPM_CR_STOP_IDMA ((ushort)0x000b)
#define mk_cr_cmd(PG, SBC, MCN, OP) \
((PG << 26) | (SBC << 21) | (MCN << 6) | OP)

311
include/asm-powerpc/fsl_lbc.h Normal file
View File

@ -0,0 +1,311 @@
/* Freescale Local Bus Controller
*
* Copyright (c) 2006-2007 Freescale Semiconductor
*
* Authors: Nick Spence <nick.spence@freescale.com>,
* Scott Wood <scottwood@freescale.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_FSL_LBC_H
#define __ASM_FSL_LBC_H
#include <linux/types.h>
#include <linux/spinlock.h>
#include <asm/io.h>
struct fsl_lbc_bank {
__be32 br; /**< Base Register */
#define BR_BA 0xFFFF8000
#define BR_BA_SHIFT 15
#define BR_PS 0x00001800
#define BR_PS_SHIFT 11
#define BR_PS_8 0x00000800 /* Port Size 8 bit */
#define BR_PS_16 0x00001000 /* Port Size 16 bit */
#define BR_PS_32 0x00001800 /* Port Size 32 bit */
#define BR_DECC 0x00000600
#define BR_DECC_SHIFT 9
#define BR_DECC_OFF 0x00000000 /* HW ECC checking and generation off */
#define BR_DECC_CHK 0x00000200 /* HW ECC checking on, generation off */
#define BR_DECC_CHK_GEN 0x00000400 /* HW ECC checking and generation on */
#define BR_WP 0x00000100
#define BR_WP_SHIFT 8
#define BR_MSEL 0x000000E0
#define BR_MSEL_SHIFT 5
#define BR_MS_GPCM 0x00000000 /* GPCM */
#define BR_MS_FCM 0x00000020 /* FCM */
#define BR_MS_SDRAM 0x00000060 /* SDRAM */
#define BR_MS_UPMA 0x00000080 /* UPMA */
#define BR_MS_UPMB 0x000000A0 /* UPMB */
#define BR_MS_UPMC 0x000000C0 /* UPMC */
#define BR_V 0x00000001
#define BR_V_SHIFT 0
#define BR_RES ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V)
__be32 or; /**< Base Register */
#define OR0 0x5004
#define OR1 0x500C
#define OR2 0x5014
#define OR3 0x501C
#define OR4 0x5024
#define OR5 0x502C
#define OR6 0x5034
#define OR7 0x503C
#define OR_FCM_AM 0xFFFF8000
#define OR_FCM_AM_SHIFT 15
#define OR_FCM_BCTLD 0x00001000
#define OR_FCM_BCTLD_SHIFT 12
#define OR_FCM_PGS 0x00000400
#define OR_FCM_PGS_SHIFT 10
#define OR_FCM_CSCT 0x00000200
#define OR_FCM_CSCT_SHIFT 9
#define OR_FCM_CST 0x00000100
#define OR_FCM_CST_SHIFT 8
#define OR_FCM_CHT 0x00000080
#define OR_FCM_CHT_SHIFT 7
#define OR_FCM_SCY 0x00000070
#define OR_FCM_SCY_SHIFT 4
#define OR_FCM_SCY_1 0x00000010
#define OR_FCM_SCY_2 0x00000020
#define OR_FCM_SCY_3 0x00000030
#define OR_FCM_SCY_4 0x00000040
#define OR_FCM_SCY_5 0x00000050
#define OR_FCM_SCY_6 0x00000060
#define OR_FCM_SCY_7 0x00000070
#define OR_FCM_RST 0x00000008
#define OR_FCM_RST_SHIFT 3
#define OR_FCM_TRLX 0x00000004
#define OR_FCM_TRLX_SHIFT 2
#define OR_FCM_EHTR 0x00000002
#define OR_FCM_EHTR_SHIFT 1
};
struct fsl_lbc_regs {
struct fsl_lbc_bank bank[8];
u8 res0[0x28];
__be32 mar; /**< UPM Address Register */
u8 res1[0x4];
__be32 mamr; /**< UPMA Mode Register */
#define MxMR_OP_NO (0 << 28) /**< normal operation */
#define MxMR_OP_WA (1 << 28) /**< write array */
#define MxMR_OP_RA (2 << 28) /**< read array */
#define MxMR_OP_RP (3 << 28) /**< run pattern */
#define MxMR_MAD 0x3f /**< machine address */
__be32 mbmr; /**< UPMB Mode Register */
__be32 mcmr; /**< UPMC Mode Register */
u8 res2[0x8];
__be32 mrtpr; /**< Memory Refresh Timer Prescaler Register */
__be32 mdr; /**< UPM Data Register */
u8 res3[0x4];
__be32 lsor; /**< Special Operation Initiation Register */
__be32 lsdmr; /**< SDRAM Mode Register */
u8 res4[0x8];
__be32 lurt; /**< UPM Refresh Timer */
__be32 lsrt; /**< SDRAM Refresh Timer */
u8 res5[0x8];
__be32 ltesr; /**< Transfer Error Status Register */
#define LTESR_BM 0x80000000
#define LTESR_FCT 0x40000000
#define LTESR_PAR 0x20000000
#define LTESR_WP 0x04000000
#define LTESR_ATMW 0x00800000
#define LTESR_ATMR 0x00400000
#define LTESR_CS 0x00080000
#define LTESR_CC 0x00000001
#define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC)
__be32 ltedr; /**< Transfer Error Disable Register */
__be32 lteir; /**< Transfer Error Interrupt Register */
__be32 lteatr; /**< Transfer Error Attributes Register */
__be32 ltear; /**< Transfer Error Address Register */
u8 res6[0xC];
__be32 lbcr; /**< Configuration Register */
#define LBCR_LDIS 0x80000000
#define LBCR_LDIS_SHIFT 31
#define LBCR_BCTLC 0x00C00000
#define LBCR_BCTLC_SHIFT 22
#define LBCR_AHD 0x00200000
#define LBCR_LPBSE 0x00020000
#define LBCR_LPBSE_SHIFT 17
#define LBCR_EPAR 0x00010000
#define LBCR_EPAR_SHIFT 16
#define LBCR_BMT 0x0000FF00
#define LBCR_BMT_SHIFT 8
#define LBCR_INIT 0x00040000
__be32 lcrr; /**< Clock Ratio Register */
#define LCRR_DBYP 0x80000000
#define LCRR_DBYP_SHIFT 31
#define LCRR_BUFCMDC 0x30000000
#define LCRR_BUFCMDC_SHIFT 28
#define LCRR_ECL 0x03000000
#define LCRR_ECL_SHIFT 24
#define LCRR_EADC 0x00030000
#define LCRR_EADC_SHIFT 16
#define LCRR_CLKDIV 0x0000000F
#define LCRR_CLKDIV_SHIFT 0
u8 res7[0x8];
__be32 fmr; /**< Flash Mode Register */
#define FMR_CWTO 0x0000F000
#define FMR_CWTO_SHIFT 12
#define FMR_BOOT 0x00000800
#define FMR_ECCM 0x00000100
#define FMR_AL 0x00000030
#define FMR_AL_SHIFT 4
#define FMR_OP 0x00000003
#define FMR_OP_SHIFT 0
__be32 fir; /**< Flash Instruction Register */
#define FIR_OP0 0xF0000000
#define FIR_OP0_SHIFT 28
#define FIR_OP1 0x0F000000
#define FIR_OP1_SHIFT 24
#define FIR_OP2 0x00F00000
#define FIR_OP2_SHIFT 20
#define FIR_OP3 0x000F0000
#define FIR_OP3_SHIFT 16
#define FIR_OP4 0x0000F000
#define FIR_OP4_SHIFT 12
#define FIR_OP5 0x00000F00
#define FIR_OP5_SHIFT 8
#define FIR_OP6 0x000000F0
#define FIR_OP6_SHIFT 4
#define FIR_OP7 0x0000000F
#define FIR_OP7_SHIFT 0
#define FIR_OP_NOP 0x0 /* No operation and end of sequence */
#define FIR_OP_CA 0x1 /* Issue current column address */
#define FIR_OP_PA 0x2 /* Issue current block+page address */
#define FIR_OP_UA 0x3 /* Issue user defined address */
#define FIR_OP_CM0 0x4 /* Issue command from FCR[CMD0] */
#define FIR_OP_CM1 0x5 /* Issue command from FCR[CMD1] */
#define FIR_OP_CM2 0x6 /* Issue command from FCR[CMD2] */
#define FIR_OP_CM3 0x7 /* Issue command from FCR[CMD3] */
#define FIR_OP_WB 0x8 /* Write FBCR bytes from FCM buffer */
#define FIR_OP_WS 0x9 /* Write 1 or 2 bytes from MDR[AS] */
#define FIR_OP_RB 0xA /* Read FBCR bytes to FCM buffer */
#define FIR_OP_RS 0xB /* Read 1 or 2 bytes to MDR[AS] */
#define FIR_OP_CW0 0xC /* Wait then issue FCR[CMD0] */
#define FIR_OP_CW1 0xD /* Wait then issue FCR[CMD1] */
#define FIR_OP_RBW 0xE /* Wait then read FBCR bytes */
#define FIR_OP_RSW 0xE /* Wait then read 1 or 2 bytes */
__be32 fcr; /**< Flash Command Register */
#define FCR_CMD0 0xFF000000
#define FCR_CMD0_SHIFT 24
#define FCR_CMD1 0x00FF0000
#define FCR_CMD1_SHIFT 16
#define FCR_CMD2 0x0000FF00
#define FCR_CMD2_SHIFT 8
#define FCR_CMD3 0x000000FF
#define FCR_CMD3_SHIFT 0
__be32 fbar; /**< Flash Block Address Register */
#define FBAR_BLK 0x00FFFFFF
__be32 fpar; /**< Flash Page Address Register */
#define FPAR_SP_PI 0x00007C00
#define FPAR_SP_PI_SHIFT 10
#define FPAR_SP_MS 0x00000200
#define FPAR_SP_CI 0x000001FF
#define FPAR_SP_CI_SHIFT 0
#define FPAR_LP_PI 0x0003F000
#define FPAR_LP_PI_SHIFT 12
#define FPAR_LP_MS 0x00000800
#define FPAR_LP_CI 0x000007FF
#define FPAR_LP_CI_SHIFT 0
__be32 fbcr; /**< Flash Byte Count Register */
#define FBCR_BC 0x00000FFF
u8 res11[0x8];
u8 res8[0xF00];
};
extern struct fsl_lbc_regs __iomem *fsl_lbc_regs;
extern spinlock_t fsl_lbc_lock;
/*
* FSL UPM routines
*/
struct fsl_upm {
__be32 __iomem *mxmr;
int width;
};
extern int fsl_lbc_find(phys_addr_t addr_base);
extern int fsl_upm_find(phys_addr_t addr_base, struct fsl_upm *upm);
/**
* fsl_upm_start_pattern - start UPM patterns execution
* @upm: pointer to the fsl_upm structure obtained via fsl_upm_find
* @pat_offset: UPM pattern offset for the command to be executed
*
* This routine programmes UPM so the next memory access that hits an UPM
* will trigger pattern execution, starting at pat_offset.
*/
static inline void fsl_upm_start_pattern(struct fsl_upm *upm, u8 pat_offset)
{
clrsetbits_be32(upm->mxmr, MxMR_MAD, MxMR_OP_RP | pat_offset);
}
/**
* fsl_upm_end_pattern - end UPM patterns execution
* @upm: pointer to the fsl_upm structure obtained via fsl_upm_find
*
* This routine reverts UPM to normal operation mode.
*/
static inline void fsl_upm_end_pattern(struct fsl_upm *upm)
{
clrbits32(upm->mxmr, MxMR_OP_RP);
while (in_be32(upm->mxmr) & MxMR_OP_RP)
cpu_relax();
}
/**
* fsl_upm_run_pattern - actually run an UPM pattern
* @upm: pointer to the fsl_upm structure obtained via fsl_upm_find
* @io_base: remapped pointer to where memory access should happen
* @mar: MAR register content during pattern execution
*
* This function triggers dummy write to the memory specified by the io_base,
* thus UPM pattern actually executed. Note that mar usage depends on the
* pre-programmed AMX bits in the UPM RAM.
*/
static inline int fsl_upm_run_pattern(struct fsl_upm *upm,
void __iomem *io_base, u32 mar)
{
int ret = 0;
unsigned long flags;
spin_lock_irqsave(&fsl_lbc_lock, flags);
out_be32(&fsl_lbc_regs->mar, mar << (32 - upm->width));
switch (upm->width) {
case 8:
out_8(io_base, 0x0);
break;
case 16:
out_be16(io_base, 0x0);
break;
case 32:
out_be32(io_base, 0x0);
break;
default:
ret = -EINVAL;
break;
}
spin_unlock_irqrestore(&fsl_lbc_lock, flags);
return ret;
}
#endif /* __ASM_FSL_LBC_H */

3
include/asm-powerpc/immap_qe.h
View File

@ -20,6 +20,7 @@
#ifdef __KERNEL__
#include <linux/kernel.h>
#include <asm/io.h>
#define QE_IMMAP_SIZE (1024 * 1024) /* 1MB from 1MB+IMMR */
@ -468,7 +469,7 @@ struct qe_immap {
u8 res18[0xC0000]; /* 0x140000 - 0x200000 */
} __attribute__ ((packed));
extern struct qe_immap *qe_immr;
extern struct qe_immap __iomem *qe_immr;
extern phys_addr_t get_qe_base(void);
static inline unsigned long immrbar_virt_to_phys(void *address)

12
include/asm-powerpc/qe.h
View File

@ -85,6 +85,7 @@ extern int par_io_data_set(u8 port, u8 pin, u8 val);
/* QE internal API */
int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input);
enum qe_clock qe_clock_source(const char *source);
unsigned int qe_get_brg_clk(void);
int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier);
int qe_get_snum(void);
void qe_put_snum(u8 snum);
@ -92,7 +93,16 @@ unsigned long qe_muram_alloc(int size, int align);
int qe_muram_free(unsigned long offset);
unsigned long qe_muram_alloc_fixed(unsigned long offset, int size);
void qe_muram_dump(void);
void *qe_muram_addr(unsigned long offset);
static inline void __iomem *qe_muram_addr(unsigned long offset)
{
return (void __iomem *)&qe_immr->muram[offset];
}
static inline unsigned long qe_muram_offset(void __iomem *addr)
{
return addr - (void __iomem *)qe_immr->muram;
}
/* Structure that defines QE firmware binary files.
*