openkylin
/
linux
mirror of https://gitee.com/openkylin/linux.git
9
0
Fork 0
Code Issues Projects Releases Wiki Activity

bnx2x: Do not enable CL37 BAM unless it is explicitly enabled 

Enabling CL37 BAM on BCM8073 by default may lead to link issues since
not all switches support it. So enable CL37 BAM only if explicitly
selected.

Signed-off-by: Yaniv Rosner <yanivr@broadcom.com>
Signed-off-by: Eilon Greenstein <eilong@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Yaniv Rosner 2010-11-01 05:32:38 +00:00 committed by David S. Miller
parent 650154bfd1
commit 121839beac
2 changed files with 20 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
drivers/net/bnx2x/bnx2x_hsi.h
View File

@ -244,7 +244,14 @@ struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */
u16 xgxs_config_tx[4]; /* 0x1A0 */ u16 xgxs_config_tx[4]; /* 0x1A0 */
u32 Reserved1[57]; /* 0x1A8 */ u32 Reserved1[56]; /* 0x1A8 */
u32 default_cfg; /* 0x288 */
/* Enable BAM on KR */
#define PORT_HW_CFG_ENABLE_BAM_ON_KR_MASK 0x00100000
#define PORT_HW_CFG_ENABLE_BAM_ON_KR_SHIFT 20
#define PORT_HW_CFG_ENABLE_BAM_ON_KR_DISABLED 0x00000000
#define PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED 0x00100000
u32 speed_capability_mask2; /* 0x28C */ u32 speed_capability_mask2; /* 0x28C */
#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK 0x0000FFFF #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK 0x0000FFFF
#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT 0 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT 0

18
drivers/net/bnx2x/bnx2x_link.c
View File

@ -3525,13 +3525,19 @@ static u8 bnx2x_8073_config_init(struct bnx2x_phy *phy,
DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1); DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
/* Enable CL37 BAM */ /* Enable CL37 BAM */
bnx2x_cl45_read(bp, phy, if (REG_RD(bp, params->shmem_base +
MDIO_AN_DEVAD, offsetof(struct shmem_region, dev_info.
MDIO_AN_REG_8073_BAM, &val); port_hw_config[params->port].default_cfg)) &
bnx2x_cl45_write(bp, phy, PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
MDIO_AN_DEVAD,
MDIO_AN_REG_8073_BAM, val | 1);
bnx2x_cl45_read(bp, phy,
MDIO_AN_DEVAD,
MDIO_AN_REG_8073_BAM, &val);
bnx2x_cl45_write(bp, phy,
MDIO_AN_DEVAD,
MDIO_AN_REG_8073_BAM, val | 1);
DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
}
if (params->loopback_mode == LOOPBACK_EXT) { if (params->loopback_mode == LOOPBACK_EXT) {
bnx2x_807x_force_10G(bp, phy); bnx2x_807x_force_10G(bp, phy);
DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n"); DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n");