mirror of https://gitee.com/openkylin/linux.git
crypto: ccp - Base AXI DMA cache settings on device tree
The default cache operations for ARM64 were changed during 3.15. To use coherent operations a "dma-coherent" device tree property is required. If that property is not present in the device tree node then the non-coherent operations are assigned for the device. Add support to the ccp driver to assign the AXI DMA cache settings based on whether the "dma-coherent" property is present in the device node. If present, use settings that work with the caches. If not present, use settings that do not look at the caches. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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@ -7,6 +7,9 @@ Required properties:
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that services interrupts for this device
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that services interrupts for this device
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- interrupts: Should contain the CCP interrupt
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- interrupts: Should contain the CCP interrupt
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Optional properties:
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- dma-coherent: Present if dma operations are coherent
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Example:
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Example:
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ccp@e0100000 {
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ccp@e0100000 {
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compatible = "amd,ccp-seattle-v1a";
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compatible = "amd,ccp-seattle-v1a";
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@ -3,6 +3,7 @@ config CRYPTO_DEV_CCP_DD
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depends on CRYPTO_DEV_CCP
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depends on CRYPTO_DEV_CCP
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default m
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default m
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select HW_RANDOM
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select HW_RANDOM
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select OF if ARM64
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help
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help
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Provides the interface to use the AMD Cryptographic Coprocessor
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Provides the interface to use the AMD Cryptographic Coprocessor
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which can be used to accelerate or offload encryption operations
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which can be used to accelerate or offload encryption operations
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@ -364,7 +364,7 @@ int ccp_init(struct ccp_device *ccp)
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#ifdef CONFIG_ARM64
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#ifdef CONFIG_ARM64
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/* For arm64 set the recommended queue cache settings */
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/* For arm64 set the recommended queue cache settings */
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iowrite32(CACHE_WB_NO_ALLOC, ccp->io_regs + CMD_Q_CACHE_BASE +
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iowrite32(ccp->axcache, ccp->io_regs + CMD_Q_CACHE_BASE +
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(CMD_Q_CACHE_INC * i));
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(CMD_Q_CACHE_INC * i));
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#endif
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#endif
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@ -30,6 +30,7 @@
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#define TRNG_RETRIES 10
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#define TRNG_RETRIES 10
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#define CACHE_NONE 0x00
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#define CACHE_WB_NO_ALLOC 0xb7
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#define CACHE_WB_NO_ALLOC 0xb7
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@ -255,6 +256,9 @@ struct ccp_device {
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/* Suspend support */
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/* Suspend support */
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unsigned int suspending;
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unsigned int suspending;
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wait_queue_head_t suspend_queue;
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wait_queue_head_t suspend_queue;
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/* DMA caching attribute support */
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unsigned int axcache;
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};
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};
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@ -22,6 +22,7 @@
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#include <linux/spinlock.h>
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#include <linux/spinlock.h>
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#include <linux/delay.h>
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#include <linux/delay.h>
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#include <linux/ccp.h>
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#include <linux/ccp.h>
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#include <linux/of.h>
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#include "ccp-dev.h"
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#include "ccp-dev.h"
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@ -112,6 +113,11 @@ static int ccp_platform_probe(struct platform_device *pdev)
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*(dev->dma_mask) = DMA_BIT_MASK(48);
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*(dev->dma_mask) = DMA_BIT_MASK(48);
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dev->coherent_dma_mask = DMA_BIT_MASK(48);
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dev->coherent_dma_mask = DMA_BIT_MASK(48);
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if (of_property_read_bool(dev->of_node, "dma-coherent"))
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ccp->axcache = CACHE_WB_NO_ALLOC;
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else
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ccp->axcache = CACHE_NONE;
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dev_set_drvdata(dev, ccp);
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dev_set_drvdata(dev, ccp);
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ret = ccp_init(ccp);
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ret = ccp_init(ccp);
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